Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
stm32h7: simplify generic SPI driver
Supporting large transfers (>64k) isn't really needed;
the main use case right now is interfacing with an LCD
controller.
Change-Id: I901e5ddb1b4efa9aa650b3e5074537ba785c6d41
authored by
Aidan MacDonald
and committed by
Solomon Peachy
8d279aa4
09a31fff
+15
-80
+2
-1
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.c
+2
-1
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.c
···
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#include "spi-stm32h7.h"
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#include "gpio-stm32h7.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/spi.h"
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struct stm_spi_config spi_cfg = {
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.num = STM_SPI5,
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.instance = ITA_SPI5,
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.mode = STM_SPIMODE_HALF_DUPLEX,
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.proto = STM_SPIPROTO_MOTOROLA,
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.frame_bits = 9,
+11
-66
firmware/target/arm/stm32/spi-stm32h7.c
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-66
firmware/target/arm/stm32/spi-stm32h7.c
···
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****************************************************************************/
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#include "spi-stm32h7.h"
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#include "regs/stm32h743/spi.h"
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#include "panic.h"
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/*
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* Align the max transfer size to ensure it will always be a multiple
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* of 32 bits. This is necessary because an unaligned TSIZE will cause
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* some data written to the FIFO to be ignored -- this is OK and the
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* intended behavior when it happens at the end of the transfer. But
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* we don't want this to happen when TSER > 0 when we're still in the
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* middle of the transfer, as it will throw away valid data.
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* some data written to the FIFO to be ignored.
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*/
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#define TSIZE_MAX \
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ALIGN_DOWN(reg_vreadf(BM_SPI_CR2_TSIZE, SPI_CR2, TSIZE), sizeof(uint32_t))
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static struct stm_spi *spi_map[STM_SPI_COUNT];
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static const uint32_t spi_addr[STM_SPI_COUNT] INITDATA_ATTR = {
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[STM_SPI1] = ITA_SPI1,
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[STM_SPI2] = ITA_SPI2,
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[STM_SPI3] = ITA_SPI3,
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[STM_SPI4] = ITA_SPI4,
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[STM_SPI5] = ITA_SPI5,
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[STM_SPI6] = ITA_SPI6,
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};
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ALIGN_DOWN(BM_SPI_CR2_TSIZE >> BP_SPI_CR2_TSIZE, sizeof(uint32_t))
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static void stm_spi_set_cs(struct stm_spi *spi, bool enable)
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{
···
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static void stm_spi_enable(struct stm_spi *spi, bool hd_tx, size_t size)
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{
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size_t tsize = size / spi->frame_size;
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size_t tser = 0;
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size_t left = 0;
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if (tsize > TSIZE_MAX)
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{
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tser = tsize - TSIZE_MAX;
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tsize = TSIZE_MAX;
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if (tser > TSIZE_MAX)
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{
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left = tser - TSIZE_MAX;
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tser = TSIZE_MAX;
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}
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}
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/*
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* Save number of bytes left for next TSER load, tracked
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* separately from the overall transfer size because the
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* timing of the SPI_SR.TSERF interrupt isn't clear. We'll
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* decrement this by TSIZE_MAX whenever we load TSER in the
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* middle of a transfer.
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*/
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spi->tser_left = left;
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panicf("%s: tsize > TSIZE_MAX", __func__);
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/* TSIZE must be programmed before setting SPE. */
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reg_assignlf(spi->regs, SPI_CR2, TSIZE(tsize), TSER(tser));
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reg_assignlf(spi->regs, SPI_CR2, TSIZE(tsize), TSER(0));
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reg_writelf(spi->regs, SPI_CR1, HDDIR(hd_tx), SPE(1));
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}
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···
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{
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uint32_t ftlevel;
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spi->regs = spi_addr[config->num];
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spi->regs = config->instance;
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spi->mode = config->mode;
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spi->set_cs = config->set_cs;
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···
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* So we can double the threshold setting for SPI1-3.
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* (Maximum allowable threshold is 1/2 the FIFO size.)
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*/
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if (config->num <= STM_SPI3)
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if (config->instance == ITA_SPI1 ||
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config->instance == ITA_SPI2 ||
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config->instance == ITA_SPI3)
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{
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ftlevel *= 2;
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}
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/* TODO: allow setting MBR here */
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reg_writelf(spi->regs, SPI_CFG1,
···
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IOSWP(config->swap_mosi_miso),
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MIDI(0),
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MSSI(0));
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spi_map[config->num] = spi;
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}
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int stm_spi_xfer(struct stm_spi *spi, size_t size,
···
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{
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uint32_t sr = reg_readl(spi->regs, SPI_SR);
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/*
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* Handle continuation of large transfers
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*
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* TODO - something is not right with this code
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*/
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if (spi->tser_left > 0 && reg_vreadf(sr, SPI_SR, TSERF))
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{
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if (spi->tser_left < TSIZE_MAX)
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{
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reg_writelf(spi->regs, SPI_CR2, TSER(spi->tser_left));
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spi->tser_left = 0;
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}
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else
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{
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reg_writelf(spi->regs, SPI_CR2, TSER(TSIZE_MAX));
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spi->tser_left -= TSIZE_MAX;
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}
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}
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/* Handle FIFO write */
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if (size_tx > 0 && reg_vreadf(sr, SPI_SR, TXP))
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{
···
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stm_spi_set_cs(spi, false);
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return 0;
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}
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void spi_irq_handler(void)
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{
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while (1);
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}
+2
-13
firmware/target/arm/stm32/spi-stm32h7.h
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-13
firmware/target/arm/stm32/spi-stm32h7.h
···
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struct stm_spi;
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enum stm_spi_num
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{
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STM_SPI1,
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STM_SPI2,
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STM_SPI3,
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STM_SPI4,
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STM_SPI5,
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STM_SPI6,
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STM_SPI_COUNT,
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};
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/* Must match the SPI_CFG2.COMM register */
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enum stm_spi_mode
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{
···
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struct stm_spi_config
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{
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enum stm_spi_num num;
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/* Peripheral instance base address; one of ITA_SPIx */
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uint32_t instance;
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enum stm_spi_mode mode;
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enum stm_spi_protocol proto;
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stm_spi_set_cs_t set_cs;
···
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enum stm_spi_mode mode;
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stm_spi_set_cs_t set_cs;
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uint32_t frame_size;
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size_t tser_left;
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};
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void stm_spi_init(struct stm_spi *spi,