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Sansa Connect: Fix reported CPU frequency
Make frequency related comments accurate. Disable UART0 clock.
Change-Id: I224a3d6656ad53165dcff68ed716fa2c6863240d
+66
-30
+4
-1
firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c
+4
-1
firmware/target/arm/tms320dm320/sansa-connect/avr-sansaconnect.c
···
501
501
bitclr16(&IO_GIO_DIR2, (1 << 0));
502
502
avr_hid_release();
503
503
504
-
/* RATE = 219 (0xDB) -> 200 kHz */
504
+
/* Master, MSB first, RATE = 219 (Bit rate = ARM clock / 2*(RATE + 1)))
505
+
* Boosted 148.5 MHz / 440 = 337.5 kHz
506
+
* Default 74.25 MHz / 440 = 168.75 kHz
507
+
*/
505
508
IO_SERIAL1_MODE = 0x6DB;
506
509
507
510
mutex_init(&avr_mtx);
+41
-23
firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
+41
-23
firmware/target/arm/tms320dm320/sansa-connect/crt0-board.S
···
58
58
/* Setup the EMIF interface timings */
59
59
60
60
/* FLASH interface:
61
-
* These are based on the OF setup
61
+
* These are based on the OF setup
62
62
*/
63
63
/* IO_EMIF_CS0CTRL1 and
64
-
* IO_EMIF_CS0CTRL2
64
+
* IO_EMIF_CS0CTRL2
65
65
*/
66
66
mwh 0x30A00, 0x889A
67
67
mwh 0x30A02, 0x1110
···
75
75
mwh 0x30A0E, 0x0222
76
76
77
77
/* IO_EMIF_CS3CTRL1 and
78
-
* IO_EMIF_CS3CTRL2
78
+
* IO_EMIF_CS3CTRL2
79
79
*/
80
80
mwh 0x30A10, 0x8899
81
81
mwh 0x30A12, 0x5110
···
96
96
_clock_setup:
97
97
/* Clock initialization */
98
98
99
+
/* Disable peripheral clocks */
100
+
mwhm 0x3089A, 0
101
+
mwhm 0x3089C, 0
102
+
99
103
/* IO_CLK_BYP: Bypass the PLLs for the following changes */
100
104
mwh 0x30894, 0x1111
101
105
102
106
/*
103
-
* IO_CLK_PLLA
104
-
* IO_CLK_PLLB
107
+
* IO_CLK_PLLA: 27 MHz * 11 / 1 = 297 MHz
108
+
* IO_CLK_PLLB: 27 MHz
105
109
*/
106
-
mwhm 0x30880, 0x00A0
110
+
mwh 0x30880, 0x10A0
107
111
mwhm 0x30882, 0x1000
108
112
109
-
/* IO_CLK_SEL0 */
113
+
/* IO_CLK_SEL0: Timer 0 and 1, UART 0 and 1 from PLLIN (27 MHz) */
110
114
mwh 0x30884, 0x0066
111
115
112
-
/* IO_CLK_SEL1 */
116
+
/* IO_CLK_SEL1: VENC from PLLA, OSD clock = VENC clock / 2 */
113
117
mwhm 0x30886, 0x0003
114
118
115
-
# IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */
119
+
/* IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */
116
120
mwh 0x30888, 0
117
121
118
-
/* IO_CLK_DIV0: Set the slow clock speed for the ARM/AHB */
122
+
/* IO_CLK_DIV0: Set the fast clock speed for the ARM/AHB
123
+
* ARM = PLLA / 2 = 148.5 MHz
124
+
* AHB = ARM / 2 = 74.25 MHz
125
+
*/
119
126
mwh 0x3088A, 0x0101
120
127
121
-
/* IO_CLK_DIV1: Accelerator, SDRAM */
128
+
/* IO_CLK_DIV1: Accelerator, SDRAM
129
+
* AXL = PLLA / 2 = 148.5 MHz
130
+
* SDRAM = PLLA / 3 = 99 MHz
131
+
*/
122
132
mwh 0x3088C, 0x0102
123
133
124
134
/* IO_CLK_DIV2: DSP, MS Clock
125
135
* OF must be booted with this value
136
+
* DSP = PLLA / 3 = 99 MHz
137
+
* MS = PLLA / 1 = 297 MHz
126
138
*/
127
139
mwhm 0x3088E, 0x0200
128
140
129
-
# PLLA &= ~0x1000 (BIC #0x1000)
141
+
/* PLLA &= ~0x1000 (BIC #0x1000) */
130
142
mrh 0x30880
131
143
bic r0, r0, #0x1000
132
144
strh r0, [r1]
···
141
153
/* IO_CLK_BYP: Enable PLL feeds */
142
154
mwhm 0x30894, 0x0
143
155
144
-
/* IO_CLK_MOD0 */
156
+
/* IO_CLK_MOD0
157
+
* Enable clocks:
158
+
* ARM, Bus Controller, AHB, ARM internal memory, EMIF, SDRAM
159
+
* Disable clocks:
160
+
* ETM, E2ICE, INTC, EXTHOST, DSP, HPIB
161
+
*/
145
162
mwh 0x30898, 0x01A7
146
163
147
-
/* IO_CLK_MOD1 */
148
-
mwhm 0x3089A, 0x18
149
-
150
-
/* IO_CLK_MOD2 */
151
-
mwhm 0x3089C, 0x4A0
164
+
/* IO_CLK_MOD2: Enable GIO and SIF1 clocks */
165
+
mwhm 0x3089C, 0x0420
152
166
153
167
/* Setup the SDRAM range on the AHB bus */
154
168
/* SDRAMSA */
155
169
mov r0, #0x60000
156
170
mov r1, #0x1000000
157
171
str r1, [r0, #0xF00]
158
-
172
+
159
173
/* SDRAMEA: 64MB */
160
174
mov r1, #0x5000000
161
175
str r1, [r0, #0xF04]
162
-
176
+
163
177
/* SDRC_REFCTL */
164
178
mwh 0x309A8, 0
165
179
···
183
197
184
198
mwhm 0x309A8, 0x0140
185
199
200
+
/* IMGBUF SDRAM priority bit 2 set */
186
201
mwhm 0x309BE, 0x4
202
+
/* SDRAM refresh priority bit 1 set */
187
203
mwhm 0x309BC, 0x2
204
+
/* Use defined priority bits */
188
205
ldr r0, =0x309C4
189
206
ldr r1, [r0]
190
207
orr r1, r1, #1
···
198
215
orr r1, r1, #0x40
199
216
strh r1, [r0]
200
217
218
+
/* Enable auto refresh with interval (64 + 1) * 8 SDRAM clocks */
201
219
mwhm 0x309A8, 0x0140
202
220
203
221
/* Go through the GPIO initialization */
204
-
/* Warning: setting some of the functions wrong will make OF unable
222
+
/* Warning: setting some of the functions wrong will make OF unable
205
223
to boot (freeze during startup) */
206
224
/* IO_GIO_FSEL0: Set up the GPIO pin functions 0-16 */
207
225
mwhm 0x305A4, 0xC000
···
223
241
224
242
/* IO_GIO_DIR2 */
225
243
mwh 0x30584, 0x01FD
226
-
244
+
227
245
/* IO_GIO_INV0 */
228
246
mwh 0x30586, 0x0000
229
247
···
235
253
236
254
bx lr
237
255
238
-
.ltorg
256
+
.ltorg
239
257
.size _init_board, .-_init_board
240
258
+1
-1
firmware/target/arm/tms320dm320/sansa-connect/lcd-sansaconnect.c
+1
-1
firmware/target/arm/tms320dm320/sansa-connect/lcd-sansaconnect.c
···
141
141
VENC Clock from PLLA */
142
142
IO_CLK_SEL1 = 0x3;
143
143
144
-
/* Set VENC Clock Division to 11
144
+
/* Set VENC Clock Division to 11 (PLLA / 11 = 297 MHz / 11 = 27 MHz)
145
145
OF bootloader sets division to 8, vmlinux sets it to 11 */
146
146
IO_CLK_DIV3 = (IO_CLK_DIV3 & ~(0x1F00)) | 0xB00;
147
147
+3
-1
firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c
+3
-1
firmware/target/arm/tms320dm320/sansa-connect/wifi-sansaconnect.c
···
40
40
IO_SERIAL0_TX_ENABLE = 0x0001;
41
41
42
42
/* SELSDEN = 0, SLVEN = 0, SIOCLR = 0, SCLKM = 1, MSB = 1, MSSEL = 0,
43
-
* RATE = 2 -> 15MHz
43
+
* RATE = 1 (Bit rate = ARM clock / 2*(RATE + 1)))
44
+
* Boosted 148.5 MHz / 4 = 37.125 MHz
45
+
* Default 74.25 MHz / 4 = 18.5625 MHz
44
46
*/
45
47
IO_SERIAL0_MODE = 0x0601;
46
48
+3
-2
firmware/target/arm/tms320dm320/sdmmc-dm320.c
+3
-2
firmware/target/arm/tms320dm320/sdmmc-dm320.c
···
805
805
bitclr16(&IO_CLK_MOD2, CLK_MOD2_MMC);
806
806
bitset16(&IO_CLK_INV, CLK_INV_MMC);
807
807
808
-
/* mmc module clock: 75 Mhz (AHB) / 2 = ~37.5 Mhz
809
-
* (Frequencies above are taken from Sansa Connect's OF source code) */
808
+
/* mmc module clock when boosted 74.25 Mhz (AHB) / 2 = 37.125 Mhz
809
+
* default 37.125 (AHB) / 2 = 18.5625 MHz
810
+
* (Frequencies above are valid for Sansa Connect) */
810
811
IO_CLK_DIV3 = (IO_CLK_DIV3 & 0xFF00) | 0x01;
811
812
812
813
bitset16(&IO_CLK_MOD2, CLK_MOD2_MMC);
+8
-1
firmware/target/arm/tms320dm320/system-dm320.c
+8
-1
firmware/target/arm/tms320dm320/system-dm320.c
···
312
312
#endif
313
313
{
314
314
#ifdef SANSA_CONNECT
315
-
/* Setting AHB divisor to 0 increases power consumption */
315
+
/* Setting AHB divisor to 0 increases power consumption
316
+
* Slow Setup:
317
+
* ARM div = 4 ( 74.25 MHz )
318
+
* AHB div = 2 ( 37.125 MHz )
319
+
* Fast Setup:
320
+
* ARM div = 2 ( 148.5 MHz )
321
+
* AHB div = 2 ( 74.25 MHz )
322
+
*/
316
323
clock_arm_slow = (1 << 8) | 3;
317
324
clock_arm_fast = (1 << 8) | 1;
318
325
#else
+6
-1
firmware/target/arm/tms320dm320/system-target.h
+6
-1
firmware/target/arm/tms320dm320/system-target.h
···
24
24
#include "system-arm.h"
25
25
#include "mmu-arm.h"
26
26
27
-
#define CPUFREQ_SLEEP 32768
27
+
#ifdef SANSA_CONNECT
28
+
#define CPUFREQ_DEFAULT 74250000
29
+
#define CPUFREQ_NORMAL 74250000
30
+
#define CPUFREQ_MAX 148500000
31
+
#else
28
32
#define CPUFREQ_DEFAULT 87500000
29
33
#define CPUFREQ_NORMAL 87500000
30
34
#define CPUFREQ_MAX 175000000
35
+
#endif
31
36
32
37
void udelay(int usec);
33
38
void mdelay(int msec);