Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
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rust
zig
deno
ipod6g: Move pmu_is_hibernated() from bootloader to PMU driver, misc fixes
Added better comments about the PMU registers, added pmu_set_cpu_voltage() (still unused).
Credit: Cástor Muñoz <cmvidal@gmail.com>
Change-Id: I0ca21a49ece007c913c1b199952009e4dcae80e5
authored by
Vencislav Atanasov
and committed by
Solomon Peachy
9b4bab7e
6b348d7f
+59
-32
-7
bootloader/ipod-s5l87xx.c
-7
bootloader/ipod-s5l87xx.c
···
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return rc;
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}
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static bool pmu_is_hibernated(void)
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{
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/* OF sets GPIO3 to low when SDRAM is hibernated */
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return !(pmu_rd(PCF5063X_REG_GPIO3CFG) & 7) &&
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!(pmu_rd(PCF5063X_REG_OOCSHDWN) & PCF5063X_OOCSHDWN_COLDBOOT);
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}
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/* The boot sequence is executed on power-on or reset. After power-up
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* the device could come from a state of hibernation, OF hibernates
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* the iPod after an inactive period of ~30 minutes (FW 1.1.2), on
+23
firmware/target/arm/s5l8702/ipod6g/pmu-6g.c
+23
firmware/target/arm/s5l8702/ipod6g/pmu-6g.c
···
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pmu_write(0xc, 1);
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void pmu_set_cpu_voltage(bool high)
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{
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pmu_write(PCF5063X_REG_DOWN1OUT,
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high ? 0x13 /*1100mV*/ : 0xf /*1000mV*/);
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}
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#endif
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+
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#if (CONFIG_RTC == RTC_NANO2G)
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void pmu_read_rtc(unsigned char* buffer)
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{
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pmu_read_multiple(0x59, 7, buffer);
···
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{
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pmu_write_multiple(0x59, 7, buffer);
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}
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#endif
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/*
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* ADC
···
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pmu_rd_multiple(PCF5063X_REG_INT1, 5, rd_buf);
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pmu_rd(PCF50635_REG_INT6);
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}
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#ifdef BOOTLOADER
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bool pmu_is_hibernated(void)
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{
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/* OF sets GPIO3 to low when SDRAM is hibernated */
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bool gpio3out, coldboot;
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/* get (previously) configured output selection for GPIO3 */
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gpio3out = (pmu_rd(PCF5063X_REG_GPIO3CFG) & 7);
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/* coldboot: when set, device has been in NoPower state */
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coldboot = (pmu_rd(PCF5063X_REG_OOCSHDWN) & PCF5063X_OOCSHDWN_COLDBOOT);
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return !coldboot && !gpio3out;
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}
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#endif
+36
-25
firmware/target/arm/s5l8702/ipod6g/pmu-target.h
+36
-25
firmware/target/arm/s5l8702/ipod6g/pmu-target.h
···
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#include "pcf5063x.h"
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/* undocummented PMU registers */
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#define PCF50635_REG_INT6 0x85
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#define PCF50635_REG_INT6M 0x86
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#define PCF50635_REG_GPIOSTAT 0x87
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#define PCF50635_REG_INT6 0x85
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#define PCF50635_REG_INT6M 0x86
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#define PCF50635_REG_GPIOSTAT 0x87
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enum pcf50635_reg_int6 {
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PCF50635_INT6_GPIO1 = 0x01, /* TBC */
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PCF50635_INT6_GPIO2 = 0x02,
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PCF50635_INT6_GPIO3 = 0x04, /* TBC */
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};
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enum pcf50635_reg_gpiostat {
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PCF50635_GPIOSTAT_GPIO1 = 0x01, /* TBC */
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PCF50635_GPIOSTAT_GPIO2 = 0x02,
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PCF50635_GPIOSTAT_GPIO3 = 0x04, /* TBC */
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};
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/* GPIO for external PMU interrupt */
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#define GPIO_EINT_PMU 0x7b
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/* LDOs */
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#define LDO_UNK1 1 /* TBC: SoC voltage (USB) */
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#define LDO_UNK2 2 /* TBC: SoC voltage (I/O) */
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/* LDOs - enumeration starts at 1 as pcf50635 DS does */
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#define LDO_UNK1 1 /* SoC voltage (USB+TBC section) */
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#define LDO_UNK2 2 /* SoC voltage (I/O+TBC section) */
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#define LDO_LCD 3
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#define LDO_CODEC 4
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#define LDO_UNK5 5 /* TBC: nano3g NAND */
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#define LDO_UNK5 5 /* not used */
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#define LDO_CWHEEL 6
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#define LDO_ACCY 7 /* HCLDO */
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/*
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* Other LDOs:
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* AUTOLDO: Hard Disk
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* DOWN1: CPU
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* DOWN2: SDRAM
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* MEMLDO: SDRAM self-refresh (TBC)
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* DOWN1: Vcore
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* DOWN2: SDRAM
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* MEMLDO: SDRAM self-refresh (TBC)
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*
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* EXTON inputs:
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* EXTON1: button/holdswitch related (TBC)
···
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* EXTON3: ACCESSORY (Low when present)
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*
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* PMU GPIO:
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* GPIO1: input, Mikey (jack remote ctrl) interrupt (TBC)
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* GPIO1: input, Mikey (jack remote ctrl) interrupt
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* GPIO2: input, hold switch (TBC)
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* GPIO3: output, unknown
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* GPIO3: output, OF uses it as a flag to detect hibernation state,
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* it is unknown where/if this output is connected.
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*/
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struct pmu_adc_channel
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{
···
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uint8_t bias_dly; /* RB ticks */
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};
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void pmu_preinit(void);
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void pmu_init(void);
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unsigned char pmu_read(int address);
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int pmu_write(int address, unsigned char val);
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int pmu_read_multiple(int address, int count, unsigned char* buffer);
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int pmu_write_multiple(int address, int count, unsigned char* buffer);
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unsigned short pmu_read_adc(const struct pmu_adc_channel *ch);
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unsigned short pmu_adc_raw2mv(
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const struct pmu_adc_channel *ch, unsigned short raw);
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void pmu_init(void);
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#ifdef BOOTLOADER
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unsigned char pmu_rd(int address);
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int pmu_wr(int address, unsigned char val);
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int pmu_rd_multiple(int address, int count, unsigned char* buffer);
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int pmu_wr_multiple(int address, int count, unsigned char* buffer);
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bool pmu_is_hibernated(void);
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#endif
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void pmu_ldo_on_in_standby(unsigned int ldo, int onoff);
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void pmu_ldo_set_voltage(unsigned int ldo, unsigned char voltage);
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void pmu_ldo_power_on(unsigned int ldo);
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void pmu_ldo_power_off(unsigned int ldo);
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void pmu_set_wake_condition(unsigned char condition);
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void pmu_enter_standby(void);
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void pmu_hdd_power(bool on);
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void pmu_set_cpu_voltage(bool high);
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#endif
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#if (CONFIG_RTC == RTC_NANO2G)
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void pmu_read_rtc(unsigned char* buffer);
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void pmu_write_rtc(unsigned char* buffer);
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void pmu_hdd_power(bool on);
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#endif
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unsigned short pmu_read_adc(const struct pmu_adc_channel *ch);
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unsigned short pmu_adc_raw2mv(
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const struct pmu_adc_channel *ch, unsigned short raw);
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int pmu_holdswitch_locked(void);
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#if CONFIG_CHARGING
···
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#endif
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#ifdef IPOD_ACCESSORY_PROTOCOL
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int pmu_accessory_present(void);
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#endif
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void pmu_preinit(void);
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#ifdef BOOTLOADER
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unsigned char pmu_rd(int address);
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int pmu_wr(int address, unsigned char val);
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int pmu_rd_multiple(int address, int count, unsigned char* buffer);
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int pmu_wr_multiple(int address, int count, unsigned char* buffer);
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#endif
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#endif /* __PMU_TARGET_H__ */