Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
ipod4g: Explicitly initialize both UARTs
This should allow either accesspory port to be used for IAP comms.
No regressions on an ipodphoto and mini2g through the dock connector,
but I don't have any headset-attached accessories to test against.
Change-Id: If217d8147ee871b20ad5f81ba95542379eb9f2dc
+37
-35
+37
-35
firmware/target/arm/pp/uart-pp.c
+37
-35
firmware/target/arm/pp/uart-pp.c
···
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{
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int tmp;
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-
#if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IPOD_MINI2G)
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+
#if defined(IPOD_NANO) || defined(IPOD_VIDEO)
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+
/* Route the Tx/Rx pins. 5G Ipods. ser0, dock conncetor */
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(*(volatile unsigned long *)(0x7000008C)) &= ~0x0C;
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GPO32_ENABLE &= ~0x0C;
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/* Route the Tx/Rx pins. 4G Ipod, MINI & MINI2G ser1, dock connector */
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base_RBR = &SER0_RBR;
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base_THR = &SER0_THR;
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base_LCR = &SER0_LCR;
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base_LSR = &SER0_LSR;
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base_DLL = &SER0_DLL;
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+
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DEV_EN = DEV_EN | DEV_SER0;
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CPU_HI_INT_DIS = SER0_MASK;
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+
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DEV_RS |= DEV_SER0;
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sleep(1);
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DEV_RS &= ~DEV_SER0;
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+
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SER0_LCR = 0x80; /* Divisor latch enable */
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SER0_DLM = 0x00;
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SER0_LCR = 0x03; /* Divisor latch disable, 8-N-1 */
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SER0_IER = 0x01;
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+
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SER0_FCR = 0x07; /* Tx+Rx FIFO reset and FIFO enable */
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+
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CPU_INT_EN = HI_MASK;
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CPU_HI_INT_EN = SER0_MASK;
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tmp = SER0_RBR;
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+
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serial_bitrate(0);
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#elif defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IPOD_MINI2G)
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/* Route the Tx/Rx pins. 4G Ipods, MINI & MINI2G. ser1, dock connector */
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GPIO_CLEAR_BITWISE(GPIOD_ENABLE, 0x6);
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GPIO_CLEAR_BITWISE(GPIOD_OUTPUT_EN, 0x6);
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···
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CPU_HI_INT_EN = SER1_MASK;
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tmp = SER1_RBR;
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#elif defined(IPOD_NANO) || defined(IPOD_VIDEO)
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/* Route the Tx/Rx pins. 5G Ipod */
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(*(volatile unsigned long *)(0x7000008C)) &= ~0x0C;
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GPO32_ENABLE &= ~0x0C;
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base_RBR = &SER0_RBR;
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base_THR = &SER0_THR;
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base_LCR = &SER0_LCR;
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base_LSR = &SER0_LSR;
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base_DLL = &SER0_DLL;
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DEV_EN = DEV_EN | DEV_SER0;
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CPU_HI_INT_DIS = SER0_MASK;
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-
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DEV_RS |= DEV_SER0;
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sleep(1);
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DEV_RS &= ~DEV_SER0;
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SER0_LCR = 0x80; /* Divisor latch enable */
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SER0_DLM = 0x00;
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SER0_LCR = 0x03; /* Divisor latch disable, 8-N-1 */
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SER0_IER = 0x01;
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SER0_FCR = 0x07; /* Tx+Rx FIFO reset and FIFO enable */
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+
serial_bitrate(0);
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CPU_INT_EN = HI_MASK;
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CPU_HI_INT_EN = SER0_MASK;
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tmp = SER0_RBR;
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#else
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/* Default Route the Tx/Rx pins. 4G Ipod, ser0, top connector */
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-
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/* Route the Tx/Rx pins. 4G Ipod, ser0, top connector */
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GPIO_CLEAR_BITWISE(GPIOC_INT_EN, 0x8);
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GPIO_CLEAR_BITWISE(GPIOC_INT_LEV, 0x8);
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GPIOC_INT_CLR = 0x8;
···
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CPU_HI_INT_EN = SER0_MASK;
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tmp = SER0_RBR;
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serial_bitrate(0);
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+
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#endif
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(void)tmp;
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-
serial_bitrate(0);
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}
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void serial_bitrate(int rate)