Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
imx233: add power debug screen
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31100 a1c6a512-1295-4272-9138-f99709370657
+126
-1
+37
-1
firmware/target/arm/imx233/debug-imx233.c
+37
-1
firmware/target/arm/imx233/debug-imx233.c
···
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#include "font.h"
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#include "adc.h"
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#include "adc-imx233.h"
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#include "power-imx233.h"
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#include "powermgmt.h"
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static struct
···
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}
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}
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bool dbg_hw_info_power(void)
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{
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lcd_setfont(FONT_SYSFIXED);
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while(1)
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{
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int button = get_action(CONTEXT_STD, HZ / 25);
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switch(button)
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{
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case ACTION_STD_NEXT:
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case ACTION_STD_PREV:
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case ACTION_STD_OK:
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case ACTION_STD_MENU:
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lcd_setfont(FONT_UI);
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return true;
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case ACTION_STD_CANCEL:
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lcd_setfont(FONT_UI);
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return false;
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}
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lcd_clear_display();
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struct imx233_power_info_t info = imx233_power_get_info(POWER_INFO_ALL);
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lcd_putsf(0, 0, "VDDD: %d mV linreg: %d", info.vddd, info.vddd_linreg);
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lcd_putsf(0, 1, "VDDA: %d mV linreg: %d", info.vdda, info.vdda_linreg);
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lcd_putsf(0, 2, "VDDIO: %d mV", info.vddio);
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lcd_putsf(0, 3, "VDDMEM: %d mV linreg: %d", info.vddmem, info.vddmem_linreg);
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lcd_putsf(0, 4, "DC-DC: pll: %d freq: %d", info.dcdc_sel_pllclk, info.dcdc_freqsel);
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lcd_update();
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yield();
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}
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}
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bool dbg_hw_info_adc(void)
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{
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lcd_setfont(FONT_SYSFIXED);
···
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bool dbg_hw_info(void)
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{
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return dbg_hw_info_dma() && dbg_hw_info_adc() && dbg_hw_target_info();
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return dbg_hw_info_dma() && dbg_hw_info_adc() && dbg_hw_info_power() &&
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dbg_hw_target_info();
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}
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bool dbg_ports(void)
+41
firmware/target/arm/imx233/power-imx233.c
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firmware/target/arm/imx233/power-imx233.c
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#include "config.h"
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#include "system.h"
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#include "power.h"
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#include "string.h"
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#include "system-target.h"
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#include "usb-target.h"
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···
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{
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return false;
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}
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struct imx233_power_info_t imx233_power_get_info(unsigned flags)
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{
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static int dcdc_freqsel[8] = {
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[HW_POWER_MISC__FREQSEL__RES] = 0,
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[HW_POWER_MISC__FREQSEL__20MHz] = 20000,
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[HW_POWER_MISC__FREQSEL__24MHz] = 24000,
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[HW_POWER_MISC__FREQSEL__19p2MHz] = 19200,
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[HW_POWER_MISC__FREQSEL__14p4MHz] = 14200,
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[HW_POWER_MISC__FREQSEL__18MHz] = 18000,
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[HW_POWER_MISC__FREQSEL__21p6MHz] = 21600,
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[HW_POWER_MISC__FREQSEL__17p28MHz] = 17280,
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};
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struct imx233_power_info_t s;
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memset(&s, 0, sizeof(s));
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if(flags & POWER_INFO_VDDD)
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{
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s.vddd = HW_POWER_VDDDCTRL__TRG_MIN + HW_POWER_VDDDCTRL__TRG_STEP * __XTRACT(HW_POWER_VDDDCTRL, TRG);
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s.vddd_linreg = HW_POWER_VDDDCTRL & HW_POWER_VDDDCTRL__ENABLE_LINREG;
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}
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if(flags & POWER_INFO_VDDA)
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{
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s.vdda = HW_POWER_VDDACTRL__TRG_MIN + HW_POWER_VDDACTRL__TRG_STEP * __XTRACT(HW_POWER_VDDACTRL, TRG);
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s.vdda_linreg = HW_POWER_VDDACTRL & HW_POWER_VDDACTRL__ENABLE_LINREG;
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}
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if(flags & POWER_INFO_VDDIO)
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s.vddio = HW_POWER_VDDIOCTRL__TRG_MIN + HW_POWER_VDDIOCTRL__TRG_STEP * __XTRACT(HW_POWER_VDDIOCTRL, TRG);
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if(flags & POWER_INFO_VDDMEM)
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{
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s.vddmem = HW_POWER_VDDMEMCTRL__TRG_MIN + HW_POWER_VDDMEMCTRL__TRG_STEP * __XTRACT(HW_POWER_VDDMEMCTRL, TRG);
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s.vddmem_linreg = HW_POWER_VDDMEMCTRL & HW_POWER_VDDMEMCTRL__ENABLE_LINREG;
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}
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if(flags & POWER_INFO_DCDC)
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{
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s.dcdc_sel_pllclk = HW_POWER_MISC & HW_POWER_MISC__SEL_PLLCLK;
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s.dcdc_freqsel = dcdc_freqsel[__XTRACT(HW_POWER_MISC, FREQSEL)];
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}
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return s;
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}
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firmware/target/arm/imx233/power-imx233.h
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firmware/target/arm/imx233/power-imx233.h
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#define HW_POWER_VDDDCTRL__TRG_BM 0x1f
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#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
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#define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */
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#define HW_POWER_VDDDCTRL__ENABLE_LINREG (1 << 21)
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#define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50))
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#define HW_POWER_VDDACTRL__TRG_BP 0
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#define HW_POWER_VDDACTRL__TRG_BM 0x1f
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#define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */
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#define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */
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#define HW_POWER_VDDACTRL__ENABLE_LINREG (1 << 17)
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#define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60))
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#define HW_POWER_VDDIOCTRL__TRG_BP 0
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#define HW_POWER_VDDIOCTRL__TRG_BM 0x1f
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#define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */
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#define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */
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#define HW_POWER_VDDMEMCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x70))
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#define HW_POWER_VDDMEMCTRL__TRG_BP 0
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#define HW_POWER_VDDMEMCTRL__TRG_BM 0x1f
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#define HW_POWER_VDDMEMCTRL__TRG_STEP 50 /* mV */
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#define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */
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#define HW_POWER_VDDMEMCTRL__ENABLE_LINREG (1 << 8)
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#define HW_POWER_MISC (*(volatile uint32_t *)(HW_POWER_BASE + 0x90))
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#define HW_POWER_MISC__SEL_PLLCLK 1
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#define HW_POWER_MISC__FREQSEL_BP 4
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#define HW_POWER_MISC__FREQSEL_BM (0x7 << 4)
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#define HW_POWER_MISC__FREQSEL__RES 0
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#define HW_POWER_MISC__FREQSEL__20MHz 1
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#define HW_POWER_MISC__FREQSEL__24MHz 2
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#define HW_POWER_MISC__FREQSEL__19p2MHz 3
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#define HW_POWER_MISC__FREQSEL__14p4MHz 4
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#define HW_POWER_MISC__FREQSEL__18MHz 5
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#define HW_POWER_MISC__FREQSEL__21p6MHz 6
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#define HW_POWER_MISC__FREQSEL__17p28MHz 7
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#define HW_POWER_STS (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0))
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#define HW_POWER_STS__VBUSVALID (1 << 1)
···
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#define HW_POWER_RESET (*(volatile uint32_t *)(HW_POWER_BASE + 0x100))
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#define HW_POWER_RESET__UNLOCK 0x3E770000
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#define HW_POWER_RESET__PWD 0x1
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struct imx233_power_info_t
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{
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int vddd; /* in mV */
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bool vddd_linreg; /* VDDD source: linreg from VDDA or DC-DC */
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int vdda; /* in mV */
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bool vdda_linreg; /* VDDA source: linreg from VDDIO or DC-DC */
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int vddio; /* in mV */
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int vddmem; /* in mV */
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bool vddmem_linreg; /* VDDMEM source: linreg from VDDIO or off */
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bool dcdc_sel_pllclk; /* clock source of DC-DC: pll or 24MHz xtal */
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int dcdc_freqsel;
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};
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#define POWER_INFO_VDDD (1 << 0)
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#define POWER_INFO_VDDA (1 << 1)
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#define POWER_INFO_VDDIO (1 << 2)
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#define POWER_INFO_VDDMEM (1 << 3)
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#define POWER_INFO_DCDC (1 << 4)
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#define POWER_INFO_ALL 0x1f
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struct imx233_power_info_t imx233_power_get_info(unsigned flags);
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#endif /* __POWER_IMX233__ */