Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
S5L8702: Move I/O addresses from DMA driver to SoC definitions, reuse existing definitions
No difference in the produced binaries for ipod6g (normal and bootloader)
This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.
Change-Id: I82943e91ba7e6764428f853f84799f0d54b700a6
+50
-33
+9
-3
firmware/export/s5l87xx.h
+9
-3
firmware/export/s5l87xx.h
···
1002
1002
#define ECCCTRL_STARTDECNOSYND (1 << 2)
1003
1003
1004
1004
/* 17. IIS Tx/Rx INTERFACE */
1005
-
#define I2S_BASE 0x3CA00000
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+
#define I2S_BASE 0x3CA00000
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+
#define I2S_INTERFACE1_OFFSET 0x300000
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+
#define I2S_INTERFACE2_OFFSET 0xA00000
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1008
1007
1009
#define I2SCLKCON (*(REG32_PTR_T)(I2S_BASE)) /* Clock Control Register */
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1010
#define I2STXCON (*(REG32_PTR_T)(I2S_BASE + 0x04)) /* Tx configuration Register */
···
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#define UARTC_BASE_ADDR 0x3CC00000
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#define UARTC_N_PORTS 4
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#define UARTC_PORT_OFFSET 0x4000
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+
#if CONFIG_CPU == S5L8720
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+
#define UARTC_DMA_BASE_ADDR 0x3DB00000
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+
#define UARTC_DMA_PORT_OFFSET 0x100000
1287
+
#endif
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#endif
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/* 26. LCD INTERFACE CONTROLLER */
···
1727
1733
#define IRQ_EXT6 33
1728
1734
#endif
1729
1735
1730
-
#if CONFIG_CPU == S5L8702
1731
-
/* Something related to the ATA controller, needed for power up */
1736
+
/* Something related to the ATA controller, needed for HDD power up on ipod6g */
1732
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#define ATA_UNKNOWN_BASE 0x38a00000
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1738
1739
+
#if CONFIG_CPU == S5L8702
1734
1740
#define ATA_UNKNOWN (*((REG32_PTR_T)(ATA_UNKNOWN_BASE)))
1735
1741
#endif
1736
1742
+41
-30
firmware/target/arm/s5l8702/dma-s5l8702.h
+41
-30
firmware/target/arm/s5l8702/dma-s5l8702.h
···
84
84
#define S5L8702_DMAC1_PERI_MEM DMAC_PERI_NONE
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86
/* s5l8702 peripheral DMA R/W addesses */
87
-
#define S5L8702_DADDR_PERI_LCD_WR 0x38300040
87
+
#define S5L8702_DADDR_PERI_LCD_WR (LCD_BASE + 0x40)
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88
#if CONFIG_CPU == S5L8702
89
-
#define S5L8702_DADDR_PERI_SPDIF_TX 0x3CB00010 /* TBC */
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+
#define S5L8702_DADDR_PERI_SPDIF_TX (SPD_BASE + 0x10) /* TBC */
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#endif
91
-
#define S5L8702_DADDR_PERI_UART0_TX 0x3CC00020
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-
#define S5L8702_DADDR_PERI_UART0_RX 0x3CC00024
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+
#define S5L8702_DADDR_PERI_UART_TX(i) (UARTC_BASE_ADDR + UARTC_PORT_OFFSET * (i) + 0x20)
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+
#define S5L8702_DADDR_PERI_UART_RX(i) (UARTC_BASE_ADDR + UARTC_PORT_OFFSET * (i) + 0x24)
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+
#define S5L8702_DADDR_PERI_UART0_TX S5L8702_DADDR_PERI_UART_TX(0)
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+
#define S5L8702_DADDR_PERI_UART0_RX S5L8702_DADDR_PERI_UART_RX(0)
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#if CONFIG_CPU == S5L8702
94
-
#define S5L8702_DADDR_PERI_UART1_TX 0x3CC04020
95
-
#define S5L8702_DADDR_PERI_UART1_RX 0x3CC04024
96
-
#define S5L8702_DADDR_PERI_UART2_TX 0x3CC08020
97
-
#define S5L8702_DADDR_PERI_UART2_RX 0x3CC08024
98
-
#define S5L8702_DADDR_PERI_UART3_TX 0x3CC0C020
99
-
#define S5L8702_DADDR_PERI_UART3_RX 0x3CC0C024
96
+
#define S5L8702_DADDR_PERI_UART1_TX S5L8702_DADDR_PERI_UART_TX(1)
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+
#define S5L8702_DADDR_PERI_UART1_RX S5L8702_DADDR_PERI_UART_RX(1)
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+
#define S5L8702_DADDR_PERI_UART2_TX S5L8702_DADDR_PERI_UART_TX(2)
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+
#define S5L8702_DADDR_PERI_UART2_RX S5L8702_DADDR_PERI_UART_RX(2)
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+
#define S5L8702_DADDR_PERI_UART3_TX S5L8702_DADDR_PERI_UART_TX(3)
101
+
#define S5L8702_DADDR_PERI_UART3_RX S5L8702_DADDR_PERI_UART_RX(3)
100
102
#elif CONFIG_CPU == S5L8720
101
-
#define S5L8702_DADDR_PERI_UART1_TX 0x3DB00020
102
-
#define S5L8702_DADDR_PERI_UART1_RX 0x3DB00024
103
-
#define S5L8702_DADDR_PERI_UART2_TX 0x3DC00020
104
-
#define S5L8702_DADDR_PERI_UART2_RX 0x3DC00024
105
-
#define S5L8702_DADDR_PERI_UART3_TX 0x3DD00020
106
-
#define S5L8702_DADDR_PERI_UART3_RX 0x3DD00024
103
+
#define S5L8720_DADDR_PERI_UART_TX(i) (UARTC_DMA_BASE_ADDR + UARTC_DMA_PORT_OFFSET * (i - 1) + 0x20)
104
+
#define S5L8720_DADDR_PERI_UART_RX(i) (UARTC_DMA_BASE_ADDR + UARTC_DMA_PORT_OFFSET * (i - 1) + 0x24)
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+
#define S5L8702_DADDR_PERI_UART1_TX S5L8720_DADDR_PERI_UART_TX(1)
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+
#define S5L8702_DADDR_PERI_UART1_RX S5L8720_DADDR_PERI_UART_RX(1)
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+
#define S5L8702_DADDR_PERI_UART2_TX S5L8720_DADDR_PERI_UART_TX(2)
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+
#define S5L8702_DADDR_PERI_UART2_RX S5L8720_DADDR_PERI_UART_RX(2)
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+
#define S5L8702_DADDR_PERI_UART3_TX S5L8720_DADDR_PERI_UART_TX(3)
110
+
#define S5L8702_DADDR_PERI_UART3_RX S5L8720_DADDR_PERI_UART_RX(3)
107
111
#endif
108
-
#define S5L8702_DADDR_PERI_IIS0_TX 0x3CA00010
109
-
#define S5L8702_DADDR_PERI_IIS0_RX 0x3CA00038
110
-
#define S5L8702_DADDR_PERI_IIS1_TX 0x3CD00010
111
-
#define S5L8702_DADDR_PERI_IIS1_RX 0x3CD00038
112
-
#define S5L8702_DADDR_PERI_IIS2_TX 0x3D400010
113
-
#define S5L8702_DADDR_PERI_IIS2_RX 0x3D400038
114
-
#define S5L8702_DADDR_PERI_CEATA_WR 0x38A00080
112
+
#define S5L8702_DADDR_PERI_IIS_OFFSET(i) ((i) == 2 ? I2S_INTERFACE2_OFFSET : \
113
+
(i) == 1 ? I2S_INTERFACE1_OFFSET : \
114
+
0)
115
+
#define S5L8702_DADDR_PERI_IIS_TX(i) (I2S_BASE + S5L8702_DADDR_PERI_IIS_OFFSET(i) + 0x10)
116
+
#define S5L8702_DADDR_PERI_IIS_RX(i) (I2S_BASE + S5L8702_DADDR_PERI_IIS_OFFSET(i) + 0x38)
117
+
#define S5L8702_DADDR_PERI_IIS0_TX S5L8702_DADDR_PERI_IIS_TX(0)
118
+
#define S5L8702_DADDR_PERI_IIS0_RX S5L8702_DADDR_PERI_IIS_RX(0)
119
+
#define S5L8702_DADDR_PERI_IIS1_TX S5L8702_DADDR_PERI_IIS_TX(1)
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+
#define S5L8702_DADDR_PERI_IIS1_RX S5L8702_DADDR_PERI_IIS_RX(1)
121
+
#define S5L8702_DADDR_PERI_IIS2_TX S5L8702_DADDR_PERI_IIS_TX(2)
122
+
#define S5L8702_DADDR_PERI_IIS2_RX S5L8702_DADDR_PERI_IIS_RX(2)
123
+
#define S5L8702_DADDR_PERI_CEATA_WR (ATA_UNKNOWN_BASE + 0x80)
115
124
#if CONFIG_CPU == S5L8702
116
-
#define S5L8702_DADDR_PERI_CEATA_RD 0x38A04080
125
+
#define S5L8702_DADDR_PERI_CEATA_RD (ATA_UNKNOWN_BASE + 0x4000 + 0x80)
117
126
#endif
118
-
#define S5L8702_DADDR_PERI_SPI0_TX 0x3C300010
119
-
#define S5L8702_DADDR_PERI_SPI0_RX 0x3C300020
120
-
#define S5L8702_DADDR_PERI_SPI1_TX 0x3CE00010
121
-
#define S5L8702_DADDR_PERI_SPI1_RX 0x3CE00020
122
-
#define S5L8702_DADDR_PERI_SPI2_TX 0x3D200010
123
-
#define S5L8702_DADDR_PERI_SPI2_RX 0x3D200020
127
+
#define S5L8702_DADDR_PERI_SPI_TX(i) (SPIBASE(i) + 0x10)
128
+
#define S5L8702_DADDR_PERI_SPI_RX(i) (SPIBASE(i) + 0x20)
129
+
#define S5L8702_DADDR_PERI_SPI0_TX S5L8702_DADDR_PERI_SPI_TX(0)
130
+
#define S5L8702_DADDR_PERI_SPI0_RX S5L8702_DADDR_PERI_SPI_RX(0)
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+
#define S5L8702_DADDR_PERI_SPI1_TX S5L8702_DADDR_PERI_SPI_TX(1)
132
+
#define S5L8702_DADDR_PERI_SPI1_RX S5L8702_DADDR_PERI_SPI_RX(1)
133
+
#define S5L8702_DADDR_PERI_SPI2_TX S5L8702_DADDR_PERI_SPI_TX(2)
134
+
#define S5L8702_DADDR_PERI_SPI2_RX S5L8702_DADDR_PERI_SPI_RX(2)
124
135
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/* proto */
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void dma_init(void);