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echoplayer: modify LCD timings to disable PLL3 fractional mode
According to the datasheet, the PLL fractional mode is
apparently not supported in the medium VCO range.
The LCD isn't picky about front/back porch settings so
modify these to get a dot clock close to 6 MHz (within
~0.1% error).
Change-Id: I51647534db8c2b261391864db9262a0b04548e6d
authored by
Aidan MacDonald
and committed by
Solomon Peachy
b155e2c3
fe0c404d
+11
-13
+8
-10
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
+8
-10
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
···
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#include "regs/stm32h743/syscfg.h"
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#define PLL1Q_FREQ 48000000
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+
#define PLL3R_FREQ 6000000
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/* Flag to use VOS0 */
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#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
···
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/* For simplicity, PLL parameters are hardcoded */
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_Static_assert(STM32_HSE_FREQ == 24000000,
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"HSE frequency not correct");
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-
_Static_assert(LCD_DOTCLOCK_FREQ == 6199200,
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"PLL3 parameters not correct for dot clock");
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_Static_assert(LCD_DOTCLOCK_FREQ <= PLL3R_FREQ,
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"PLL3R too slow for LCD");
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_Static_assert(PLL1Q_FREQ == 48000000,
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"PLL1Q parameters not correct");
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/*
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* Use HSE/4 input for PLL1
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-
* Use HSE/16 input for PLL3
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* Use HSE/12 input for PLL3
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* PLL2 reserved for audio; configured in target PCM code
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*/
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reg_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
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DIVM1(4),
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DIVM2(0),
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DIVM3(16));
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DIVM3(12));
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/* Enable PLL1P, PLL1Q, PLL3R */
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reg_writef(RCC_PLLCFGR,
···
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DIVQ(10 - 1), /* 480 / 10 = 48 MHz */
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DIVR(1 - 1));
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reg_writef(RCC_PLL3FRACR, FRACN(1468));
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reg_writef(RCC_PLL3DIVR,
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DIVN(161 - 1), /* approx 241.768 MHz */
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DIVN(90 - 1), /* 2 * 90 = 180 MHz */
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DIVP(1 - 1),
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DIVQ(1 - 1),
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DIVR(39 - 1)); /* approx 6.1992 MHz */
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-
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reg_writef(RCC_PLLCFGR, PLL3FRACEN(1));
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DIVR(30 - 1)); /* 180 / 30 = 6 MHz */
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reg_writef(RCC_CR, PLL1ON(1), PLL3ON(1));
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while (!reg_readf(RCC_CR, PLL1RDY));
···
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};
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const struct stm32_clock ltdc_ker_clock = {
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.frequency = LCD_DOTCLOCK_FREQ,
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.frequency = PLL3R_FREQ,
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.en_reg = ITA_RCC_APB3ENR,
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.en_bit = BM_RCC_APB3ENR_LTDCEN,
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.lpen_reg = ITA_RCC_APB3LPENR,
+3
-3
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.h
+3
-3
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.h
···
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#include "config.h"
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/* Hsync pulse width in units of dot clocks */
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#define LCD_HSW 10
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#define LCD_HSW 14
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/* Hsync back porch in units of dot clocks */
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#define LCD_HBP 20
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#define LCD_HBP 7
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/* Horizontal active width in units of dot clocks */
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#define LCD_HAW LCD_WIDTH
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/* Hsync front porch in units of dot clocks */
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#define LCD_HFP 10
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#define LCD_HFP 7
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/* Vsync pulse height in units of horizontal lines */
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#define LCD_VSH 2