Rockbox open source high quality audio player as a Music Player Daemon
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Sansa AMS: Assume IDE_CLK is used as MCLK for internal SD. We assumed PCLK previously.

This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz.

Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657

+24 -12
+19 -6
firmware/target/arm/as3525/ata_sd_as3525.c
··· 121 121 bool sd_enabled = false; 122 122 #endif 123 123 124 + #if defined(HAVE_MULTIDRIVE) 125 + static bool hs_card = false; 126 + #endif 127 + 124 128 static struct wakeup transfer_completion_signal; 125 129 static volatile unsigned int transfer_error[NUM_VOLUMES]; 126 130 #define PL180_MAX_TRANSFER_ERRORS 10 ··· 347 351 348 352 sd_parse_csd(&card_info[drive]); 349 353 354 + #if defined(HAVE_MULTIDRIVE) 355 + hs_card = (card_info[drive].speed == 50000000) ? true : false; 356 + #endif 357 + 350 358 /* Boost MCICLK to operating speed */ 351 359 if(drive == INTERNAL_AS3525) 352 - MCI_CLOCK(drive) = MCI_QUARTERSPEED; /* MCICLK = PCLK/4 = 15.5MHz */ 360 + MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */ 361 + #if defined(HAVE_MULTIDRIVE) 353 362 else 354 363 /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/ 355 - MCI_CLOCK(drive) = ((card_info[drive].speed == 50000000) ? 356 - MCI_HALFSPEED : MCI_QUARTERSPEED); 364 + MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED); 365 + #endif 357 366 358 367 /* CMD7 w/rca: Select card to put it in TRAN state */ 359 368 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL)) ··· 733 742 dma_enable_channel(0, dma_buf, MCI_FIFO(drive), 734 743 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT, 735 744 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL); 736 - 745 + #if defined(HAVE_MULTIDRIVE) 737 746 /*Small delay for writes prevents data crc failures at lower freqs*/ 738 - int write_delay = 125; 739 - while(write_delay--); 747 + if((drive == SD_SLOT_AS3525) && !hs_card) 748 + { 749 + int write_delay = 125; 750 + while(write_delay--); 751 + } 752 + #endif 740 753 } 741 754 else 742 755 dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
+2 -3
firmware/target/arm/as3525/clock-target.h
··· 118 118 119 119 #define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */ 120 120 #define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/ 121 - #define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq 122 - but sd transfers fail on some 123 - players with this limit */ 121 + #define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */ 122 + 124 123 125 124 //#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */ 126 125 //#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/
+3 -3
firmware/target/arm/as3525/debug-as3525.c
··· 185 185 if(!(MCI_NAND & (1<<8))) 186 186 return 0; 187 187 else if(MCI_NAND & (1<<10)) 188 - return calc_freq(CLK_PCLK); 188 + return calc_freq(CLK_IDE); 189 189 else 190 - return calc_freq(CLK_PCLK)/(((MCI_NAND & 0xff)+1)*2); 190 + return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2); 191 191 case CLK_SD_MCLK_MSD: 192 192 if(!(MCI_SD & (1<<8))) 193 193 return 0; ··· 304 304 } 305 305 306 306 lcd_putsf(0, line++, "SD :%3dMHz %3dMHz", 307 - ((AS3525_PCLK_FREQ/ 1000000) / 307 + ((AS3525_IDE_FREQ/ 1000000) / 308 308 ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))), 309 309 calc_freq(CLK_SD_MCLK_NAND)/1000000); 310 310 #ifdef HAVE_MULTIDRIVE