tsiry-sandratraina.com / rockbox-zig
Rockbox open source high quality audio player as a Music Player Daemon
mpris rockbox mpd libadwaita audio rust zig deno
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FS#11597 : decrease FCLK frequency when unboosted

FCLK is unused because we use fastbus clocking: CPU clock = PCLK
Base PCLK off PLLA and use the lowest frqeuency for FCLK (24MHz source,
maximum divider)
Save a bit of power, adjust Clipv1/e200v2/Fuzev1 current usage accordingly

Note: the power saving (in mA) is a bit less on e200v2/Fuzev1 than on Clipv1

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28000 a1c6a512-1295-4272-9138-f99709370657

Rafaël Carré c196da2c d71d537b

+19 -27
+1 -1
firmware/export/config/sansaclip.h
··· 154 154 /* #define HAVE_POWEROFF_WHILE_CHARGING */ 155 155 156 156 /* define current usage levels (based on battery bench) */ 157 - #define CURRENT_NORMAL 42 157 + #define CURRENT_NORMAL 37 158 158 #define CURRENT_BACKLIGHT 13 159 159 #define CURRENT_RECORD CURRENT_NORMAL 160 160
+1 -1
firmware/export/config/sansae200v2.h
··· 158 158 #define CONFIG_I2C I2C_AS3525 159 159 160 160 /* define current usage levels (based on battery bench) */ 161 - #define CURRENT_NORMAL 45 161 + #define CURRENT_NORMAL 44 162 162 #define CURRENT_BACKLIGHT 30 163 163 #define CURRENT_RECORD CURRENT_NORMAL 164 164
+1 -1
firmware/export/config/sansafuze.h
··· 162 162 #define CONFIG_I2C I2C_AS3525 163 163 164 164 /* define current usage levels (based on battery bench) */ 165 - #define CURRENT_NORMAL 37 165 + #define CURRENT_NORMAL 35 166 166 #define CURRENT_BACKLIGHT 30 167 167 #define CURRENT_RECORD CURRENT_NORMAL 168 168
+9 -13
firmware/target/arm/as3525/clock-target.h
··· 139 139 #define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/ 140 140 141 141 #if CONFIG_CPU == AS3525v2 142 - /* On as3525v2 we change fclk by writing to CGU_PROC */ 143 142 #define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */ 144 143 /* Since pclk is based on fclk, we need to change CGU_PERI as well */ 145 144 #define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ ··· 164 163 165 164 /* PCLK */ 166 165 167 - /* Figure out if we need to use asynchronous bus */ 168 - #if ((CONFIG_CPU == AS3525) && (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ)) 169 - #define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */ 170 - #endif 166 + #if CONFIG_CPU == AS3525 167 + 168 + #define AS3525_PCLK_SEL AS3525_CLK_PLLA 169 + /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ 170 + #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ 171 + #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ 172 + #else 171 173 172 - #ifdef ASYNCHRONOUS_BUS 173 - #define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */ 174 - #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/ 175 - #else /* ASYNCHRONOUS_BUS */ 176 - #define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */ 174 + #define AS3525_PCLK_SEL AS3525_CLK_FCLK 177 175 #define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/ 178 - #endif /* ASYNCHRONOUS_BUS */ 179 176 180 - /*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/ 181 - #define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/ 177 + #endif /* CONFIG_CPU */ 182 178 183 179 /* PCLK as Source */ 184 180 #define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
+7 -11
firmware/target/arm/as3525/system-as3525.c
··· 262 262 #endif 263 263 AS3525_PCLK_SEL); 264 264 265 - #if CONFIG_CPU == AS3525 266 - cpu_frequency = CPUFREQ_DEFAULT; /* fastbus */ 267 - #else 268 - cpu_frequency = CPUFREQ_MAX; 269 - #endif 265 + set_cpu_frequency(CPUFREQ_DEFAULT); 270 266 271 267 #if 0 /* the GPIO clock is already enabled by the dualboot function */ 272 268 CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; ··· 367 363 while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */ 368 364 #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */ 369 365 366 + CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) | 367 + (AS3525_FCLK_PREDIV << 2) | 368 + AS3525_FCLK_SEL); 369 + 370 370 asm volatile( 371 371 "mrc p15, 0, r0, c1, c0 \n" 372 - 373 - #ifdef ASYNCHRONOUS_BUS 374 - "orr r0, r0, #3<<30 \n" /* asynchronous bus clocking */ 375 - #else 376 372 "bic r0, r0, #3<<30 \n" /* clear bus bits */ 377 373 "orr r0, r0, #1<<30 \n" /* synchronous bus clocking */ 378 - #endif 379 - 380 374 "mcr p15, 0, r0, c1, c0 \n" 381 375 : : : "r0" ); 382 376 ··· 390 384 "mcr p15, 0, r0, c1, c0 \n" 391 385 : : : "r0" ); 392 386 387 + /* FCLK is unused so put it to the lowest freq we can */ 388 + CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN); 393 389 394 390 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE 395 391 /* Decreasing frequency so reduce voltage after change */