Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
Untested attempt at a Clip+ LCD driver using SSP (PrimeCell PL022)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24523 a1c6a512-1295-4272-9138-f99709370657
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-7
+14
firmware/export/as3525.h
+14
firmware/export/as3525.h
···
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#define I2SOUT_CLEAR (*(volatile unsigned char*)(I2SOUT_BASE+0x10))
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#define I2SOUT_DATA (volatile unsigned long*)(I2SOUT_BASE+0x14)
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+
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/* SSP registers (PrimeCell PL022) */
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#define SSP_CR0 (*(volatile unsigned short*)(SSP_BASE+0x00))
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#define SSP_CR1 (*(volatile unsigned char*)(SSP_BASE+0x04))
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#define SSP_DATA (*(volatile unsigned short*)(SSP_BASE+0x08))
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#define SSP_SR (*(volatile unsigned char*)(SSP_BASE+0x0C))
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#define SSP_CPSR (*(volatile unsigned char*)(SSP_BASE+0x10))
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#define SSP_IMSC (*(volatile unsigned char*)(SSP_BASE+0x14))
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#define SSP_IRS (*(volatile unsigned char*)(SSP_BASE+0x18))
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#define SSP_MIS (*(volatile unsigned char*)(SSP_BASE+0x1C))
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#define SSP_ICR (*(volatile unsigned char*)(SSP_BASE+0x20))
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#define SSP_DMACR (*(volatile unsigned char*)(SSP_BASE+0x24))
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/* PCM addresses for obtaining buffers will be what DMA is using (physical) */
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#define HAVE_PCM_DMA_ADDRESS
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+55
-7
firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
+55
-7
firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
···
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#define LCD_CNTL_HIGHCOL 0x10 /* Upper column address */
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#define LCD_CNTL_LOWCOL 0x00 /* Lower column address */
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+
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static void lcd_hw_init(void)
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{
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#if defined(SANSA_CLIP)
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/* DBOP initialisation, do what OF does */
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-
static void ams3525_dbop_init(void)
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-
{
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-
#ifdef SANSA_CLIP
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CGU_DBOP = (1<<3) | AS3525_DBOP_DIV;
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GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */
···
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DBOP_CTRL = 0x51008;
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DBOP_TIMPOL_01 = 0x6E167;
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DBOP_TIMPOL_23 = 0xA167E06F;
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-
#else /* SANSA_CLIPV2 */
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+
#elif defined(SANSA_CLIPV2)
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/* DBOP initialisation, do what OF does */
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CCU_IO |= (1<<12); /* ?? */
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CGU_DBOP |= /*(1<<3)*/ 0x18 | AS3525_DBOP_DIV;
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DBOP_CTRL = 0x51004;
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DBOP_TIMPOL_01 = 0x36A12F;
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DBOP_TIMPOL_23 = 0xE037E037;
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#elif defined(SANSA_CLIPPLUS)
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CGU_PERI |= CGU_SSP_CLOCK_ENABLE;
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SSP_CPSR; /* No clock prescale */
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SSP_CR0 = 0 | 7; /* Motorola SPI frame format, 8 bits */
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SSP_CR1 = 1<<1; /* SSP Operation enabled */
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SSP_IMSC = 0; /* No interrupts */
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#endif
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}
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···
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#define LCD_DELAY 10
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#endif
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+
#if defined(SANSA_CLIP) || defined(SANSA_CLIPV2)
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void lcd_write_command(int byte)
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{
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volatile int i = 0;
···
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DBOP_TIMPOL_23 = 0xE037E037;
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#endif
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}
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#elif defined(SANSA_CLIPPLUS)
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void lcd_write_command(int byte)
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{
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while(SSP_SR & (1<<4)) /* BSY flag */
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;
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GPIOB_PIN(2) = 0;
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SSP_DATA = byte;
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while(SSP_SR & (1<<4)) /* BSY flag */
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;
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}
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#endif
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#if defined(SANSA_CLIP) || defined(SANSA_CLIPV2)
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void lcd_write_data(const fb_data* p_bytes, int count)
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{
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volatile int i = 0;
···
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/* While push fifo is not empty */
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while ((DBOP_STAT & (1<<10)) == 0);
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}
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#elif defined(SANSA_CLIPPLUS)
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void lcd_write_data(const fb_data* p_bytes, int count)
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+
{
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GPIOB_PIN(2) = (1<<2);
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+
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SSP_CR0 = 0 | 15; /* Motorola SPI frame format, 16 bits */
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while (count--)
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{
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while(SSP_SR & (1<<1)) /* Transmit FIFO is not full */
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SSP_DATA = *p_bytes++;
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while(!(SSP_SR & (1<<0))) /* Transmit FIFO is not empty */
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;
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}
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SSP_CR0 = 0 | 7; /* Motorola SPI frame format, 8 bits */
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}
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#endif
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/** globals **/
···
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#define LCD_FULLSCREEN (128+4)
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fb_data p_bytes[LCD_FULLSCREEN]; /* framebuffer used to clear the screen */
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-
ams3525_dbop_init();
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lcd_hw_init();
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-
#ifdef SANSA_CLIP
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#if defined(SANSA_CLIP)
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GPIOA_DIR |= 0x33; /* pins 5:4 and 1:0 out */
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GPIOB_DIR |= 0x40; /* pin 6 out */
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···
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GPIOA_PIN(0) = (1<<0);
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GPIOA_PIN(4) = 0;
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GPIOB_PIN(6) = (1<<6);
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-
#else /* SANSA_CLIPV2 */
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#elif defined(SANSA_CLIPV2)
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GPIOB_DIR |= (1<<2)|(1<<5);
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GPIOB_PIN(5) = (1<<5);
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#elif defined(SANSA_CLIPPLUS)
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GPIOA_DIR |= (1<<5);
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GPIOB_DIR |= (1<<2) | (1<<7);
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GPIOA_PIN(5) = 0;
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GPIOA_DIR &= (1<<0);
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GPIOA_PIN(0) = (1<<0);
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+
GPIOB_PIN(7) = (1<<7);
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#endif
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/* Set display clock (divide ratio = 1) and oscillator frequency (1) */