Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
S5L8702: Move I/O addresses from drivers to SoC definitions
No changes to ipod6g binaries (normal + bootloader).
Change-Id: Iaad0d0de16176ff94b1f67aa3fdb7c6cc063b27e
authored by
Vencislav Atanasov
and committed by
Solomon Peachy
eb57d428
f233b6e2
+142
-133
+133
firmware/export/s5l87xx.h
+133
firmware/export/s5l87xx.h
···
58
58
#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
59
59
#endif
60
60
61
+
/* Base address of the memory-mapped I/O */
62
+
#define IO_BASE 0x38000000
63
+
61
64
/* 04. CALMADM2E */
62
65
63
66
/* Following registers are mapped on IO Area in data memory area of Calm. */
···
1219
1222
#define PDAT6 PDAT(6) /* The data register for port 6 */
1220
1223
#define PCON7 PCON(7) /* Configures the pins of port 7 */
1221
1224
#define PDAT7 PDAT(7) /* The data register for port 7 */
1225
+
#define PUNK8 PUNB(8) /* Unknown thing for port 8 */
1222
1226
#define PCON10 PCON(10) /* Configures the pins of port 10 */
1223
1227
#define PDAT10 PDAT(10) /* The data register for port 10 */
1224
1228
#define PCON11 PCON(11) /* Configures the pins of port 11 */
···
1241
1245
#elif CONFIG_CPU==S5L8702
1242
1246
#define GPIO_N_GROUPS 16
1243
1247
#define GPIOCMD (*((REG32_PTR_T)(GPIO_BASE + 0x200)))
1248
+
#define GPIOUNK380 (*((REG32_PTR_T)(GPIO_BASE + 0x380)))
1244
1249
#elif CONFIG_CPU==S5L8720
1245
1250
#define GPIO_N_GROUPS 15
1246
1251
#define GPIOCMD (*((REG32_PTR_T)(GPIO_BASE + 0x1e0)))
···
1721
1726
#define IRQ_EXT5 32
1722
1727
#define IRQ_EXT6 33
1723
1728
#endif
1729
+
1730
+
#if CONFIG_CPU == S5L8702
1731
+
/* Something related to the ATA controller, needed for power up */
1732
+
#define ATA_UNKNOWN_BASE 0x38a00000
1733
+
1734
+
#define ATA_UNKNOWN (*((REG32_PTR_T)(ATA_UNKNOWN_BASE)))
1735
+
#endif
1736
+
1737
+
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
1738
+
/*
1739
+
* s5l8702 External (GPIO) Interrupt Controller
1740
+
*
1741
+
* 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
1742
+
* to groups 6..3 in reverse order.
1743
+
* On group 3, last four bits are dissbled (GPIO 124..127).
1744
+
* All bits in groups 1 and 2 are disabled (not used).
1745
+
* On group 0, all bits are masked except bits 0 and 2:
1746
+
* bit 0: if unmasked, EINT6 is generated when ALVTCNT
1747
+
* reachs ALVTEND.
1748
+
* bit 2: if unmasked, EINT6 is generated when USB cable
1749
+
* is plugged and/or(TBC) unplugged.
1750
+
*
1751
+
* EIC_GROUP0..6 are connected to EINT6..0 of the VIC.
1752
+
*/
1753
+
#define EIC_N_GROUPS 7
1754
+
1755
+
/* get EIC group and bit for a given GPIO port */
1756
+
#define EIC_GROUP(n) (6 - ((n) >> 5))
1757
+
#define EIC_INDEX(n) ((0x18 - ((n) & 0x18)) | ((n) & 0x7))
1758
+
1759
+
/* SoC EINTs uses these 'gpio' numbers */
1760
+
#define GPIO_EINT_USB 0xd8
1761
+
#define GPIO_EINT_ALIVE 0xda
1762
+
1763
+
/* probably a part of the system controller */
1764
+
#if CONFIG_CPU == S5L8702
1765
+
#define EIC_BASE 0x39a00000
1766
+
#elif CONFIG_CPU == S5L8720
1767
+
#define EIC_BASE 0x39700000
1768
+
#endif
1769
+
1770
+
#define EIC_INTLEVEL(g) (*((REG32_PTR_T)(EIC_BASE + 0x80 + 4*(g))))
1771
+
#define EIC_INTSTAT(g) (*((REG32_PTR_T)(EIC_BASE + 0xA0 + 4*(g))))
1772
+
#define EIC_INTEN(g) (*((REG32_PTR_T)(EIC_BASE + 0xC0 + 4*(g))))
1773
+
#define EIC_INTTYPE(g) (*((REG32_PTR_T)(EIC_BASE + 0xE0 + 4*(g))))
1774
+
1775
+
#define EIC_INTLEVEL_LOW 0
1776
+
#define EIC_INTLEVEL_HIGH 1
1777
+
1778
+
#define EIC_INTTYPE_EDGE 0
1779
+
#define EIC_INTTYPE_LEVEL 1
1780
+
#endif
1781
+
1782
+
#if CONFIG_CPU == S5L8702
1783
+
/*
1784
+
* This is very preliminary work in progress, ATM this region is called
1785
+
* system 'alive' because it seems there are similiarities when mixing
1786
+
* concepts from:
1787
+
* - s3c2440 datasheet (figure 7-12, Sleep mode) and
1788
+
* - ARM-DDI-0287B (2.1.8 System Mode Control, Sleep an Doze modes)
1789
+
*
1790
+
* Known components:
1791
+
* - independent clocking
1792
+
* - 32-bit timer
1793
+
* - level/edge configurable interrupt controller
1794
+
*
1795
+
*
1796
+
* OSCSEL
1797
+
* |\ CKSEL
1798
+
* OSC0 -->| | |\
1799
+
* | |--->| | _________ ___________
1800
+
* OSC1 -->| | | | | | SClk | |
1801
+
* |/ | |--->| 1/CKDIV |---------->| 1/ALVTDIV |--> Timer
1802
+
* | | |_________| | |___________| counter
1803
+
* PClk --------->| | | ___________
1804
+
* |/ | | |
1805
+
* +-->| 1/UNKDIV |--> Unknown
1806
+
* |___________|
1807
+
*/
1808
+
#define SYSALV_BASE 0x39a00000
1809
+
1810
+
#define ALVCON (*((REG32_PTR_T)(SYSALV_BASE)))
1811
+
#define ALVUNK4 (*((REG32_PTR_T)(SYSALV_BASE + 0x4)))
1812
+
#define ALVUNK100 (*((REG32_PTR_T)(SYSALV_BASE + 0x100)))
1813
+
#define ALVUNK104 (*((REG32_PTR_T)(SYSALV_BASE + 0x104)))
1814
+
1815
+
1816
+
/*
1817
+
* System Alive control register
1818
+
*/
1819
+
#define ALVCON_CKSEL_BIT (1 << 25) /* 0 -> S5L8702_OSCx, 1 -> PClk */
1820
+
#define ALVCON_CKDIVEN_BIT (1 << 24) /* 0 -> CK divider Off, 1 -> On */
1821
+
#define ALVCON_CKDIV_POS 20 /* real_val = reg_val+1 */
1822
+
#define ALVCON_CKDIV_MSK 0xf
1823
+
1824
+
/* UNKDIV: real_val = reg_val+1 (TBC), valid reg_val=0,1,2 */
1825
+
/* experimental: for registers in this region, read/write speed is
1826
+
* scaled by this divider, so probably it is related with internal
1827
+
* 'working' frequency.
1828
+
*/
1829
+
#define ALVCON_UNKDIV_POS 16
1830
+
#define ALVCON_UNKDIV_MSK 0x3
1831
+
1832
+
/* bits[14:1] are UNKNOWN */
1833
+
1834
+
#define ALVCON_OSCSEL_BIT (1 << 0) /* 0 -> OSC0, 1 -> OSC1 */
1835
+
1836
+
1837
+
/*
1838
+
* System Alive timer
1839
+
*
1840
+
* ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
1841
+
* is SClk / ALVTDIV. When count reachs ALVTEND then ALVTSTAT[0]
1842
+
* and ALVUNK4[0] are set, optionally an interrupt is generated (see
1843
+
* GPIO_EINT_ALIVE). Writing 1 to ALVTCOM_RST_BIT clears ALVSTAT[0]
1844
+
* and ALVUNK4[0], and initializes ALVTCNT to zero.
1845
+
*/
1846
+
#define ALVTCOM (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
1847
+
#define ALVTCOM_RUN_BIT (1 << 0) /* 0 -> Stop, 1 -> Start */
1848
+
#define ALVTCOM_RST_BIT (1 << 1) /* 1 -> Reset */
1849
+
1850
+
#define ALVTEND (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
1851
+
#define ALVTDIV (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
1852
+
1853
+
#define ALVTCNT (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
1854
+
#define ALVTSTAT (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
1855
+
1856
+
#endif /* CONFIG_CPU == S5L8702 */
1724
1857
1725
1858
#endif /* __S5L87XX_H__ */
-124
firmware/target/arm/s5l8702/gpio-s5l8702.h
-124
firmware/target/arm/s5l8702/gpio-s5l8702.h
···
23
23
#define __GPIO_S5L8702_H__
24
24
#include <stdint.h>
25
25
26
-
27
-
#define REG32_PTR_T volatile uint32_t *
28
-
29
-
/*
30
-
* s5l8702 External (GPIO) Interrupt Controller
31
-
*
32
-
* 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
33
-
* to groups 6..3 in reverse order.
34
-
* On group 3, last four bits are dissbled (GPIO 124..127).
35
-
* All bits in groups 1 and 2 are disabled (not used).
36
-
* On group 0, all bits are masked except bits 0 and 2:
37
-
* bit 0: if unmasked, EINT6 is generated when ALVTCNT
38
-
* reachs ALVTEND.
39
-
* bit 2: if unmasked, EINT6 is generated when USB cable
40
-
* is plugged and/or(TBC) unplugged.
41
-
*
42
-
* EIC_GROUP0..6 are connected to EINT6..0 of the VIC.
43
-
*/
44
-
#define EIC_N_GROUPS 7
45
-
46
-
/* get EIC group and bit for a given GPIO port */
47
-
#define EIC_GROUP(n) (6 - ((n) >> 5))
48
-
#define EIC_INDEX(n) ((0x18 - ((n) & 0x18)) | ((n) & 0x7))
49
-
50
-
/* SoC EINTs uses these 'gpio' numbers */
51
-
#define GPIO_EINT_USB 0xd8
52
-
#define GPIO_EINT_ALIVE 0xda
53
-
54
-
/* probably a part of the system controller */
55
-
#if CONFIG_CPU == S5L8702
56
-
#define EIC_BASE 0x39a00000
57
-
#elif CONFIG_CPU == S5L8720
58
-
#define EIC_BASE 0x39700000
59
-
#endif
60
-
61
-
#define EIC_INTLEVEL(g) (*((REG32_PTR_T)(EIC_BASE + 0x80 + 4*(g))))
62
-
#define EIC_INTSTAT(g) (*((REG32_PTR_T)(EIC_BASE + 0xA0 + 4*(g))))
63
-
#define EIC_INTEN(g) (*((REG32_PTR_T)(EIC_BASE + 0xC0 + 4*(g))))
64
-
#define EIC_INTTYPE(g) (*((REG32_PTR_T)(EIC_BASE + 0xE0 + 4*(g))))
65
-
66
-
#define EIC_INTLEVEL_LOW 0
67
-
#define EIC_INTLEVEL_HIGH 1
68
-
69
-
#define EIC_INTTYPE_EDGE 0
70
-
#define EIC_INTTYPE_LEVEL 1
71
-
72
-
73
26
struct eic_handler {
74
27
uint8_t gpio_n;
75
28
uint8_t type; /* EIC_INTTYPE_ */
···
87
40
/* get/set configuration for GPIO groups (0..15) */
88
41
uint32_t gpio_group_get(int group);
89
42
void gpio_group_set(int group, uint32_t mask, uint32_t cfg);
90
-
91
-
92
-
#if CONFIG_CPU == S5L8702
93
-
/*
94
-
* This is very preliminary work in progress, ATM this region is called
95
-
* system 'alive' because it seems there are similiarities when mixing
96
-
* concepts from:
97
-
* - s3c2440 datasheet (figure 7-12, Sleep mode) and
98
-
* - ARM-DDI-0287B (2.1.8 System Mode Control, Sleep an Doze modes)
99
-
*
100
-
* Known components:
101
-
* - independent clocking
102
-
* - 32-bit timer
103
-
* - level/edge configurable interrupt controller
104
-
*
105
-
*
106
-
* OSCSEL
107
-
* |\ CKSEL
108
-
* OSC0 -->| | |\
109
-
* | |--->| | _________ ___________
110
-
* OSC1 -->| | | | | | SClk | |
111
-
* |/ | |--->| 1/CKDIV |---------->| 1/ALVTDIV |--> Timer
112
-
* | | |_________| | |___________| counter
113
-
* PClk --------->| | | ___________
114
-
* |/ | | |
115
-
* +-->| 1/UNKDIV |--> Unknown
116
-
* |___________|
117
-
*/
118
-
#define SYSALV_BASE 0x39a00000
119
-
120
-
#define ALVCON (*((REG32_PTR_T)(SYSALV_BASE + 0x0)))
121
-
#define ALVUNK4 (*((REG32_PTR_T)(SYSALV_BASE + 0x4)))
122
-
#define ALVUNK100 (*((REG32_PTR_T)(SYSALV_BASE + 0x100)))
123
-
#define ALVUNK104 (*((REG32_PTR_T)(SYSALV_BASE + 0x104)))
124
-
125
-
126
-
/*
127
-
* System Alive control register
128
-
*/
129
-
#define ALVCON_CKSEL_BIT (1 << 25) /* 0 -> S5L8702_OSCx, 1 -> PClk */
130
-
#define ALVCON_CKDIVEN_BIT (1 << 24) /* 0 -> CK divider Off, 1 -> On */
131
-
#define ALVCON_CKDIV_POS 20 /* real_val = reg_val+1 */
132
-
#define ALVCON_CKDIV_MSK 0xf
133
-
134
-
/* UNKDIV: real_val = reg_val+1 (TBC), valid reg_val=0,1,2 */
135
-
/* experimental: for registers in this region, read/write speed is
136
-
* scaled by this divider, so probably it is related with internal
137
-
* 'working' frequency.
138
-
*/
139
-
#define ALVCON_UNKDIV_POS 16
140
-
#define ALVCON_UNKDIV_MSK 0x3
141
-
142
-
/* bits[14:1] are UNKNOWN */
143
-
144
-
#define ALVCON_OSCSEL_BIT (1 << 0) /* 0 -> OSC0, 1 -> OSC1 */
145
-
146
-
147
-
/*
148
-
* System Alive timer
149
-
*
150
-
* ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
151
-
* is SClk / ALVTDIV. When count reachs ALVTEND then ALVTSTAT[0]
152
-
* and ALVUNK4[0] are set, optionally an interrupt is generated (see
153
-
* GPIO_EINT_ALIVE). Writing 1 to ALVTCOM_RST_BIT clears ALVSTAT[0]
154
-
* and ALVUNK4[0], and initializes ALVTCNT to zero.
155
-
*/
156
-
#define ALVTCOM (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
157
-
#define ALVTCOM_RUN_BIT (1 << 0) /* 0 -> Stop, 1 -> Start */
158
-
#define ALVTCOM_RST_BIT (1 << 1) /* 1 -> Reset */
159
-
160
-
#define ALVTEND (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
161
-
#define ALVTDIV (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
162
-
163
-
#define ALVTCNT (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
164
-
#define ALVTSTAT (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
165
-
166
-
#endif /* CONFIG_CPU == S5L8702 */
167
43
168
44
#endif /* __GPIO_S5L8702_H__ */
+8
-8
firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c
+8
-8
firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c
···
483
483
484
484
static int ceata_cancel_command(void)
485
485
{
486
-
*((uint32_t volatile*)0x3cf00200) = 0x9000e;
486
+
GPIOCMD = 0x9000e;
487
487
udelay(1);
488
-
*((uint32_t volatile*)0x3cf00200) = 0x9000f;
488
+
GPIOCMD = 0x9000f;
489
489
udelay(1);
490
-
*((uint32_t volatile*)0x3cf00200) = 0x90003;
490
+
GPIOCMD = 0x90003;
491
491
udelay(1);
492
492
PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
493
493
| SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
···
669
669
PCON(8) = 0x33333333;
670
670
PCON(9) = 0x00000033;
671
671
PCON(11) |= 0xf;
672
-
*((uint32_t volatile*)0x38a00000) = 0;
673
-
*((uint32_t volatile*)0x38700000) = 0;
672
+
ATA_UNKNOWN = 0;
673
+
ATA_CONTROL = 0;
674
674
PWRCON(0) &= ~(1 << 9);
675
675
SDCI_RESET = 0xa5;
676
676
sleep(HZ / 100);
677
-
*((uint32_t volatile*)0x3cf00380) = 0;
678
-
*((uint32_t volatile*)0x3cf0010c) = 0xff;
677
+
GPIOUNK380 = 0;
678
+
PUNK8 = 0xff;
679
679
SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
680
680
| SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
681
681
SDCI_CLKDIV = SDCI_CDIV_CLKDIV(260);
682
-
*((uint32_t volatile*)0x3cf00200) = 0xb000f;
682
+
GPIOCMD = 0xb000f;
683
683
SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
684
684
PASS_RC(mmc_init(), 3, 0);
685
685
SDCI_CLKDIV = SDCI_CDIV_CLKDIV(4);
+1
-1
firmware/target/arm/s5l8702/system-s5l8702.c
+1
-1
firmware/target/arm/s5l8702/system-s5l8702.c
···
301
301
#endif
302
302
303
303
/* disable caching for I/O area */
304
-
map_section(0x38000000, 0x38000000, 0x80, CACHE_NONE);
304
+
map_section(IO_BASE, IO_BASE, 0x80, CACHE_NONE);
305
305
306
306
/* map RAM uncached addresses */
307
307
map_section(0, S5L8702_UNCACHED_ADDR(0x0), 0x380, CACHE_NONE);