"Das U-Boot" Source Tree
clk: rockchip: rk3128: Support more mmc clocks
Support setting and getting all required clocks rates for sdmmc and emmc.
Also replace function prefix from rockchip_ to more appropriate rk3128_.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
authored by
Alex Bee
and committed by
joshua stein
6d12d063
d03bde81
+14
-13
+14
-13
drivers/clk/rockchip/clk_rk3128.c
+14
-13
drivers/clk/rockchip/clk_rk3128.c
···
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
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int periph)
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static ulong rk3128_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
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int periph)
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{
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uint src_rate;
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uint div, mux;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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case SCLK_EMMC_SAMPLE:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
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div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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con = readl(&cru->cru_clksel_con[11]);
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mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
···
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return DIV_TO_RATE(src_rate, div);
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}
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static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
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int periph, uint freq)
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static ulong rk3128_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
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int periph, uint freq)
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{
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int src_clk_div;
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int mux;
···
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}
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_PLL_MASK | EMMC_DIV_MASK,
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mux << EMMC_PLL_SHIFT |
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK | MMC0_DIV_MASK,
···
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
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return rk3128_mmc_get_clk(cru, clk_general_rate, periph);
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}
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static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
···
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static ulong rk3128_clk_get_rate(struct clk *clk)
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{
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struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
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ulong gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
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switch (clk->id) {
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case 0 ... 63:
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return rkclk_pll_get_rate(priv->cru, clk->id);
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case SCLK_EMMC:
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case SCLK_SDMMC:
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return rk3128_mmc_get_clk(priv->cru, gclk_rate, clk->id);
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case PCLK_I2C0:
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case PCLK_I2C1:
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case PCLK_I2C2:
···
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new_rate = rk3128_vop_set_clk(priv->cru,
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clk->id, rate);
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break;
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case HCLK_EMMC:
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new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
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clk->id, rate);
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case SCLK_EMMC:
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case SCLK_SDMMC:
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new_rate = rk3128_mmc_set_clk(priv->cru, gclk_rate,
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clk->id, rate);
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break;
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case PCLK_I2C0:
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case PCLK_I2C1: