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clk: rockchip: rk3128: Fix PLL lock condition

A PLL is locked if the respective bit is set, thus we have to wait until
is set.

Signed-off-by: Alex Bee <knaerzche@gmail.com>

authored by

Alex Bee and committed by
joshua stein d03bde81 e37de002

+1 -1
+1 -1
drivers/clk/rockchip/clk_rk3128.c
··· 69 69 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 70 70 71 71 /* waiting for pll lock */ 72 - while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 72 + while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 73 73 udelay(1); 74 74 75 75 return 0;