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arm: rockchip: Drop GRF_GPIOXX_IOMUX enums from RK3128's GRF header

Those enums are not used anywhere for RK3128 and they will cause problems
if both RK3128's and RK3288's grf header is included in a driver, because
RK3288's grf header defines enums with members which have exactly the same
name as these.
If they are required, they can be defined inline as it is done for most
other Rockchip SoCs.

Signed-off-by: Alex Bee <knaerzche@gmail.com>

authored by

Alex Bee and committed by
joshua stein e10b277a 8657fc04

-452
-452
arch/arm/include/asm/arch-rockchip/grf_rk3128.h
··· 94 94 }; 95 95 check_member(rk3128_pmu, int_st, 0x34); 96 96 97 - /* GRF_GPIO0A_IOMUX */ 98 - enum { 99 - GPIO0A7_SHIFT = 14, 100 - GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, 101 - GPIO0A7_GPIO = 0, 102 - GPIO0A7_I2C3_SDA, 103 - 104 - GPIO0A6_SHIFT = 12, 105 - GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, 106 - GPIO0A6_GPIO = 0, 107 - GPIO0A6_I2C3_SCL, 108 - 109 - GPIO0A3_SHIFT = 6, 110 - GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, 111 - GPIO0A3_GPIO = 0, 112 - GPIO0A3_I2C1_SDA, 113 - 114 - GPIO0A2_SHIFT = 4, 115 - GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, 116 - GPIO0A2_GPIO = 0, 117 - GPIO0A2_I2C1_SCL, 118 - 119 - GPIO0A1_SHIFT = 2, 120 - GPIO0A1_MASK = 1 << GPIO0A1_SHIFT, 121 - GPIO0A1_GPIO = 0, 122 - GPIO0A1_I2C0_SDA, 123 - 124 - GPIO0A0_SHIFT = 0, 125 - GPIO0A0_MASK = 1 << GPIO0A0_SHIFT, 126 - GPIO0A0_GPIO = 0, 127 - GPIO0A0_I2C0_SCL, 128 - }; 129 - 130 - /* GRF_GPIO0B_IOMUX */ 131 - enum { 132 - GPIO0B6_SHIFT = 12, 133 - GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, 134 - GPIO0B6_GPIO = 0, 135 - GPIO0B6_I2S_SDI, 136 - GPIO0B6_SPI_CSN0, 137 - 138 - GPIO0B5_SHIFT = 10, 139 - GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, 140 - GPIO0B5_GPIO = 0, 141 - GPIO0B5_I2S_SDO, 142 - GPIO0B5_SPI_RXD, 143 - 144 - GPIO0B4_SHIFT = 8, 145 - GPIO0B4_MASK = 1 << GPIO0B4_SHIFT, 146 - GPIO0B4_GPIO = 0, 147 - GPIO0B4_I2S_LRCKTX, 148 - 149 - GPIO0B3_SHIFT = 6, 150 - GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, 151 - GPIO0B3_GPIO = 0, 152 - GPIO0B3_I2S_LRCKRX, 153 - GPIO0B3_SPI_TXD, 154 - 155 - GPIO0B1_SHIFT = 2, 156 - GPIO0B1_MASK = 3, 157 - GPIO0B1_GPIO = 0, 158 - GPIO0B1_I2S_SCLK, 159 - GPIO0B1_SPI_CLK, 160 - 161 - GPIO0B0_SHIFT = 0, 162 - GPIO0B0_MASK = 3, 163 - GPIO0B0_GPIO = 0, 164 - GPIO0B0_I2S1_MCLK, 165 - }; 166 - 167 - /* GRF_GPIO0D_IOMUX */ 168 - enum { 169 - GPIO0D4_SHIFT = 8, 170 - GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, 171 - GPIO0D4_GPIO = 0, 172 - GPIO0D4_PWM2, 173 - 174 - GPIO0D3_SHIFT = 6, 175 - GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, 176 - GPIO0D3_GPIO = 0, 177 - GPIO0D3_PWM1, 178 - 179 - GPIO0D2_SHIFT = 4, 180 - GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, 181 - GPIO0D2_GPIO = 0, 182 - GPIO0D2_PWM0, 183 - 184 - GPIO0D1_SHIFT = 2, 185 - GPIO0D1_MASK = 1 << GPIO0D1_SHIFT, 186 - GPIO0D1_GPIO = 0, 187 - GPIO0D1_UART2_CTSN, 188 - 189 - GPIO0D0_SHIFT = 0, 190 - GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, 191 - GPIO0D0_GPIO = 0, 192 - GPIO0D0_UART2_RTSN, 193 - GPIO0D0_PMIC_SLEEP, 194 - }; 195 - 196 - /* GRF_GPIO1A_IOMUX */ 197 - enum { 198 - GPIO1A5_SHIFT = 10, 199 - GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, 200 - GPIO1A5_GPIO = 0, 201 - GPIO1A5_I2S_SDI, 202 - GPIO1A5_SDMMC_DATA3, 203 - 204 - GPIO1A4_SHIFT = 8, 205 - GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, 206 - GPIO1A4_GPIO = 0, 207 - GPIO1A4_I2S_SD0, 208 - GPIO1A4_SDMMC_DATA2, 209 - 210 - GPIO1A3_SHIFT = 6, 211 - GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, 212 - GPIO1A3_GPIO = 0, 213 - GPIO1A3_I2S_LRCKTX, 214 - 215 - GPIO1A2_SHIFT = 4, 216 - GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, 217 - GPIO1A2_GPIO = 0, 218 - GPIO1A2_I2S_LRCKRX, 219 - GPIO1A2_SDMMC_DATA1, 220 - 221 - GPIO1A1_SHIFT = 2, 222 - GPIO1A1_MASK = 3 << GPIO1A1_SHIFT, 223 - GPIO1A1_GPIO = 0, 224 - GPIO1A1_I2S_SCLK, 225 - GPIO1A1_SDMMC_DATA0, 226 - GPIO1A1_PMIC_SLEEP, 227 - 228 - GPIO1A0_SHIFT = 0, 229 - GPIO1A0_MASK = 3, 230 - GPIO1A0_GPIO = 0, 231 - GPIO1A0_I2S_MCLK, 232 - GPIO1A0_SDMMC_CLKOUT, 233 - GPIO1A0_XIN32K, 234 - 235 - }; 236 - 237 - /* GRF_GPIO1B_IOMUX */ 238 - enum { 239 - GPIO1B7_SHIFT = 14, 240 - GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, 241 - GPIO1B7_GPIO = 0, 242 - GPIO1B7_MMC0_CMD, 243 - 244 - GPIO1B6_SHIFT = 12, 245 - GPIO1B6_MASK = 1 << GPIO1B6_SHIFT, 246 - GPIO1B6_GPIO = 0, 247 - GPIO1B6_MMC_PWREN, 248 - 249 - GPIO1B2_SHIFT = 4, 250 - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, 251 - GPIO1B2_GPIO = 0, 252 - GPIO1B2_SPI_RXD, 253 - GPIO1B2_UART1_SIN, 254 - 255 - GPIO1B1_SHIFT = 2, 256 - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, 257 - GPIO1B1_GPIO = 0, 258 - GPIO1B1_SPI_TXD, 259 - GPIO1B1_UART1_SOUT, 260 - 261 - GPIO1B0_SHIFT = 0, 262 - GPIO1B0_MASK = 3 << GPIO1B0_SHIFT, 263 - GPIO1B0_GPIO = 0, 264 - GPIO1B0_SPI_CLK, 265 - GPIO1B0_UART1_CTSN 266 - }; 267 - 268 - /* GRF_GPIO1C_IOMUX */ 269 - enum { 270 - GPIO1C6_SHIFT = 12, 271 - GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, 272 - GPIO1C6_GPIO = 0, 273 - GPIO1C6_NAND_CS2, 274 - GPIO1C6_EMMC_CMD, 275 - 276 - GPIO1C5_SHIFT = 10, 277 - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, 278 - GPIO1C5_GPIO = 0, 279 - GPIO1C5_MMC0_D3, 280 - GPIO1C5_JTAG_TMS, 281 - 282 - GPIO1C4_SHIFT = 8, 283 - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, 284 - GPIO1C4_GPIO = 0, 285 - GPIO1C4_MMC0_D2, 286 - GPIO1C4_JTAG_TCK, 287 - 288 - GPIO1C3_SHIFT = 6, 289 - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, 290 - GPIO1C3_GPIO = 0, 291 - GPIO1C3_MMC0_D1, 292 - GPIO1C3_UART2_RX, 293 - 294 - GPIO1C2_SHIFT = 4, 295 - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, 296 - GPIO1C2_GPIO = 0, 297 - GPIO1C2_MMC0_D0, 298 - GPIO1C2_UART2_TX, 299 - 300 - GPIO1C1_SHIFT = 2, 301 - GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, 302 - GPIO1C1_GPIO = 0, 303 - GPIO1C1_MMC0_DETN, 304 - 305 - GPIO1C0_SHIFT = 0, 306 - GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, 307 - GPIO1C0_GPIO = 0, 308 - GPIO1C0_MMC0_CLKOUT, 309 - }; 310 - 311 - /* GRF_GPIO1D_IOMUX */ 312 - enum { 313 - GPIO1D7_SHIFT = 14, 314 - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, 315 - GPIO1D7_GPIO = 0, 316 - GPIO1D7_NAND_D7, 317 - GPIO1D7_EMMC_D7, 318 - GPIO1D7_SPI_CSN1, 319 - 320 - GPIO1D6_SHIFT = 12, 321 - GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, 322 - GPIO1D6_GPIO = 0, 323 - GPIO1D6_NAND_D6, 324 - GPIO1D6_EMMC_D6, 325 - GPIO1D6_SPI_CSN0, 326 - 327 - GPIO1D5_SHIFT = 10, 328 - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, 329 - GPIO1D5_GPIO = 0, 330 - GPIO1D5_NAND_D5, 331 - GPIO1D5_EMMC_D5, 332 - GPIO1D5_SPI_TXD1, 333 - 334 - GPIO1D4_SHIFT = 8, 335 - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, 336 - GPIO1D4_GPIO = 0, 337 - GPIO1D4_NAND_D4, 338 - GPIO1D4_EMMC_D4, 339 - GPIO1D4_SPI_RXD1, 340 - 341 - GPIO1D3_SHIFT = 6, 342 - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, 343 - GPIO1D3_GPIO = 0, 344 - GPIO1D3_NAND_D3, 345 - GPIO1D3_EMMC_D3, 346 - GPIO1D3_SFC_SIO3, 347 - 348 - GPIO1D2_SHIFT = 4, 349 - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, 350 - GPIO1D2_GPIO = 0, 351 - GPIO1D2_NAND_D2, 352 - GPIO1D2_EMMC_D2, 353 - GPIO1D2_SFC_SIO2, 354 - 355 - GPIO1D1_SHIFT = 2, 356 - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, 357 - GPIO1D1_GPIO = 0, 358 - GPIO1D1_NAND_D1, 359 - GPIO1D1_EMMC_D1, 360 - GPIO1D1_SFC_SIO1, 361 - 362 - GPIO1D0_SHIFT = 0, 363 - GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, 364 - GPIO1D0_GPIO = 0, 365 - GPIO1D0_NAND_D0, 366 - GPIO1D0_EMMC_D0, 367 - GPIO1D0_SFC_SIO0, 368 - }; 369 - 370 - /* GRF_GPIO2A_IOMUX */ 371 - enum { 372 - GPIO2A7_SHIFT = 14, 373 - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, 374 - GPIO2A7_GPIO = 0, 375 - GPIO2A7_NAND_DQS, 376 - GPIO2A7_EMMC_CLKOUT, 377 - 378 - GPIO2A6_SHIFT = 12, 379 - GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, 380 - GPIO2A6_GPIO = 0, 381 - GPIO2A6_NAND_CS0, 382 - 383 - GPIO2A5_SHIFT = 10, 384 - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, 385 - GPIO2A5_GPIO = 0, 386 - GPIO2A5_NAND_WP, 387 - GPIO2A5_EMMC_PWREN, 388 - 389 - GPIO2A4_SHIFT = 8, 390 - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, 391 - GPIO2A4_GPIO = 0, 392 - GPIO2A4_NAND_RDY, 393 - GPIO2A4_EMMC_CMD, 394 - GPIO2A3_SFC_CLK, 395 - 396 - GPIO2A3_SHIFT = 6, 397 - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, 398 - GPIO2A3_GPIO = 0, 399 - GPIO2A3_NAND_RDN, 400 - GPIO2A4_SFC_CSN1, 401 - 402 - GPIO2A2_SHIFT = 4, 403 - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, 404 - GPIO2A2_GPIO = 0, 405 - GPIO2A2_NAND_WRN, 406 - GPIO2A4_SFC_CSN0, 407 - 408 - GPIO2A1_SHIFT = 2, 409 - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, 410 - GPIO2A1_GPIO = 0, 411 - GPIO2A1_NAND_CLE, 412 - GPIO2A1_EMMC_CLKOUT, 413 - 414 - GPIO2A0_SHIFT = 0, 415 - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, 416 - GPIO2A0_GPIO = 0, 417 - GPIO2A0_NAND_ALE, 418 - GPIO2A0_SPI_CLK, 419 - }; 420 - 421 - /* GRF_GPIO2B_IOMUX */ 422 - enum { 423 - GPIO2B7_SHIFT = 14, 424 - GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, 425 - GPIO2B7_GPIO = 0, 426 - GPIO2B7_LCDC0_D13, 427 - GPIO2B7_EBC_SDCE5, 428 - GPIO2B7_GMAC_RXER, 429 - 430 - GPIO2B6_SHIFT = 12, 431 - GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, 432 - GPIO2B6_GPIO = 0, 433 - GPIO2B6_LCDC0_D12, 434 - GPIO2B6_EBC_SDCE4, 435 - GPIO2B6_GMAC_CLK, 436 - 437 - GPIO2B5_SHIFT = 10, 438 - GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, 439 - GPIO2B5_GPIO = 0, 440 - GPIO2B5_LCDC0_D11, 441 - GPIO2B5_EBC_SDCE3, 442 - GPIO2B5_GMAC_TXEN, 443 - 444 - GPIO2B4_SHIFT = 8, 445 - GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, 446 - GPIO2B4_GPIO = 0, 447 - GPIO2B4_LCDC0_D10, 448 - GPIO2B4_EBC_SDCE2, 449 - GPIO2B4_GMAC_MDIO, 450 - 451 - GPIO2B3_SHIFT = 6, 452 - GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, 453 - GPIO2B3_GPIO = 0, 454 - GPIO2B3_LCDC0_DEN, 455 - GPIO2B3_EBC_GDCLK, 456 - GPIO2B3_GMAC_RXCLK, 457 - 458 - GPIO2B2_SHIFT = 4, 459 - GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, 460 - GPIO2B2_GPIO = 0, 461 - GPIO2B2_LCDC0_VSYNC, 462 - GPIO2B2_EBC_SDOE, 463 - GPIO2B2_GMAC_CRS, 464 - 465 - GPIO2B1_SHIFT = 2, 466 - GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, 467 - GPIO2B1_GPIO = 0, 468 - GPIO2B1_LCDC0_HSYNC, 469 - GPIO2B1_EBC_SDLE, 470 - GPIO2B1_GMAC_TXCLK, 471 - 472 - GPIO2B0_SHIFT = 0, 473 - GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, 474 - GPIO2B0_GPIO = 0, 475 - GPIO2B0_LCDC0_DCLK, 476 - GPIO2B0_EBC_SDCLK, 477 - GPIO2B0_GMAC_RXDV, 478 - }; 479 - 480 - /* GRF_GPIO2C_IOMUX */ 481 - enum { 482 - GPIO2C3_SHIFT = 6, 483 - GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, 484 - GPIO2C3_GPIO = 0, 485 - GPIO2C3_LCDC0_D17, 486 - GPIO2C3_EBC_GDPWR0, 487 - GPIO2C3_GMAC_TXD0, 488 - 489 - GPIO2C2_SHIFT = 4, 490 - GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, 491 - GPIO2C2_GPIO = 0, 492 - GPIO2C2_LCDC0_D16, 493 - GPIO2C2_EBC_GDSP, 494 - GPIO2C2_GMAC_TXD1, 495 - 496 - GPIO2C1_SHIFT = 2, 497 - GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, 498 - GPIO2C1_GPIO = 0, 499 - GPIO2C1_LCDC0_D15, 500 - GPIO2C1_EBC_GDOE, 501 - GPIO2C1_GMAC_RXD0, 502 - 503 - GPIO2C0_SHIFT = 0, 504 - GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, 505 - GPIO2C0_GPIO = 0, 506 - GPIO2C0_LCDC0_D14, 507 - GPIO2C0_EBC_VCOM, 508 - GPIO2C0_GMAC_RXD1, 509 - }; 510 - 511 - /* GRF_GPIO2D_IOMUX */ 512 - enum { 513 - GPIO2D6_SHIFT = 12, 514 - GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, 515 - GPIO2D6_GPIO = 0, 516 - GPIO2D6_LCDC0_D22, 517 - GPIO2D6_GMAC_COL = 4, 518 - 519 - GPIO2D1_SHIFT = 2, 520 - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, 521 - GPIO2D1_GPIO = 0, 522 - GPIO2D1_GMAC_MDC = 3, 523 - }; 524 - 525 - /* GRF_GPIO2C_IOMUX2 */ 526 - enum { 527 - GPIO2C7_SHIFT = 12, 528 - GPIO2C7_MASK = 7 << GPIO2C7_SHIFT, 529 - GPIO2C7_GPIO = 0, 530 - GPIO2C7_GMAC_TXD3 = 4, 531 - 532 - GPIO2C6_SHIFT = 12, 533 - GPIO2C6_MASK = 7 << GPIO2C6_SHIFT, 534 - GPIO2C6_GPIO = 0, 535 - GPIO2C6_GMAC_TXD2 = 4, 536 - 537 - GPIO2C5_SHIFT = 4, 538 - GPIO2C5_MASK = 7 << GPIO2C5_SHIFT, 539 - GPIO2C5_GPIO = 0, 540 - GPIO2C5_I2C2_SCL = 3, 541 - GPIO2C5_GMAC_RXD2, 542 - 543 - GPIO2C4_SHIFT = 0, 544 - GPIO2C4_MASK = 7 << GPIO2C4_SHIFT, 545 - GPIO2C4_GPIO = 0, 546 - GPIO2C4_I2C2_SDA = 3, 547 - GPIO2C4_GMAC_RXD2, 548 - }; 549 97 #endif