tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Clean the functions pointer set as NULL

We dont need to set the functions to NULL which arent
needed as global structure members are by default
set to zero or NULL for pointers.

Cc: Leo Liu <leo.liu@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sunil Khatri and committed by
Alex Deucher 0016e870 8231e3af

-228
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
··· 603 603 604 604 static const struct amd_ip_funcs acp_ip_funcs = { 605 605 .name = "acp_ip", 606 - .early_init = NULL, 607 - .late_init = NULL, 608 606 .sw_init = acp_sw_init, 609 607 .sw_fini = acp_sw_fini, 610 608 .hw_init = acp_hw_init, ··· 612 614 .is_idle = acp_is_idle, 613 615 .set_clockgating_state = acp_set_clockgating_state, 614 616 .set_powergating_state = acp_set_powergating_state, 615 - .dump_ip_state = NULL, 616 - .print_ip_state = NULL, 617 617 }; 618 618 619 619 const struct amdgpu_ip_block_version acp_ip_block = {
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
··· 143 143 static const struct amd_ip_funcs isp_ip_funcs = { 144 144 .name = "isp_ip", 145 145 .early_init = isp_early_init, 146 - .late_init = NULL, 147 146 .hw_init = isp_hw_init, 148 147 .hw_fini = isp_hw_fini, 149 148 .is_idle = isp_is_idle,
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 4095 4095 const struct amd_ip_funcs psp_ip_funcs = { 4096 4096 .name = "psp", 4097 4097 .early_init = psp_early_init, 4098 - .late_init = NULL, 4099 4098 .sw_init = psp_sw_init, 4100 4099 .sw_fini = psp_sw_fini, 4101 4100 .hw_init = psp_hw_init, 4102 4101 .hw_fini = psp_hw_fini, 4103 4102 .suspend = psp_suspend, 4104 4103 .resume = psp_resume, 4105 - .is_idle = NULL, 4106 - .check_soft_reset = NULL, 4107 - .wait_for_idle = NULL, 4108 - .soft_reset = NULL, 4109 4104 .set_clockgating_state = psp_set_clockgating_state, 4110 4105 .set_powergating_state = psp_set_powergating_state, 4111 4106 };
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
··· 993 993 .hw_fini = umsch_mm_hw_fini, 994 994 .suspend = umsch_mm_suspend, 995 995 .resume = umsch_mm_resume, 996 - .dump_ip_state = NULL, 997 - .print_ip_state = NULL, 998 996 }; 999 997 1000 998 const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
··· 646 646 647 647 static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { 648 648 .name = "amdgpu_vkms", 649 - .early_init = NULL, 650 - .late_init = NULL, 651 649 .sw_init = amdgpu_vkms_sw_init, 652 650 .sw_fini = amdgpu_vkms_sw_fini, 653 651 .hw_init = amdgpu_vkms_hw_init, ··· 655 657 .is_idle = amdgpu_vkms_is_idle, 656 658 .set_clockgating_state = amdgpu_vkms_set_clockgating_state, 657 659 .set_powergating_state = amdgpu_vkms_set_powergating_state, 658 - .dump_ip_state = NULL, 659 - .print_ip_state = NULL, 660 660 }; 661 661 662 662 const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
··· 906 906 const struct amd_ip_funcs vpe_ip_funcs = { 907 907 .name = "vpe_v6_1", 908 908 .early_init = vpe_early_init, 909 - .late_init = NULL, 910 909 .sw_init = vpe_sw_init, 911 910 .sw_fini = vpe_sw_fini, 912 911 .hw_init = vpe_hw_init, 913 912 .hw_fini = vpe_hw_fini, 914 913 .suspend = vpe_suspend, 915 914 .resume = vpe_resume, 916 - .soft_reset = NULL, 917 915 .set_clockgating_state = vpe_set_clockgating_state, 918 916 .set_powergating_state = vpe_set_powergating_state, 919 917 };
-3
drivers/gpu/drm/amd/amdgpu/cik.c
··· 2176 2176 static const struct amd_ip_funcs cik_common_ip_funcs = { 2177 2177 .name = "cik_common", 2178 2178 .early_init = cik_common_early_init, 2179 - .late_init = NULL, 2180 2179 .hw_init = cik_common_hw_init, 2181 2180 .hw_fini = cik_common_hw_fini, 2182 2181 .resume = cik_common_resume, ··· 2183 2184 .soft_reset = cik_common_soft_reset, 2184 2185 .set_clockgating_state = cik_common_set_clockgating_state, 2185 2186 .set_powergating_state = cik_common_set_powergating_state, 2186 - .dump_ip_state = NULL, 2187 - .print_ip_state = NULL, 2188 2187 }; 2189 2188 2190 2189 static const struct amdgpu_ip_block_version cik_common_ip_block =
-3
drivers/gpu/drm/amd/amdgpu/cik_ih.c
··· 417 417 static const struct amd_ip_funcs cik_ih_ip_funcs = { 418 418 .name = "cik_ih", 419 419 .early_init = cik_ih_early_init, 420 - .late_init = NULL, 421 420 .sw_init = cik_ih_sw_init, 422 421 .sw_fini = cik_ih_sw_fini, 423 422 .hw_init = cik_ih_hw_init, ··· 428 429 .soft_reset = cik_ih_soft_reset, 429 430 .set_clockgating_state = cik_ih_set_clockgating_state, 430 431 .set_powergating_state = cik_ih_set_powergating_state, 431 - .dump_ip_state = NULL, 432 - .print_ip_state = NULL, 433 432 }; 434 433 435 434 static const struct amdgpu_ih_funcs cik_ih_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
··· 1213 1213 static const struct amd_ip_funcs cik_sdma_ip_funcs = { 1214 1214 .name = "cik_sdma", 1215 1215 .early_init = cik_sdma_early_init, 1216 - .late_init = NULL, 1217 1216 .sw_init = cik_sdma_sw_init, 1218 1217 .sw_fini = cik_sdma_sw_fini, 1219 1218 .hw_init = cik_sdma_hw_init, ··· 1224 1225 .soft_reset = cik_sdma_soft_reset, 1225 1226 .set_clockgating_state = cik_sdma_set_clockgating_state, 1226 1227 .set_powergating_state = cik_sdma_set_powergating_state, 1227 - .dump_ip_state = NULL, 1228 - .print_ip_state = NULL, 1229 1228 }; 1230 1229 1231 1230 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/cz_ih.c
··· 415 415 static const struct amd_ip_funcs cz_ih_ip_funcs = { 416 416 .name = "cz_ih", 417 417 .early_init = cz_ih_early_init, 418 - .late_init = NULL, 419 418 .sw_init = cz_ih_sw_init, 420 419 .sw_fini = cz_ih_sw_fini, 421 420 .hw_init = cz_ih_hw_init, ··· 426 427 .soft_reset = cz_ih_soft_reset, 427 428 .set_clockgating_state = cz_ih_set_clockgating_state, 428 429 .set_powergating_state = cz_ih_set_powergating_state, 429 - .dump_ip_state = NULL, 430 - .print_ip_state = NULL, 431 430 }; 432 431 433 432 static const struct amdgpu_ih_funcs cz_ih_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 3317 3317 static const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3318 3318 .name = "dce_v10_0", 3319 3319 .early_init = dce_v10_0_early_init, 3320 - .late_init = NULL, 3321 3320 .sw_init = dce_v10_0_sw_init, 3322 3321 .sw_fini = dce_v10_0_sw_fini, 3323 3322 .hw_init = dce_v10_0_hw_init, ··· 3328 3329 .soft_reset = dce_v10_0_soft_reset, 3329 3330 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3330 3331 .set_powergating_state = dce_v10_0_set_powergating_state, 3331 - .dump_ip_state = NULL, 3332 - .print_ip_state = NULL, 3333 3332 }; 3334 3333 3335 3334 static void
-3
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 3449 3449 static const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3450 3450 .name = "dce_v11_0", 3451 3451 .early_init = dce_v11_0_early_init, 3452 - .late_init = NULL, 3453 3452 .sw_init = dce_v11_0_sw_init, 3454 3453 .sw_fini = dce_v11_0_sw_fini, 3455 3454 .hw_init = dce_v11_0_hw_init, ··· 3459 3460 .soft_reset = dce_v11_0_soft_reset, 3460 3461 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3461 3462 .set_powergating_state = dce_v11_0_set_powergating_state, 3462 - .dump_ip_state = NULL, 3463 - .print_ip_state = NULL, 3464 3463 }; 3465 3464 3466 3465 static void
-3
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 3139 3139 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3140 3140 .name = "dce_v6_0", 3141 3141 .early_init = dce_v6_0_early_init, 3142 - .late_init = NULL, 3143 3142 .sw_init = dce_v6_0_sw_init, 3144 3143 .sw_fini = dce_v6_0_sw_fini, 3145 3144 .hw_init = dce_v6_0_hw_init, ··· 3149 3150 .soft_reset = dce_v6_0_soft_reset, 3150 3151 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3151 3152 .set_powergating_state = dce_v6_0_set_powergating_state, 3152 - .dump_ip_state = NULL, 3153 - .print_ip_state = NULL, 3154 3153 }; 3155 3154 3156 3155 static void
-3
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 3227 3227 static const struct amd_ip_funcs dce_v8_0_ip_funcs = { 3228 3228 .name = "dce_v8_0", 3229 3229 .early_init = dce_v8_0_early_init, 3230 - .late_init = NULL, 3231 3230 .sw_init = dce_v8_0_sw_init, 3232 3231 .sw_fini = dce_v8_0_sw_fini, 3233 3232 .hw_init = dce_v8_0_hw_init, ··· 3237 3238 .soft_reset = dce_v8_0_soft_reset, 3238 3239 .set_clockgating_state = dce_v8_0_set_clockgating_state, 3239 3240 .set_powergating_state = dce_v8_0_set_powergating_state, 3240 - .dump_ip_state = NULL, 3241 - .print_ip_state = NULL, 3242 3241 }; 3243 3242 3244 3243 static void
-3
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
··· 3435 3435 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3436 3436 .name = "gfx_v6_0", 3437 3437 .early_init = gfx_v6_0_early_init, 3438 - .late_init = NULL, 3439 3438 .sw_init = gfx_v6_0_sw_init, 3440 3439 .sw_fini = gfx_v6_0_sw_fini, 3441 3440 .hw_init = gfx_v6_0_hw_init, ··· 3445 3446 .wait_for_idle = gfx_v6_0_wait_for_idle, 3446 3447 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3447 3448 .set_powergating_state = gfx_v6_0_set_powergating_state, 3448 - .dump_ip_state = NULL, 3449 - .print_ip_state = NULL, 3450 3449 }; 3451 3450 3452 3451 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
-2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
··· 5005 5005 .soft_reset = gfx_v7_0_soft_reset, 5006 5006 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 5007 5007 .set_powergating_state = gfx_v7_0_set_powergating_state, 5008 - .dump_ip_state = NULL, 5009 - .print_ip_state = NULL, 5010 5008 }; 5011 5009 5012 5010 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
-2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 6948 6948 .set_clockgating_state = gfx_v8_0_set_clockgating_state, 6949 6949 .set_powergating_state = gfx_v8_0_set_powergating_state, 6950 6950 .get_clockgating_state = gfx_v8_0_get_clockgating_state, 6951 - .dump_ip_state = NULL, 6952 - .print_ip_state = NULL, 6953 6951 }; 6954 6952 6955 6953 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
-2
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
··· 1121 1121 .soft_reset = gmc_v6_0_soft_reset, 1122 1122 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1123 1123 .set_powergating_state = gmc_v6_0_set_powergating_state, 1124 - .dump_ip_state = NULL, 1125 - .print_ip_state = NULL, 1126 1124 }; 1127 1125 1128 1126 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
-2
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
··· 1348 1348 .soft_reset = gmc_v7_0_soft_reset, 1349 1349 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1350 1350 .set_powergating_state = gmc_v7_0_set_powergating_state, 1351 - .dump_ip_state = NULL, 1352 - .print_ip_state = NULL, 1353 1351 }; 1354 1352 1355 1353 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
-2
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
··· 1722 1722 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1723 1723 .set_powergating_state = gmc_v8_0_set_powergating_state, 1724 1724 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1725 - .dump_ip_state = NULL, 1726 - .print_ip_state = NULL, 1727 1725 }; 1728 1726 1729 1727 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
··· 407 407 static const struct amd_ip_funcs iceland_ih_ip_funcs = { 408 408 .name = "iceland_ih", 409 409 .early_init = iceland_ih_early_init, 410 - .late_init = NULL, 411 410 .sw_init = iceland_ih_sw_init, 412 411 .sw_fini = iceland_ih_sw_fini, 413 412 .hw_init = iceland_ih_hw_init, ··· 418 419 .soft_reset = iceland_ih_soft_reset, 419 420 .set_clockgating_state = iceland_ih_set_clockgating_state, 420 421 .set_powergating_state = iceland_ih_set_powergating_state, 421 - .dump_ip_state = NULL, 422 - .print_ip_state = NULL, 423 422 }; 424 423 425 424 static const struct amdgpu_ih_funcs iceland_ih_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
··· 779 779 static const struct amd_ip_funcs ih_v6_0_ip_funcs = { 780 780 .name = "ih_v6_0", 781 781 .early_init = ih_v6_0_early_init, 782 - .late_init = NULL, 783 782 .sw_init = ih_v6_0_sw_init, 784 783 .sw_fini = ih_v6_0_sw_fini, 785 784 .hw_init = ih_v6_0_hw_init, ··· 791 792 .set_clockgating_state = ih_v6_0_set_clockgating_state, 792 793 .set_powergating_state = ih_v6_0_set_powergating_state, 793 794 .get_clockgating_state = ih_v6_0_get_clockgating_state, 794 - .dump_ip_state = NULL, 795 - .print_ip_state = NULL, 796 795 }; 797 796 798 797 static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
··· 762 762 static const struct amd_ip_funcs ih_v6_1_ip_funcs = { 763 763 .name = "ih_v6_1", 764 764 .early_init = ih_v6_1_early_init, 765 - .late_init = NULL, 766 765 .sw_init = ih_v6_1_sw_init, 767 766 .sw_fini = ih_v6_1_sw_fini, 768 767 .hw_init = ih_v6_1_hw_init, ··· 774 775 .set_clockgating_state = ih_v6_1_set_clockgating_state, 775 776 .set_powergating_state = ih_v6_1_set_powergating_state, 776 777 .get_clockgating_state = ih_v6_1_get_clockgating_state, 777 - .dump_ip_state = NULL, 778 - .print_ip_state = NULL, 779 778 }; 780 779 781 780 static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
··· 752 752 static const struct amd_ip_funcs ih_v7_0_ip_funcs = { 753 753 .name = "ih_v7_0", 754 754 .early_init = ih_v7_0_early_init, 755 - .late_init = NULL, 756 755 .sw_init = ih_v7_0_sw_init, 757 756 .sw_fini = ih_v7_0_sw_fini, 758 757 .hw_init = ih_v7_0_hw_init, ··· 764 765 .set_clockgating_state = ih_v7_0_set_clockgating_state, 765 766 .set_powergating_state = ih_v7_0_set_powergating_state, 766 767 .get_clockgating_state = ih_v7_0_get_clockgating_state, 767 - .dump_ip_state = NULL, 768 - .print_ip_state = NULL, 769 768 }; 770 769 771 770 static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
-7
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
··· 742 742 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 743 743 .name = "jpeg_v2_0", 744 744 .early_init = jpeg_v2_0_early_init, 745 - .late_init = NULL, 746 745 .sw_init = jpeg_v2_0_sw_init, 747 746 .sw_fini = jpeg_v2_0_sw_fini, 748 747 .hw_init = jpeg_v2_0_hw_init, ··· 750 751 .resume = jpeg_v2_0_resume, 751 752 .is_idle = jpeg_v2_0_is_idle, 752 753 .wait_for_idle = jpeg_v2_0_wait_for_idle, 753 - .check_soft_reset = NULL, 754 - .pre_soft_reset = NULL, 755 - .soft_reset = NULL, 756 - .post_soft_reset = NULL, 757 754 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 758 755 .set_powergating_state = jpeg_v2_0_set_powergating_state, 759 - .dump_ip_state = NULL, 760 - .print_ip_state = NULL, 761 756 }; 762 757 763 758 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
-14
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
··· 613 613 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { 614 614 .name = "jpeg_v2_5", 615 615 .early_init = jpeg_v2_5_early_init, 616 - .late_init = NULL, 617 616 .sw_init = jpeg_v2_5_sw_init, 618 617 .sw_fini = jpeg_v2_5_sw_fini, 619 618 .hw_init = jpeg_v2_5_hw_init, ··· 621 622 .resume = jpeg_v2_5_resume, 622 623 .is_idle = jpeg_v2_5_is_idle, 623 624 .wait_for_idle = jpeg_v2_5_wait_for_idle, 624 - .check_soft_reset = NULL, 625 - .pre_soft_reset = NULL, 626 - .soft_reset = NULL, 627 - .post_soft_reset = NULL, 628 625 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 629 626 .set_powergating_state = jpeg_v2_5_set_powergating_state, 630 - .dump_ip_state = NULL, 631 - .print_ip_state = NULL, 632 627 }; 633 628 634 629 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { 635 630 .name = "jpeg_v2_6", 636 631 .early_init = jpeg_v2_5_early_init, 637 - .late_init = NULL, 638 632 .sw_init = jpeg_v2_5_sw_init, 639 633 .sw_fini = jpeg_v2_5_sw_fini, 640 634 .hw_init = jpeg_v2_5_hw_init, ··· 636 644 .resume = jpeg_v2_5_resume, 637 645 .is_idle = jpeg_v2_5_is_idle, 638 646 .wait_for_idle = jpeg_v2_5_wait_for_idle, 639 - .check_soft_reset = NULL, 640 - .pre_soft_reset = NULL, 641 - .soft_reset = NULL, 642 - .post_soft_reset = NULL, 643 647 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 644 648 .set_powergating_state = jpeg_v2_5_set_powergating_state, 645 - .dump_ip_state = NULL, 646 - .print_ip_state = NULL, 647 649 }; 648 650 649 651 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
-7
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
··· 533 533 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { 534 534 .name = "jpeg_v3_0", 535 535 .early_init = jpeg_v3_0_early_init, 536 - .late_init = NULL, 537 536 .sw_init = jpeg_v3_0_sw_init, 538 537 .sw_fini = jpeg_v3_0_sw_fini, 539 538 .hw_init = jpeg_v3_0_hw_init, ··· 541 542 .resume = jpeg_v3_0_resume, 542 543 .is_idle = jpeg_v3_0_is_idle, 543 544 .wait_for_idle = jpeg_v3_0_wait_for_idle, 544 - .check_soft_reset = NULL, 545 - .pre_soft_reset = NULL, 546 - .soft_reset = NULL, 547 - .post_soft_reset = NULL, 548 545 .set_clockgating_state = jpeg_v3_0_set_clockgating_state, 549 546 .set_powergating_state = jpeg_v3_0_set_powergating_state, 550 - .dump_ip_state = NULL, 551 - .print_ip_state = NULL, 552 547 }; 553 548 554 549 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
-7
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
··· 700 700 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 701 701 .name = "jpeg_v4_0", 702 702 .early_init = jpeg_v4_0_early_init, 703 - .late_init = NULL, 704 703 .sw_init = jpeg_v4_0_sw_init, 705 704 .sw_fini = jpeg_v4_0_sw_fini, 706 705 .hw_init = jpeg_v4_0_hw_init, ··· 708 709 .resume = jpeg_v4_0_resume, 709 710 .is_idle = jpeg_v4_0_is_idle, 710 711 .wait_for_idle = jpeg_v4_0_wait_for_idle, 711 - .check_soft_reset = NULL, 712 - .pre_soft_reset = NULL, 713 - .soft_reset = NULL, 714 - .post_soft_reset = NULL, 715 712 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 716 713 .set_powergating_state = jpeg_v4_0_set_powergating_state, 717 - .dump_ip_state = NULL, 718 - .print_ip_state = NULL, 719 714 }; 720 715 721 716 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
-7
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
··· 1050 1050 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1051 1051 .name = "jpeg_v4_0_3", 1052 1052 .early_init = jpeg_v4_0_3_early_init, 1053 - .late_init = NULL, 1054 1053 .sw_init = jpeg_v4_0_3_sw_init, 1055 1054 .sw_fini = jpeg_v4_0_3_sw_fini, 1056 1055 .hw_init = jpeg_v4_0_3_hw_init, ··· 1058 1059 .resume = jpeg_v4_0_3_resume, 1059 1060 .is_idle = jpeg_v4_0_3_is_idle, 1060 1061 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1061 - .check_soft_reset = NULL, 1062 - .pre_soft_reset = NULL, 1063 - .soft_reset = NULL, 1064 - .post_soft_reset = NULL, 1065 1062 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1066 1063 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1067 - .dump_ip_state = NULL, 1068 - .print_ip_state = NULL, 1069 1064 }; 1070 1065 1071 1066 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
-7
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
··· 741 741 static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = { 742 742 .name = "jpeg_v4_0_5", 743 743 .early_init = jpeg_v4_0_5_early_init, 744 - .late_init = NULL, 745 744 .sw_init = jpeg_v4_0_5_sw_init, 746 745 .sw_fini = jpeg_v4_0_5_sw_fini, 747 746 .hw_init = jpeg_v4_0_5_hw_init, ··· 749 750 .resume = jpeg_v4_0_5_resume, 750 751 .is_idle = jpeg_v4_0_5_is_idle, 751 752 .wait_for_idle = jpeg_v4_0_5_wait_for_idle, 752 - .check_soft_reset = NULL, 753 - .pre_soft_reset = NULL, 754 - .soft_reset = NULL, 755 - .post_soft_reset = NULL, 756 753 .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state, 757 754 .set_powergating_state = jpeg_v4_0_5_set_powergating_state, 758 - .dump_ip_state = NULL, 759 - .print_ip_state = NULL, 760 755 }; 761 756 762 757 static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
-7
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
··· 620 620 static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = { 621 621 .name = "jpeg_v5_0_0", 622 622 .early_init = jpeg_v5_0_0_early_init, 623 - .late_init = NULL, 624 623 .sw_init = jpeg_v5_0_0_sw_init, 625 624 .sw_fini = jpeg_v5_0_0_sw_fini, 626 625 .hw_init = jpeg_v5_0_0_hw_init, ··· 628 629 .resume = jpeg_v5_0_0_resume, 629 630 .is_idle = jpeg_v5_0_0_is_idle, 630 631 .wait_for_idle = jpeg_v5_0_0_wait_for_idle, 631 - .check_soft_reset = NULL, 632 - .pre_soft_reset = NULL, 633 - .soft_reset = NULL, 634 - .post_soft_reset = NULL, 635 632 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state, 636 633 .set_powergating_state = jpeg_v5_0_0_set_powergating_state, 637 - .dump_ip_state = NULL, 638 - .print_ip_state = NULL, 639 634 }; 640 635 641 636 static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
-2
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
··· 1696 1696 .hw_fini = mes_v11_0_hw_fini, 1697 1697 .suspend = mes_v11_0_suspend, 1698 1698 .resume = mes_v11_0_resume, 1699 - .dump_ip_state = NULL, 1700 - .print_ip_state = NULL, 1701 1699 }; 1702 1700 1703 1701 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
-3
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
··· 694 694 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 695 695 .name = "navi10_ih", 696 696 .early_init = navi10_ih_early_init, 697 - .late_init = NULL, 698 697 .sw_init = navi10_ih_sw_init, 699 698 .sw_fini = navi10_ih_sw_fini, 700 699 .hw_init = navi10_ih_hw_init, ··· 706 707 .set_clockgating_state = navi10_ih_set_clockgating_state, 707 708 .set_powergating_state = navi10_ih_set_powergating_state, 708 709 .get_clockgating_state = navi10_ih_get_clockgating_state, 709 - .dump_ip_state = NULL, 710 - .print_ip_state = NULL, 711 710 }; 712 711 713 712 static const struct amdgpu_ih_funcs navi10_ih_funcs = {
-2
drivers/gpu/drm/amd/amdgpu/nv.c
··· 1104 1104 .set_clockgating_state = nv_common_set_clockgating_state, 1105 1105 .set_powergating_state = nv_common_set_powergating_state, 1106 1106 .get_clockgating_state = nv_common_get_clockgating_state, 1107 - .dump_ip_state = NULL, 1108 - .print_ip_state = NULL, 1109 1107 };
-3
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
··· 1096 1096 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1097 1097 .name = "sdma_v2_4", 1098 1098 .early_init = sdma_v2_4_early_init, 1099 - .late_init = NULL, 1100 1099 .sw_init = sdma_v2_4_sw_init, 1101 1100 .sw_fini = sdma_v2_4_sw_fini, 1102 1101 .hw_init = sdma_v2_4_hw_init, ··· 1107 1108 .soft_reset = sdma_v2_4_soft_reset, 1108 1109 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1109 1110 .set_powergating_state = sdma_v2_4_set_powergating_state, 1110 - .dump_ip_state = NULL, 1111 - .print_ip_state = NULL, 1112 1111 }; 1113 1112 1114 1113 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
··· 1534 1534 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1535 1535 .name = "sdma_v3_0", 1536 1536 .early_init = sdma_v3_0_early_init, 1537 - .late_init = NULL, 1538 1537 .sw_init = sdma_v3_0_sw_init, 1539 1538 .sw_fini = sdma_v3_0_sw_fini, 1540 1539 .hw_init = sdma_v3_0_hw_init, ··· 1549 1550 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1550 1551 .set_powergating_state = sdma_v3_0_set_powergating_state, 1551 1552 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1552 - .dump_ip_state = NULL, 1553 - .print_ip_state = NULL, 1554 1553 }; 1555 1554 1556 1555 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
-1
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1929 1929 static const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1930 1930 .name = "sdma_v5_0", 1931 1931 .early_init = sdma_v5_0_early_init, 1932 - .late_init = NULL, 1933 1932 .sw_init = sdma_v5_0_sw_init, 1934 1933 .sw_fini = sdma_v5_0_sw_fini, 1935 1934 .hw_init = sdma_v5_0_hw_init,
-1
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 1918 1918 static const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1919 1919 .name = "sdma_v5_2", 1920 1920 .early_init = sdma_v5_2_early_init, 1921 - .late_init = NULL, 1922 1921 .sw_init = sdma_v5_2_sw_init, 1923 1922 .sw_fini = sdma_v5_2_sw_fini, 1924 1923 .hw_init = sdma_v5_2_hw_init,
-1
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
··· 1644 1644 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1645 1645 .name = "sdma_v6_0", 1646 1646 .early_init = sdma_v6_0_early_init, 1647 - .late_init = NULL, 1648 1647 .sw_init = sdma_v6_0_sw_init, 1649 1648 .sw_fini = sdma_v6_0_sw_fini, 1650 1649 .hw_init = sdma_v6_0_hw_init,
-3
drivers/gpu/drm/amd/amdgpu/si.c
··· 2664 2664 static const struct amd_ip_funcs si_common_ip_funcs = { 2665 2665 .name = "si_common", 2666 2666 .early_init = si_common_early_init, 2667 - .late_init = NULL, 2668 2667 .hw_init = si_common_hw_init, 2669 2668 .hw_fini = si_common_hw_fini, 2670 2669 .resume = si_common_resume, 2671 2670 .is_idle = si_common_is_idle, 2672 2671 .set_clockgating_state = si_common_set_clockgating_state, 2673 2672 .set_powergating_state = si_common_set_powergating_state, 2674 - .dump_ip_state = NULL, 2675 - .print_ip_state = NULL, 2676 2673 }; 2677 2674 2678 2675 static const struct amdgpu_ip_block_version si_common_ip_block =
-3
drivers/gpu/drm/amd/amdgpu/si_dma.c
··· 691 691 static const struct amd_ip_funcs si_dma_ip_funcs = { 692 692 .name = "si_dma", 693 693 .early_init = si_dma_early_init, 694 - .late_init = NULL, 695 694 .sw_init = si_dma_sw_init, 696 695 .sw_fini = si_dma_sw_fini, 697 696 .hw_init = si_dma_hw_init, ··· 702 703 .soft_reset = si_dma_soft_reset, 703 704 .set_clockgating_state = si_dma_set_clockgating_state, 704 705 .set_powergating_state = si_dma_set_powergating_state, 705 - .dump_ip_state = NULL, 706 - .print_ip_state = NULL, 707 706 }; 708 707 709 708 static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/si_ih.c
··· 278 278 static const struct amd_ip_funcs si_ih_ip_funcs = { 279 279 .name = "si_ih", 280 280 .early_init = si_ih_early_init, 281 - .late_init = NULL, 282 281 .sw_init = si_ih_sw_init, 283 282 .sw_fini = si_ih_sw_fini, 284 283 .hw_init = si_ih_hw_init, ··· 289 290 .soft_reset = si_ih_soft_reset, 290 291 .set_clockgating_state = si_ih_set_clockgating_state, 291 292 .set_powergating_state = si_ih_set_powergating_state, 292 - .dump_ip_state = NULL, 293 - .print_ip_state = NULL, 294 293 }; 295 294 296 295 static const struct amdgpu_ih_funcs si_ih_funcs = {
-2
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 1494 1494 .set_clockgating_state = soc15_common_set_clockgating_state, 1495 1495 .set_powergating_state = soc15_common_set_powergating_state, 1496 1496 .get_clockgating_state= soc15_common_get_clockgating_state, 1497 - .dump_ip_state = NULL, 1498 - .print_ip_state = NULL, 1499 1497 };
-2
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 993 993 .set_clockgating_state = soc21_common_set_clockgating_state, 994 994 .set_powergating_state = soc21_common_set_powergating_state, 995 995 .get_clockgating_state = soc21_common_get_clockgating_state, 996 - .dump_ip_state = NULL, 997 - .print_ip_state = NULL, 998 996 };
-3
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
··· 463 463 static const struct amd_ip_funcs tonga_ih_ip_funcs = { 464 464 .name = "tonga_ih", 465 465 .early_init = tonga_ih_early_init, 466 - .late_init = NULL, 467 466 .sw_init = tonga_ih_sw_init, 468 467 .sw_fini = tonga_ih_sw_fini, 469 468 .hw_init = tonga_ih_hw_init, ··· 477 478 .post_soft_reset = tonga_ih_post_soft_reset, 478 479 .set_clockgating_state = tonga_ih_set_clockgating_state, 479 480 .set_powergating_state = tonga_ih_set_powergating_state, 480 - .dump_ip_state = NULL, 481 - .print_ip_state = NULL, 482 481 }; 483 482 484 483 static const struct amdgpu_ih_funcs tonga_ih_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
··· 805 805 static const struct amd_ip_funcs uvd_v3_1_ip_funcs = { 806 806 .name = "uvd_v3_1", 807 807 .early_init = uvd_v3_1_early_init, 808 - .late_init = NULL, 809 808 .sw_init = uvd_v3_1_sw_init, 810 809 .sw_fini = uvd_v3_1_sw_fini, 811 810 .hw_init = uvd_v3_1_hw_init, ··· 817 818 .soft_reset = uvd_v3_1_soft_reset, 818 819 .set_clockgating_state = uvd_v3_1_set_clockgating_state, 819 820 .set_powergating_state = uvd_v3_1_set_powergating_state, 820 - .dump_ip_state = NULL, 821 - .print_ip_state = NULL, 822 821 }; 823 822 824 823 const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
-3
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
··· 755 755 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 756 756 .name = "uvd_v4_2", 757 757 .early_init = uvd_v4_2_early_init, 758 - .late_init = NULL, 759 758 .sw_init = uvd_v4_2_sw_init, 760 759 .sw_fini = uvd_v4_2_sw_fini, 761 760 .hw_init = uvd_v4_2_hw_init, ··· 767 768 .soft_reset = uvd_v4_2_soft_reset, 768 769 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 769 770 .set_powergating_state = uvd_v4_2_set_powergating_state, 770 - .dump_ip_state = NULL, 771 - .print_ip_state = NULL, 772 771 }; 773 772 774 773 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
··· 867 867 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 868 868 .name = "uvd_v5_0", 869 869 .early_init = uvd_v5_0_early_init, 870 - .late_init = NULL, 871 870 .sw_init = uvd_v5_0_sw_init, 872 871 .sw_fini = uvd_v5_0_sw_fini, 873 872 .hw_init = uvd_v5_0_hw_init, ··· 880 881 .set_clockgating_state = uvd_v5_0_set_clockgating_state, 881 882 .set_powergating_state = uvd_v5_0_set_powergating_state, 882 883 .get_clockgating_state = uvd_v5_0_get_clockgating_state, 883 - .dump_ip_state = NULL, 884 - .print_ip_state = NULL, 885 884 }; 886 885 887 886 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
··· 1532 1532 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 1533 1533 .name = "uvd_v6_0", 1534 1534 .early_init = uvd_v6_0_early_init, 1535 - .late_init = NULL, 1536 1535 .sw_init = uvd_v6_0_sw_init, 1537 1536 .sw_fini = uvd_v6_0_sw_fini, 1538 1537 .hw_init = uvd_v6_0_hw_init, ··· 1548 1549 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 1549 1550 .set_powergating_state = uvd_v6_0_set_powergating_state, 1550 1551 .get_clockgating_state = uvd_v6_0_get_clockgating_state, 1551 - .dump_ip_state = NULL, 1552 - .print_ip_state = NULL, 1553 1552 }; 1554 1553 1555 1554 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
-1
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
··· 1789 1789 const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1790 1790 .name = "uvd_v7_0", 1791 1791 .early_init = uvd_v7_0_early_init, 1792 - .late_init = NULL, 1793 1792 .sw_init = uvd_v7_0_sw_init, 1794 1793 .sw_fini = uvd_v7_0_sw_fini, 1795 1794 .hw_init = uvd_v7_0_hw_init,
-3
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
··· 617 617 static const struct amd_ip_funcs vce_v2_0_ip_funcs = { 618 618 .name = "vce_v2_0", 619 619 .early_init = vce_v2_0_early_init, 620 - .late_init = NULL, 621 620 .sw_init = vce_v2_0_sw_init, 622 621 .sw_fini = vce_v2_0_sw_fini, 623 622 .hw_init = vce_v2_0_hw_init, ··· 628 629 .soft_reset = vce_v2_0_soft_reset, 629 630 .set_clockgating_state = vce_v2_0_set_clockgating_state, 630 631 .set_powergating_state = vce_v2_0_set_powergating_state, 631 - .dump_ip_state = NULL, 632 - .print_ip_state = NULL, 633 632 }; 634 633 635 634 static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
-3
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
··· 896 896 static const struct amd_ip_funcs vce_v3_0_ip_funcs = { 897 897 .name = "vce_v3_0", 898 898 .early_init = vce_v3_0_early_init, 899 - .late_init = NULL, 900 899 .sw_init = vce_v3_0_sw_init, 901 900 .sw_fini = vce_v3_0_sw_fini, 902 901 .hw_init = vce_v3_0_hw_init, ··· 911 912 .set_clockgating_state = vce_v3_0_set_clockgating_state, 912 913 .set_powergating_state = vce_v3_0_set_powergating_state, 913 914 .get_clockgating_state = vce_v3_0_get_clockgating_state, 914 - .dump_ip_state = NULL, 915 - .print_ip_state = NULL, 916 915 }; 917 916 918 917 static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
-1
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
··· 1076 1076 const struct amd_ip_funcs vce_v4_0_ip_funcs = { 1077 1077 .name = "vce_v4_0", 1078 1078 .early_init = vce_v4_0_early_init, 1079 - .late_init = NULL, 1080 1079 .sw_init = vce_v4_0_sw_init, 1081 1080 .sw_fini = vce_v4_0_sw_fini, 1082 1081 .hw_init = vce_v4_0_hw_init,
-1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
··· 1987 1987 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1988 1988 .name = "vcn_v1_0", 1989 1989 .early_init = vcn_v1_0_early_init, 1990 - .late_init = NULL, 1991 1990 .sw_init = vcn_v1_0_sw_init, 1992 1991 .sw_fini = vcn_v1_0_sw_fini, 1993 1992 .hw_init = vcn_v1_0_hw_init,
-5
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
··· 2095 2095 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 2096 2096 .name = "vcn_v2_0", 2097 2097 .early_init = vcn_v2_0_early_init, 2098 - .late_init = NULL, 2099 2098 .sw_init = vcn_v2_0_sw_init, 2100 2099 .sw_fini = vcn_v2_0_sw_fini, 2101 2100 .hw_init = vcn_v2_0_hw_init, ··· 2103 2104 .resume = vcn_v2_0_resume, 2104 2105 .is_idle = vcn_v2_0_is_idle, 2105 2106 .wait_for_idle = vcn_v2_0_wait_for_idle, 2106 - .check_soft_reset = NULL, 2107 - .pre_soft_reset = NULL, 2108 - .soft_reset = NULL, 2109 - .post_soft_reset = NULL, 2110 2107 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2111 2108 .set_powergating_state = vcn_v2_0_set_powergating_state, 2112 2109 .dump_ip_state = vcn_v2_0_dump_ip_state,
-10
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 1987 1987 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1988 1988 .name = "vcn_v2_5", 1989 1989 .early_init = vcn_v2_5_early_init, 1990 - .late_init = NULL, 1991 1990 .sw_init = vcn_v2_5_sw_init, 1992 1991 .sw_fini = vcn_v2_5_sw_fini, 1993 1992 .hw_init = vcn_v2_5_hw_init, ··· 1995 1996 .resume = vcn_v2_5_resume, 1996 1997 .is_idle = vcn_v2_5_is_idle, 1997 1998 .wait_for_idle = vcn_v2_5_wait_for_idle, 1998 - .check_soft_reset = NULL, 1999 - .pre_soft_reset = NULL, 2000 - .soft_reset = NULL, 2001 - .post_soft_reset = NULL, 2002 1999 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 2003 2000 .set_powergating_state = vcn_v2_5_set_powergating_state, 2004 2001 .dump_ip_state = vcn_v2_5_dump_ip_state, ··· 2004 2009 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 2005 2010 .name = "vcn_v2_6", 2006 2011 .early_init = vcn_v2_5_early_init, 2007 - .late_init = NULL, 2008 2012 .sw_init = vcn_v2_5_sw_init, 2009 2013 .sw_fini = vcn_v2_5_sw_fini, 2010 2014 .hw_init = vcn_v2_5_hw_init, ··· 2012 2018 .resume = vcn_v2_5_resume, 2013 2019 .is_idle = vcn_v2_5_is_idle, 2014 2020 .wait_for_idle = vcn_v2_5_wait_for_idle, 2015 - .check_soft_reset = NULL, 2016 - .pre_soft_reset = NULL, 2017 - .soft_reset = NULL, 2018 - .post_soft_reset = NULL, 2019 2021 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 2020 2022 .set_powergating_state = vcn_v2_5_set_powergating_state, 2021 2023 .dump_ip_state = vcn_v2_5_dump_ip_state,
-5
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
··· 2313 2313 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2314 2314 .name = "vcn_v3_0", 2315 2315 .early_init = vcn_v3_0_early_init, 2316 - .late_init = NULL, 2317 2316 .sw_init = vcn_v3_0_sw_init, 2318 2317 .sw_fini = vcn_v3_0_sw_fini, 2319 2318 .hw_init = vcn_v3_0_hw_init, ··· 2321 2322 .resume = vcn_v3_0_resume, 2322 2323 .is_idle = vcn_v3_0_is_idle, 2323 2324 .wait_for_idle = vcn_v3_0_wait_for_idle, 2324 - .check_soft_reset = NULL, 2325 - .pre_soft_reset = NULL, 2326 - .soft_reset = NULL, 2327 - .post_soft_reset = NULL, 2328 2325 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2329 2326 .set_powergating_state = vcn_v3_0_set_powergating_state, 2330 2327 .dump_ip_state = vcn_v3_0_dump_ip_state,
-5
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
··· 2220 2220 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2221 2221 .name = "vcn_v4_0", 2222 2222 .early_init = vcn_v4_0_early_init, 2223 - .late_init = NULL, 2224 2223 .sw_init = vcn_v4_0_sw_init, 2225 2224 .sw_fini = vcn_v4_0_sw_fini, 2226 2225 .hw_init = vcn_v4_0_hw_init, ··· 2228 2229 .resume = vcn_v4_0_resume, 2229 2230 .is_idle = vcn_v4_0_is_idle, 2230 2231 .wait_for_idle = vcn_v4_0_wait_for_idle, 2231 - .check_soft_reset = NULL, 2232 - .pre_soft_reset = NULL, 2233 - .soft_reset = NULL, 2234 - .post_soft_reset = NULL, 2235 2232 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2236 2233 .set_powergating_state = vcn_v4_0_set_powergating_state, 2237 2234 .dump_ip_state = vcn_v4_0_dump_ip_state,
-5
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
··· 1796 1796 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1797 1797 .name = "vcn_v4_0_3", 1798 1798 .early_init = vcn_v4_0_3_early_init, 1799 - .late_init = NULL, 1800 1799 .sw_init = vcn_v4_0_3_sw_init, 1801 1800 .sw_fini = vcn_v4_0_3_sw_fini, 1802 1801 .hw_init = vcn_v4_0_3_hw_init, ··· 1804 1805 .resume = vcn_v4_0_3_resume, 1805 1806 .is_idle = vcn_v4_0_3_is_idle, 1806 1807 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1807 - .check_soft_reset = NULL, 1808 - .pre_soft_reset = NULL, 1809 - .soft_reset = NULL, 1810 - .post_soft_reset = NULL, 1811 1808 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1812 1809 .set_powergating_state = vcn_v4_0_3_set_powergating_state, 1813 1810 .dump_ip_state = vcn_v4_0_3_dump_ip_state,
-5
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
··· 1678 1678 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { 1679 1679 .name = "vcn_v4_0_5", 1680 1680 .early_init = vcn_v4_0_5_early_init, 1681 - .late_init = NULL, 1682 1681 .sw_init = vcn_v4_0_5_sw_init, 1683 1682 .sw_fini = vcn_v4_0_5_sw_fini, 1684 1683 .hw_init = vcn_v4_0_5_hw_init, ··· 1686 1687 .resume = vcn_v4_0_5_resume, 1687 1688 .is_idle = vcn_v4_0_5_is_idle, 1688 1689 .wait_for_idle = vcn_v4_0_5_wait_for_idle, 1689 - .check_soft_reset = NULL, 1690 - .pre_soft_reset = NULL, 1691 - .soft_reset = NULL, 1692 - .post_soft_reset = NULL, 1693 1690 .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, 1694 1691 .set_powergating_state = vcn_v4_0_5_set_powergating_state, 1695 1692 .dump_ip_state = vcn_v4_0_5_dump_ip_state,
-5
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
··· 1404 1404 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { 1405 1405 .name = "vcn_v5_0_0", 1406 1406 .early_init = vcn_v5_0_0_early_init, 1407 - .late_init = NULL, 1408 1407 .sw_init = vcn_v5_0_0_sw_init, 1409 1408 .sw_fini = vcn_v5_0_0_sw_fini, 1410 1409 .hw_init = vcn_v5_0_0_hw_init, ··· 1412 1413 .resume = vcn_v5_0_0_resume, 1413 1414 .is_idle = vcn_v5_0_0_is_idle, 1414 1415 .wait_for_idle = vcn_v5_0_0_wait_for_idle, 1415 - .check_soft_reset = NULL, 1416 - .pre_soft_reset = NULL, 1417 - .soft_reset = NULL, 1418 - .post_soft_reset = NULL, 1419 1416 .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, 1420 1417 .set_powergating_state = vcn_v5_0_0_set_powergating_state, 1421 1418 .dump_ip_state = vcn_v5_0_dump_ip_state,
-1
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
··· 625 625 const struct amd_ip_funcs vega10_ih_ip_funcs = { 626 626 .name = "vega10_ih", 627 627 .early_init = vega10_ih_early_init, 628 - .late_init = NULL, 629 628 .sw_init = vega10_ih_sw_init, 630 629 .sw_fini = vega10_ih_sw_fini, 631 630 .hw_init = vega10_ih_hw_init,
-1
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
··· 690 690 const struct amd_ip_funcs vega20_ih_ip_funcs = { 691 691 .name = "vega20_ih", 692 692 .early_init = vega20_ih_early_init, 693 - .late_init = NULL, 694 693 .sw_init = vega20_ih_sw_init, 695 694 .sw_fini = vega20_ih_sw_fini, 696 695 .hw_init = vega20_ih_hw_init,
-2
drivers/gpu/drm/amd/amdgpu/vi.c
··· 2036 2036 .set_clockgating_state = vi_common_set_clockgating_state, 2037 2037 .set_powergating_state = vi_common_set_powergating_state, 2038 2038 .get_clockgating_state = vi_common_get_clockgating_state, 2039 - .dump_ip_state = NULL, 2040 - .print_ip_state = NULL, 2041 2039 }; 2042 2040 2043 2041 static const struct amdgpu_ip_block_version vi_common_ip_block =
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 3407 3407 .soft_reset = dm_soft_reset, 3408 3408 .set_clockgating_state = dm_set_clockgating_state, 3409 3409 .set_powergating_state = dm_set_powergating_state, 3410 - .dump_ip_state = NULL, 3411 - .print_ip_state = NULL, 3412 3410 }; 3413 3411 3414 3412 const struct amdgpu_ip_block_version dm_ip_block = {
-2
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
··· 3304 3304 .is_idle = kv_dpm_is_idle, 3305 3305 .set_clockgating_state = kv_dpm_set_clockgating_state, 3306 3306 .set_powergating_state = kv_dpm_set_powergating_state, 3307 - .dump_ip_state = NULL, 3308 - .print_ip_state = NULL, 3309 3307 }; 3310 3308 3311 3309 const struct amdgpu_ip_block_version kv_smu_ip_block = {
-2
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
··· 8046 8046 .wait_for_idle = si_dpm_wait_for_idle, 8047 8047 .set_clockgating_state = si_dpm_set_clockgating_state, 8048 8048 .set_powergating_state = si_dpm_set_powergating_state, 8049 - .dump_ip_state = NULL, 8050 - .print_ip_state = NULL, 8051 8049 }; 8052 8050 8053 8051 const struct amdgpu_ip_block_version si_smu_ip_block =
-2
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
··· 287 287 .is_idle = pp_is_idle, 288 288 .set_clockgating_state = pp_set_clockgating_state, 289 289 .set_powergating_state = pp_set_powergating_state, 290 - .dump_ip_state = NULL, 291 - .print_ip_state = NULL, 292 290 }; 293 291 294 292 const struct amdgpu_ip_block_version pp_smu_ip_block =