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arm64: dts: qcom: sc8180x: Add QUPs

This patch adds qup instances and i2c, spi, serial ports

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230530162454.51708-10-vkoul@kernel.org

authored by

Vinod Koul and committed by
Bjorn Andersson 0018761d d1d3ca03

+859
+859
arch/arm64/boot/dts/qcom/sc8180x.dtsi
··· 780 780 "sleep_clk"; 781 781 }; 782 782 783 + qupv3_id_0: geniqup@8c0000 { 784 + compatible = "qcom,geni-se-qup"; 785 + reg = <0 0x008c0000 0 0x6000>; 786 + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 787 + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 788 + clock-names = "m-ahb", "s-ahb"; 789 + #address-cells = <2>; 790 + #size-cells = <2>; 791 + ranges; 792 + iommus = <&apps_smmu 0x4c3 0>; 793 + status = "disabled"; 794 + 795 + i2c0: i2c@880000 { 796 + compatible = "qcom,geni-i2c"; 797 + reg = <0 0x00880000 0 0x4000>; 798 + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 799 + clock-names = "se"; 800 + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 801 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 802 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 803 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 804 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 805 + #address-cells = <1>; 806 + #size-cells = <0>; 807 + status = "disabled"; 808 + }; 809 + 810 + spi0: spi@880000 { 811 + compatible = "qcom,geni-spi"; 812 + reg = <0 0x00880000 0 0x4000>; 813 + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 814 + clock-names = "se"; 815 + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 816 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 817 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 818 + interconnect-names = "qup-core", "qup-config"; 819 + #address-cells = <1>; 820 + #size-cells = <0>; 821 + status = "disabled"; 822 + }; 823 + 824 + uart0: serial@880000 { 825 + compatible = "qcom,geni-uart"; 826 + reg = <0 0x00880000 0 0x4000>; 827 + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 828 + clock-names = "se"; 829 + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 830 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 831 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 832 + interconnect-names = "qup-core", "qup-config"; 833 + status = "disabled"; 834 + }; 835 + 836 + i2c1: i2c@884000 { 837 + compatible = "qcom,geni-i2c"; 838 + reg = <0 0x00884000 0 0x4000>; 839 + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 840 + clock-names = "se"; 841 + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 842 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 843 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 844 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 845 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 846 + #address-cells = <1>; 847 + #size-cells = <0>; 848 + status = "disabled"; 849 + }; 850 + 851 + spi1: spi@884000 { 852 + compatible = "qcom,geni-spi"; 853 + reg = <0 0x00884000 0 0x4000>; 854 + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 855 + clock-names = "se"; 856 + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 857 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 858 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 859 + interconnect-names = "qup-core", "qup-config"; 860 + #address-cells = <1>; 861 + #size-cells = <0>; 862 + status = "disabled"; 863 + }; 864 + 865 + uart1: serial@884000 { 866 + compatible = "qcom,geni-uart"; 867 + reg = <0 0x00884000 0 0x4000>; 868 + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 869 + clock-names = "se"; 870 + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 871 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 872 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 873 + interconnect-names = "qup-core", "qup-config"; 874 + status = "disabled"; 875 + }; 876 + 877 + i2c2: i2c@888000 { 878 + compatible = "qcom,geni-i2c"; 879 + reg = <0 0x00888000 0 0x4000>; 880 + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 881 + clock-names = "se"; 882 + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 883 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 884 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 885 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 886 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 887 + #address-cells = <1>; 888 + #size-cells = <0>; 889 + status = "disabled"; 890 + }; 891 + 892 + spi2: spi@888000 { 893 + compatible = "qcom,geni-spi"; 894 + reg = <0 0x00888000 0 0x4000>; 895 + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 896 + clock-names = "se"; 897 + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 898 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 899 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 900 + interconnect-names = "qup-core", "qup-config"; 901 + #address-cells = <1>; 902 + #size-cells = <0>; 903 + status = "disabled"; 904 + }; 905 + 906 + uart2: serial@888000 { 907 + compatible = "qcom,geni-uart"; 908 + reg = <0 0x00888000 0 0x4000>; 909 + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 910 + clock-names = "se"; 911 + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 912 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 913 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 914 + interconnect-names = "qup-core", "qup-config"; 915 + status = "disabled"; 916 + }; 917 + 918 + i2c3: i2c@88c000 { 919 + compatible = "qcom,geni-i2c"; 920 + reg = <0 0x0088c000 0 0x4000>; 921 + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 922 + clock-names = "se"; 923 + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 924 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 925 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 926 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 927 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 + #address-cells = <1>; 929 + #size-cells = <0>; 930 + status = "disabled"; 931 + }; 932 + 933 + spi3: spi@88c000 { 934 + compatible = "qcom,geni-spi"; 935 + reg = <0 0x0088c000 0 0x4000>; 936 + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 937 + clock-names = "se"; 938 + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 939 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 940 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 941 + interconnect-names = "qup-core", "qup-config"; 942 + #address-cells = <1>; 943 + #size-cells = <0>; 944 + status = "disabled"; 945 + }; 946 + 947 + uart3: serial@88c000 { 948 + compatible = "qcom,geni-uart"; 949 + reg = <0 0x0088c000 0 0x4000>; 950 + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 951 + clock-names = "se"; 952 + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 953 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 954 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 955 + interconnect-names = "qup-core", "qup-config"; 956 + status = "disabled"; 957 + }; 958 + 959 + i2c4: i2c@890000 { 960 + compatible = "qcom,geni-i2c"; 961 + reg = <0 0x00890000 0 0x4000>; 962 + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 963 + clock-names = "se"; 964 + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 965 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 966 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 967 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 968 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 969 + #address-cells = <1>; 970 + #size-cells = <0>; 971 + status = "disabled"; 972 + }; 973 + 974 + spi4: spi@890000 { 975 + compatible = "qcom,geni-spi"; 976 + reg = <0 0x00890000 0 0x4000>; 977 + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 978 + clock-names = "se"; 979 + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 980 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 981 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 982 + interconnect-names = "qup-core", "qup-config"; 983 + #address-cells = <1>; 984 + #size-cells = <0>; 985 + status = "disabled"; 986 + }; 987 + 988 + uart4: serial@890000 { 989 + compatible = "qcom,geni-uart"; 990 + reg = <0 0x00890000 0 0x4000>; 991 + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 992 + clock-names = "se"; 993 + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 994 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 995 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 996 + interconnect-names = "qup-core", "qup-config"; 997 + status = "disabled"; 998 + }; 999 + 1000 + i2c5: i2c@894000 { 1001 + compatible = "qcom,geni-i2c"; 1002 + reg = <0 0x00894000 0 0x4000>; 1003 + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1004 + clock-names = "se"; 1005 + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1006 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1007 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1008 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1009 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1010 + #address-cells = <1>; 1011 + #size-cells = <0>; 1012 + status = "disabled"; 1013 + }; 1014 + 1015 + spi5: spi@894000 { 1016 + compatible = "qcom,geni-spi"; 1017 + reg = <0 0x00894000 0 0x4000>; 1018 + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1019 + clock-names = "se"; 1020 + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1021 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1022 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1023 + interconnect-names = "qup-core", "qup-config"; 1024 + #address-cells = <1>; 1025 + #size-cells = <0>; 1026 + status = "disabled"; 1027 + }; 1028 + 1029 + uart5: serial@894000 { 1030 + compatible = "qcom,geni-uart"; 1031 + reg = <0 0x00894000 0 0x4000>; 1032 + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1033 + clock-names = "se"; 1034 + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1035 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1036 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1037 + interconnect-names = "qup-core", "qup-config"; 1038 + status = "disabled"; 1039 + }; 1040 + 1041 + i2c6: i2c@898000 { 1042 + compatible = "qcom,geni-i2c"; 1043 + reg = <0 0x00898000 0 0x4000>; 1044 + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1045 + clock-names = "se"; 1046 + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1047 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1048 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1049 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1050 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1051 + #address-cells = <1>; 1052 + #size-cells = <0>; 1053 + status = "disabled"; 1054 + }; 1055 + 1056 + spi6: spi@898000 { 1057 + compatible = "qcom,geni-spi"; 1058 + reg = <0 0x00898000 0 0x4000>; 1059 + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1060 + clock-names = "se"; 1061 + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1062 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1063 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1064 + interconnect-names = "qup-core", "qup-config"; 1065 + #address-cells = <1>; 1066 + #size-cells = <0>; 1067 + status = "disabled"; 1068 + }; 1069 + 1070 + uart6: serial@898000 { 1071 + compatible = "qcom,geni-uart"; 1072 + reg = <0 0x00898000 0 0x4000>; 1073 + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1074 + clock-names = "se"; 1075 + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1076 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1077 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1078 + interconnect-names = "qup-core", "qup-config"; 1079 + status = "disabled"; 1080 + }; 1081 + 1082 + i2c7: i2c@89c000 { 1083 + compatible = "qcom,geni-i2c"; 1084 + reg = <0 0x0089c000 0 0x4000>; 1085 + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1086 + clock-names = "se"; 1087 + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1088 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1089 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1090 + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1091 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1092 + #address-cells = <1>; 1093 + #size-cells = <0>; 1094 + status = "disabled"; 1095 + }; 1096 + 1097 + spi7: spi@89c000 { 1098 + compatible = "qcom,geni-spi"; 1099 + reg = <0 0x0089c000 0 0x4000>; 1100 + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1101 + clock-names = "se"; 1102 + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1103 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1104 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1105 + interconnect-names = "qup-core", "qup-config"; 1106 + #address-cells = <1>; 1107 + #size-cells = <0>; 1108 + status = "disabled"; 1109 + }; 1110 + 1111 + uart7: serial@89c000 { 1112 + compatible = "qcom,geni-uart"; 1113 + reg = <0 0x0089c000 0 0x4000>; 1114 + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1115 + clock-names = "se"; 1116 + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1117 + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1118 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1119 + interconnect-names = "qup-core", "qup-config"; 1120 + status = "disabled"; 1121 + }; 1122 + }; 1123 + 1124 + qupv3_id_1: geniqup@ac0000 { 1125 + compatible = "qcom,geni-se-qup"; 1126 + reg = <0x0 0x00ac0000 0x0 0x6000>; 1127 + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1128 + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1129 + clock-names = "m-ahb", "s-ahb"; 1130 + #address-cells = <2>; 1131 + #size-cells = <2>; 1132 + ranges; 1133 + iommus = <&apps_smmu 0x603 0>; 1134 + status = "disabled"; 1135 + 1136 + i2c8: i2c@a80000 { 1137 + compatible = "qcom,geni-i2c"; 1138 + reg = <0 0x00a80000 0 0x4000>; 1139 + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1140 + clock-names = "se"; 1141 + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1142 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1143 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1144 + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1145 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1146 + #address-cells = <1>; 1147 + #size-cells = <0>; 1148 + status = "disabled"; 1149 + }; 1150 + 1151 + spi8: spi@a80000 { 1152 + compatible = "qcom,geni-spi"; 1153 + reg = <0 0x00a80000 0 0x4000>; 1154 + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1155 + clock-names = "se"; 1156 + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1157 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1158 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1159 + interconnect-names = "qup-core", "qup-config"; 1160 + #address-cells = <1>; 1161 + #size-cells = <0>; 1162 + status = "disabled"; 1163 + }; 1164 + 1165 + uart8: serial@a80000 { 1166 + compatible = "qcom,geni-uart"; 1167 + reg = <0 0x00a80000 0 0x4000>; 1168 + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1169 + clock-names = "se"; 1170 + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1171 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1172 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1173 + interconnect-names = "qup-core", "qup-config"; 1174 + status = "disabled"; 1175 + }; 1176 + 1177 + i2c9: i2c@a84000 { 1178 + compatible = "qcom,geni-i2c"; 1179 + reg = <0 0x00a84000 0 0x4000>; 1180 + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1181 + clock-names = "se"; 1182 + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1183 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1184 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1185 + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1186 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1187 + #address-cells = <1>; 1188 + #size-cells = <0>; 1189 + status = "disabled"; 1190 + }; 1191 + 1192 + spi9: spi@a84000 { 1193 + compatible = "qcom,geni-spi"; 1194 + reg = <0 0x00a84000 0 0x4000>; 1195 + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1196 + clock-names = "se"; 1197 + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1198 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1199 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1200 + interconnect-names = "qup-core", "qup-config"; 1201 + #address-cells = <1>; 1202 + #size-cells = <0>; 1203 + status = "disabled"; 1204 + }; 1205 + 1206 + uart9: serial@a84000 { 1207 + compatible = "qcom,geni-debug-uart"; 1208 + reg = <0 0x00a84000 0 0x4000>; 1209 + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1210 + clock-names = "se"; 1211 + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1212 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1213 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1214 + interconnect-names = "qup-core", "qup-config"; 1215 + status = "disabled"; 1216 + }; 1217 + 1218 + i2c10: i2c@a88000 { 1219 + compatible = "qcom,geni-i2c"; 1220 + reg = <0 0x00a88000 0 0x4000>; 1221 + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1222 + clock-names = "se"; 1223 + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1224 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1225 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1226 + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1227 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1228 + #address-cells = <1>; 1229 + #size-cells = <0>; 1230 + status = "disabled"; 1231 + }; 1232 + 1233 + spi10: spi@a88000 { 1234 + compatible = "qcom,geni-spi"; 1235 + reg = <0 0x00a88000 0 0x4000>; 1236 + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1237 + clock-names = "se"; 1238 + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1239 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1240 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1241 + interconnect-names = "qup-core", "qup-config"; 1242 + #address-cells = <1>; 1243 + #size-cells = <0>; 1244 + status = "disabled"; 1245 + }; 1246 + 1247 + uart10: serial@a88000 { 1248 + compatible = "qcom,geni-uart"; 1249 + reg = <0 0x00a88000 0 0x4000>; 1250 + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1251 + clock-names = "se"; 1252 + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1253 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1254 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1255 + interconnect-names = "qup-core", "qup-config"; 1256 + status = "disabled"; 1257 + }; 1258 + 1259 + i2c11: i2c@a8c000 { 1260 + compatible = "qcom,geni-i2c"; 1261 + reg = <0 0x00a8c000 0 0x4000>; 1262 + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1263 + clock-names = "se"; 1264 + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1265 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1266 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1267 + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1268 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1269 + #address-cells = <1>; 1270 + #size-cells = <0>; 1271 + status = "disabled"; 1272 + }; 1273 + 1274 + spi11: spi@a8c000 { 1275 + compatible = "qcom,geni-spi"; 1276 + reg = <0 0x00a8c000 0 0x4000>; 1277 + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1278 + clock-names = "se"; 1279 + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1280 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1281 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1282 + interconnect-names = "qup-core", "qup-config"; 1283 + #address-cells = <1>; 1284 + #size-cells = <0>; 1285 + status = "disabled"; 1286 + }; 1287 + 1288 + uart11: serial@a8c000 { 1289 + compatible = "qcom,geni-uart"; 1290 + reg = <0 0x00a8c000 0 0x4000>; 1291 + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1292 + clock-names = "se"; 1293 + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1294 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1295 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1296 + interconnect-names = "qup-core", "qup-config"; 1297 + status = "disabled"; 1298 + }; 1299 + 1300 + i2c12: i2c@a90000 { 1301 + compatible = "qcom,geni-i2c"; 1302 + reg = <0 0x00a90000 0 0x4000>; 1303 + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1304 + clock-names = "se"; 1305 + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1306 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1307 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1308 + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1309 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1310 + #address-cells = <1>; 1311 + #size-cells = <0>; 1312 + status = "disabled"; 1313 + }; 1314 + 1315 + spi12: spi@a90000 { 1316 + compatible = "qcom,geni-spi"; 1317 + reg = <0 0x00a90000 0 0x4000>; 1318 + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1319 + clock-names = "se"; 1320 + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1321 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1322 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1323 + interconnect-names = "qup-core", "qup-config"; 1324 + #address-cells = <1>; 1325 + #size-cells = <0>; 1326 + status = "disabled"; 1327 + }; 1328 + 1329 + uart12: serial@a90000 { 1330 + compatible = "qcom,geni-uart"; 1331 + reg = <0 0x00a90000 0 0x4000>; 1332 + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1333 + clock-names = "se"; 1334 + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1335 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1336 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1337 + interconnect-names = "qup-core", "qup-config"; 1338 + status = "disabled"; 1339 + }; 1340 + 1341 + i2c16: i2c@a94000 { 1342 + compatible = "qcom,geni-i2c"; 1343 + reg = <0 0x00a94000 0 0x4000>; 1344 + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1345 + clock-names = "se"; 1346 + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1347 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1348 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1349 + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1350 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 + #address-cells = <1>; 1352 + #size-cells = <0>; 1353 + status = "disabled"; 1354 + }; 1355 + 1356 + spi16: spi@a94000 { 1357 + compatible = "qcom,geni-spi"; 1358 + reg = <0 0x00a94000 0 0x4000>; 1359 + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1360 + clock-names = "se"; 1361 + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1362 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1363 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1364 + interconnect-names = "qup-core", "qup-config"; 1365 + #address-cells = <1>; 1366 + #size-cells = <0>; 1367 + status = "disabled"; 1368 + }; 1369 + 1370 + uart16: serial@a94000 { 1371 + compatible = "qcom,geni-uart"; 1372 + reg = <0 0x00a94000 0 0x4000>; 1373 + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1374 + clock-names = "se"; 1375 + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1376 + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1377 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1378 + interconnect-names = "qup-core", "qup-config"; 1379 + status = "disabled"; 1380 + }; 1381 + }; 1382 + 1383 + qupv3_id_2: geniqup@cc0000 { 1384 + compatible = "qcom,geni-se-qup"; 1385 + reg = <0x0 0x00cc0000 0x0 0x6000>; 1386 + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1387 + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1388 + clock-names = "m-ahb", "s-ahb"; 1389 + #address-cells = <2>; 1390 + #size-cells = <2>; 1391 + ranges; 1392 + iommus = <&apps_smmu 0x7a3 0>; 1393 + status = "disabled"; 1394 + 1395 + i2c17: i2c@c80000 { 1396 + compatible = "qcom,geni-i2c"; 1397 + reg = <0 0x00c80000 0 0x4000>; 1398 + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1399 + clock-names = "se"; 1400 + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1401 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1402 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1403 + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1404 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1405 + #address-cells = <1>; 1406 + #size-cells = <0>; 1407 + status = "disabled"; 1408 + }; 1409 + 1410 + spi17: spi@c80000 { 1411 + compatible = "qcom,geni-spi"; 1412 + reg = <0 0x00c80000 0 0x4000>; 1413 + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1414 + clock-names = "se"; 1415 + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1416 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1417 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1418 + interconnect-names = "qup-core", "qup-config"; 1419 + #address-cells = <1>; 1420 + #size-cells = <0>; 1421 + status = "disabled"; 1422 + }; 1423 + 1424 + uart17: serial@c80000 { 1425 + compatible = "qcom,geni-uart"; 1426 + reg = <0 0x00c80000 0 0x4000>; 1427 + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1428 + clock-names = "se"; 1429 + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1430 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1431 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1432 + interconnect-names = "qup-core", "qup-config"; 1433 + status = "disabled"; 1434 + }; 1435 + 1436 + i2c18: i2c@c84000 { 1437 + compatible = "qcom,geni-i2c"; 1438 + reg = <0 0x00c84000 0 0x4000>; 1439 + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1440 + clock-names = "se"; 1441 + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1442 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1443 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1444 + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1445 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1446 + #address-cells = <1>; 1447 + #size-cells = <0>; 1448 + status = "disabled"; 1449 + }; 1450 + 1451 + spi18: spi@c84000 { 1452 + compatible = "qcom,geni-spi"; 1453 + reg = <0 0x00c84000 0 0x4000>; 1454 + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1455 + clock-names = "se"; 1456 + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1457 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1458 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1459 + interconnect-names = "qup-core", "qup-config"; 1460 + #address-cells = <1>; 1461 + #size-cells = <0>; 1462 + status = "disabled"; 1463 + }; 1464 + 1465 + uart18: serial@c84000 { 1466 + compatible = "qcom,geni-uart"; 1467 + reg = <0 0x00c84000 0 0x4000>; 1468 + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1469 + clock-names = "se"; 1470 + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1471 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1472 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1473 + interconnect-names = "qup-core", "qup-config"; 1474 + status = "disabled"; 1475 + }; 1476 + 1477 + i2c19: i2c@c88000 { 1478 + compatible = "qcom,geni-i2c"; 1479 + reg = <0 0x00c88000 0 0x4000>; 1480 + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1481 + clock-names = "se"; 1482 + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1483 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1484 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1485 + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1486 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1487 + #address-cells = <1>; 1488 + #size-cells = <0>; 1489 + status = "disabled"; 1490 + }; 1491 + 1492 + spi19: spi@c88000 { 1493 + compatible = "qcom,geni-spi"; 1494 + reg = <0 0x00c88000 0 0x4000>; 1495 + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1496 + clock-names = "se"; 1497 + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1498 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1499 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1500 + interconnect-names = "qup-core", "qup-config"; 1501 + #address-cells = <1>; 1502 + #size-cells = <0>; 1503 + status = "disabled"; 1504 + }; 1505 + 1506 + uart19: serial@c88000 { 1507 + compatible = "qcom,geni-uart"; 1508 + reg = <0 0x00c88000 0 0x4000>; 1509 + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1510 + clock-names = "se"; 1511 + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1512 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1513 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1514 + interconnect-names = "qup-core", "qup-config"; 1515 + status = "disabled"; 1516 + }; 1517 + 1518 + i2c13: i2c@c8c000 { 1519 + compatible = "qcom,geni-i2c"; 1520 + reg = <0 0x00c8c000 0 0x4000>; 1521 + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1522 + clock-names = "se"; 1523 + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1524 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1525 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1526 + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1527 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1528 + #address-cells = <1>; 1529 + #size-cells = <0>; 1530 + status = "disabled"; 1531 + }; 1532 + 1533 + spi13: spi@c8c000 { 1534 + compatible = "qcom,geni-spi"; 1535 + reg = <0 0x00c8c000 0 0x4000>; 1536 + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1537 + clock-names = "se"; 1538 + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1539 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1540 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1541 + interconnect-names = "qup-core", "qup-config"; 1542 + #address-cells = <1>; 1543 + #size-cells = <0>; 1544 + status = "disabled"; 1545 + }; 1546 + 1547 + uart13: serial@c8c000 { 1548 + compatible = "qcom,geni-uart"; 1549 + reg = <0 0x00c8c000 0 0x4000>; 1550 + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1551 + clock-names = "se"; 1552 + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1553 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1554 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1555 + interconnect-names = "qup-core", "qup-config"; 1556 + status = "disabled"; 1557 + }; 1558 + 1559 + i2c14: i2c@c90000 { 1560 + compatible = "qcom,geni-i2c"; 1561 + reg = <0 0x00c90000 0 0x4000>; 1562 + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1563 + clock-names = "se"; 1564 + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1565 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1566 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1567 + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1568 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 + #address-cells = <1>; 1570 + #size-cells = <0>; 1571 + status = "disabled"; 1572 + }; 1573 + 1574 + spi14: spi@c90000 { 1575 + compatible = "qcom,geni-spi"; 1576 + reg = <0 0x00c90000 0 0x4000>; 1577 + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1578 + clock-names = "se"; 1579 + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1580 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1581 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1582 + interconnect-names = "qup-core", "qup-config"; 1583 + #address-cells = <1>; 1584 + #size-cells = <0>; 1585 + status = "disabled"; 1586 + }; 1587 + 1588 + uart14: serial@c90000 { 1589 + compatible = "qcom,geni-uart"; 1590 + reg = <0 0x00c90000 0 0x4000>; 1591 + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1592 + clock-names = "se"; 1593 + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1594 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1595 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1596 + interconnect-names = "qup-core", "qup-config"; 1597 + status = "disabled"; 1598 + }; 1599 + 1600 + i2c15: i2c@c94000 { 1601 + compatible = "qcom,geni-i2c"; 1602 + reg = <0 0x00c94000 0 0x4000>; 1603 + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1604 + clock-names = "se"; 1605 + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1606 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1607 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1608 + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1609 + interconnect-names = "qup-core", "qup-config", "qup-memory"; 1610 + #address-cells = <1>; 1611 + #size-cells = <0>; 1612 + status = "disabled"; 1613 + }; 1614 + 1615 + spi15: spi@c94000 { 1616 + compatible = "qcom,geni-spi"; 1617 + reg = <0 0x00c94000 0 0x4000>; 1618 + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1619 + clock-names = "se"; 1620 + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1621 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1622 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1623 + interconnect-names = "qup-core", "qup-config"; 1624 + #address-cells = <1>; 1625 + #size-cells = <0>; 1626 + status = "disabled"; 1627 + }; 1628 + 1629 + uart15: serial@c94000 { 1630 + compatible = "qcom,geni-uart"; 1631 + reg = <0 0x00c94000 0 0x4000>; 1632 + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1633 + clock-names = "se"; 1634 + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1635 + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1636 + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1637 + interconnect-names = "qup-core", "qup-config"; 1638 + status = "disabled"; 1639 + }; 1640 + }; 1641 + 783 1642 config_noc: interconnect@1500000 { 784 1643 compatible = "qcom,sc8180x-config-noc"; 785 1644 reg = <0 0x01500000 0 0x7400>;