tjh.dev / kernel
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drm/i915/display: implement wa_18038517565

Disable FBC compressor clock gating before enabling FBC and
clear it after disabling FBC.

v2: update the DG2 registers for this wa

v3: use local variable and single line reg definition (Jani)

Bspec: 74212, 72197, 69741, 65555
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250330172616.718188-1-vinod.govindapillai@intel.com

Vinod Govindapillai 010363c4 9900e35a

+28
+22
drivers/gpu/drm/i915/display/intel_fbc.c
··· 520 520 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 521 521 } 522 522 523 + static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc, 524 + bool disable) 525 + { 526 + struct intel_display *display = fbc->display; 527 + 528 + if (display->platform.dg2) 529 + intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS, 530 + disable ? DG2_DPFC_GATING_DIS : 0); 531 + else if (DISPLAY_VER(display) >= 14) 532 + intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id), 533 + MTL_DPFC_GATING_DIS, 534 + disable ? MTL_DPFC_GATING_DIS : 0); 535 + } 536 + 523 537 static void ilk_fbc_deactivate(struct intel_fbc *fbc) 524 538 { 525 539 struct intel_display *display = fbc->display; ··· 547 533 if (dpfc_ctl & DPFC_CTL_EN) { 548 534 dpfc_ctl &= ~DPFC_CTL_EN; 549 535 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 536 + 537 + /* wa_18038517565 Enable DPFC clock gating after FBC disable */ 538 + if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 539 + fbc_compressor_clkgate_disable_wa(fbc, false); 550 540 } 551 541 } 552 542 ··· 940 922 if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 941 923 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 942 924 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); 925 + 926 + /* wa_18038517565 Disable DPFC clock gating before FBC enable */ 927 + if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 928 + fbc_compressor_clkgate_disable_wa(fbc, true); 943 929 } 944 930 945 931 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
+6
drivers/gpu/drm/i915/i915_reg.h
··· 1077 1077 1078 1078 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1079 1079 #define BXT_GMBUS_GATING_DIS (1 << 14) 1080 + #define DG2_DPFC_GATING_DIS REG_BIT(31) 1080 1081 1081 1082 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1082 1083 #define DPCE_GATING_DIS REG_BIT(17) ··· 4242 4241 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 4243 4242 #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) 4244 4243 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) 4244 + 4245 + #define _MTL_PIPE_CLKGATE_DIS2_A 0x60114 4246 + #define _MTL_PIPE_CLKGATE_DIS2_B 0x61114 4247 + #define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B) 4248 + #define MTL_DPFC_GATING_DIS REG_BIT(6) 4245 4249 4246 4250 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 4247 4251 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)