Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a8xx: Add support for Adreno X2-85 GPU
Adreno X2-85 GPU is found in the next generation of Qualcomm's compute
series chipset called Snapdragon X2 Elite (a.k.a Glymur). It is based
on the new A8x slice architecture and features up to 4 slices. Due to
the wider 12 channel DDR support, there is higher DDR bandwidth available
than previous generation to improve performance.
Add a new entry in the catalog along with the necessary register
configurations to enable support for it.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689026/
Message-ID: <20251118-kaana-gpu-support-v4-18-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
01ff3bf2
60a4e18e
+140
+132
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+132
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
···
1650
1650
};
1651
1651
DECLARE_ADRENO_GPULIST(a7xx);
1652
1652
1653
+
static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
1654
+
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1655
+
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1656
+
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1657
+
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1658
+
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1659
+
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1660
+
{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1661
+
{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1662
+
{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1663
+
{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1664
+
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
1665
+
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1666
+
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1667
+
{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1668
+
{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1669
+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1670
+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1671
+
{ REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1672
+
{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1673
+
{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1674
+
{ REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
1675
+
{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1676
+
{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1677
+
/* Disable CS dead batch merge */
1678
+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) },
1679
+
{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1680
+
{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1681
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
1682
+
/* BIT(26): Disable final clamp for bicubic filtering */
1683
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
1684
+
{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1685
+
{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1686
+
{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1687
+
{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1688
+
{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1689
+
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1690
+
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1691
+
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1692
+
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1693
+
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1694
+
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1695
+
{ },
1696
+
};
1697
+
1698
+
static const u32 x285_protect_regs[] = {
1699
+
A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1700
+
A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1701
+
A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1702
+
A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1703
+
A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1704
+
A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1705
+
A6XX_PROTECT_RDONLY(0x00759, 0x0026),
1706
+
A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1707
+
A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1708
+
A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1709
+
A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
1710
+
A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1711
+
A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1712
+
A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1713
+
A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1714
+
A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1715
+
A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1716
+
A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1717
+
A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1718
+
A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1719
+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1720
+
A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1721
+
A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1722
+
A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1723
+
A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1724
+
A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1725
+
A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1726
+
A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1727
+
A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1728
+
A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1729
+
A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1730
+
A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1731
+
A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
1732
+
A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1733
+
A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1734
+
A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1735
+
A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1736
+
A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1737
+
A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1738
+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1739
+
A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1740
+
A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1741
+
A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1742
+
A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1743
+
A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1744
+
A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1745
+
A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1746
+
A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1747
+
A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1748
+
A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1749
+
A6XX_PROTECT_NORDWR(0x27882, 0x000a),
1750
+
A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1751
+
};
1752
+
1753
+
DECLARE_ADRENO_PROTECT(x285_protect, 64);
1754
+
1653
1755
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
1654
1756
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1655
1757
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
···
1884
1782
1885
1783
static const struct adreno_info a8xx_gpus[] = {
1886
1784
{
1785
+
.chip_ids = ADRENO_CHIP_IDS(0x44070001),
1786
+
.family = ADRENO_8XX_GEN2,
1787
+
.fw = {
1788
+
[ADRENO_FW_SQE] = "gen80100_sqe.fw",
1789
+
[ADRENO_FW_GMU] = "gen80100_gmu.bin",
1790
+
},
1791
+
.gmem = 21 * SZ_1M,
1792
+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1793
+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1794
+
ADRENO_QUIRK_HAS_HW_APRIV,
1795
+
.funcs = &a8xx_gpu_funcs,
1796
+
.a6xx = &(const struct a6xx_info) {
1797
+
.protect = &x285_protect,
1798
+
.nonctxt_reglist = x285_nonctxt_regs,
1799
+
.gbif_cx = a840_gbif,
1800
+
.max_slices = 4,
1801
+
.gmu_chipid = 0x8010100,
1802
+
.bcms = (const struct a6xx_bcm[]) {
1803
+
{ .name = "SH0", .buswidth = 16 },
1804
+
{ .name = "MC0", .buswidth = 4 },
1805
+
{
1806
+
.name = "ACV",
1807
+
.fixed = true,
1808
+
.perfmode = BIT(2),
1809
+
.perfmode_bw = 16500000,
1810
+
},
1811
+
{ /* sentinel */ },
1812
+
},
1813
+
},
1814
+
}, {
1887
1815
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
1888
1816
.family = ADRENO_8XX_GEN2,
1889
1817
.fw = {
+3
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+3
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
···
190
190
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
191
191
u32 val;
192
192
193
+
if (adreno_is_x285(adreno_gpu) && state)
194
+
gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702);
195
+
193
196
gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
194
197
state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
195
198
gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
+5
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+5
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
580
580
return gpu->info->family >= ADRENO_8XX_GEN1;
581
581
}
582
582
583
+
static inline int adreno_is_x285(struct adreno_gpu *gpu)
584
+
{
585
+
return gpu->info->chip_ids[0] == 0x44070001;
586
+
}
587
+
583
588
static inline int adreno_is_a840(struct adreno_gpu *gpu)
584
589
{
585
590
return gpu->info->chip_ids[0] == 0x44050a01;