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spi: rzv2h-rspi: Fix invalid SPR=0/BRDV=0 clock configuration

The combination of SPR=0 and BRDV=0 results in the minimum division
ratio of 2, producing the maximum possible bit rate for a given clock
source. This combination is not supported in two cases:

- On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is fixed at
200MHz, which would yield 100Mbps. The next hardware manual update
will explicitly state that since the maximum frequency of the
RSPICKn clock signal is 50MHz, settings with N=0 and n=0 resulting
in 100Mbps are prohibited.

- On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as the clock
source, SPR=0 and BRDV=0 is explicitly listed as unsupported in
the hardware manual (Table 36.7).

Skip the SPR=0/BRDV=0 combination in rzv2h_rspi_find_rate_fixed() to
prevent the driver from selecting an invalid clock configuration on the
affected SoCs.

Additionally, remove the now redundant RSPI_SPBR_SPR_PCLK_MIN define
which was previously set to 1 to work around the PCLK restriction, but
was overly broad as it incorrectly blocked valid combinations such as
SPR=0/BRDV=1 (31.25Mbps on PCLK=125MHz).

Fixes: 8b61c8919dff ("spi: Add driver for the RZ/V2H(P) RSPI IP")
Fixes: 1ce3e8adc7d0 ("spi: rzv2h-rspi: add support for using PCLK for transfer clock")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20260410080517.2405700-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Lad Prabhakar and committed by
Mark Brown 0335767d 4e292cbf

+12 -6
+12 -6
drivers/spi/spi-rzv2h-rspi.c
··· 50 50 51 51 /* Register SPBR */ 52 52 #define RSPI_SPBR_SPR_MIN 0 53 - #define RSPI_SPBR_SPR_PCLK_MIN 1 54 53 #define RSPI_SPBR_SPR_MAX 255 55 54 56 55 /* Register SPCMD */ ··· 534 535 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) { 535 536 spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1))); 536 537 spr--; 538 + /* 539 + * Skip SPR=0 and BRDV=0 as it is not a valid combination: 540 + * - On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is 541 + * fixed at 200MHz and SPR=0 and BRDV=0 results in the maximum 542 + * bit rate of 100Mbps which is prohibited. 543 + * - On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as 544 + * the clock source, SPR=0 and BRDV=0 is explicitly listed 545 + * as unsupported in the hardware manual (Table 36.7). 546 + */ 547 + if (!spr && !brdv) 548 + continue; 537 549 if (spr >= spr_min && spr <= spr_max) 538 550 goto clock_found; 539 551 } ··· 578 568 rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN, 579 569 RSPI_SPBR_SPR_MAX, &best_clock); 580 570 581 - /* 582 - * T2H and N2H can also use PCLK as a source, which is 125MHz, but not 583 - * when both SPR and BRDV are 0. 584 - */ 585 571 if (best_clock.error && rspi->info->find_pclk_rate) 586 - rspi->info->find_pclk_rate(rspi->pclk, hz, RSPI_SPBR_SPR_PCLK_MIN, 572 + rspi->info->find_pclk_rate(rspi->pclk, hz, RSPI_SPBR_SPR_MIN, 587 573 RSPI_SPBR_SPR_MAX, &best_clock); 588 574 589 575 if (!best_clock.clk_rate)