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dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant

Add a new compatible and related bindigns for the fpga-based
"ad3552r" AXI IP core, a variant of the generic AXI DAC IP.

The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the
generic AXI "DAC" IP, intended to control ad3552r and similar chips,
mainly to reach high speed transfer rates using a QSPI DDR
(dobule-data-rate) interface.

The ad3552r device is defined as a child of the AXI DAC, that in
this case is acting as an SPI controller.

Note, #io-backend is present because it is possible (in theory anyway)
to use a separate controller for the control path than that used
for the datapath.

Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-2-f6960b4f9719@kernel-space.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Angelo Dureghello and committed by
Jonathan Cameron 043e4e51 76830926

+66 -3
+66 -3
Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
··· 19 19 memory via DMA into the DAC. 20 20 21 21 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip 22 + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html 22 23 23 24 properties: 24 25 compatible: 25 26 enum: 26 27 - adi,axi-dac-9.1.b 28 + - adi,axi-ad3552r 27 29 28 30 reg: 29 31 maxItems: 1 ··· 38 36 - const: tx 39 37 40 38 clocks: 41 - maxItems: 1 39 + minItems: 1 40 + maxItems: 2 41 + 42 + clock-names: 43 + items: 44 + - const: s_axi_aclk 45 + - const: dac_clk 46 + minItems: 1 42 47 43 48 '#io-backend-cells': 44 49 const: 0 ··· 56 47 - reg 57 48 - clocks 58 49 59 - additionalProperties: false 50 + allOf: 51 + - if: 52 + properties: 53 + compatible: 54 + contains: 55 + const: adi,axi-ad3552r 56 + then: 57 + $ref: /schemas/spi/spi-controller.yaml# 58 + properties: 59 + clocks: 60 + minItems: 2 61 + clock-names: 62 + minItems: 2 63 + required: 64 + - clock-names 65 + else: 66 + properties: 67 + clocks: 68 + maxItems: 1 69 + clock-names: 70 + maxItems: 1 71 + 72 + unevaluatedProperties: false 60 73 61 74 examples: 62 75 - | ··· 88 57 dmas = <&tx_dma 0>; 89 58 dma-names = "tx"; 90 59 #io-backend-cells = <0>; 91 - clocks = <&axi_clk>; 60 + clocks = <&clkc 15>; 61 + clock-names = "s_axi_aclk"; 62 + }; 63 + 64 + - | 65 + #include <dt-bindings/gpio/gpio.h> 66 + axi_dac: spi@44a70000 { 67 + compatible = "adi,axi-ad3552r"; 68 + reg = <0x44a70000 0x1000>; 69 + dmas = <&dac_tx_dma 0>; 70 + dma-names = "tx"; 71 + #io-backend-cells = <0>; 72 + clocks = <&clkc 15>, <&ref_clk>; 73 + clock-names = "s_axi_aclk", "dac_clk"; 74 + 75 + #address-cells = <1>; 76 + #size-cells = <0>; 77 + 78 + dac@0 { 79 + compatible = "adi,ad3552r"; 80 + reg = <0>; 81 + reset-gpios = <&gpio0 92 GPIO_ACTIVE_HIGH>; 82 + io-backends = <&axi_dac>; 83 + spi-max-frequency = <20000000>; 84 + 85 + #address-cells = <1>; 86 + #size-cells = <0>; 87 + 88 + channel@0 { 89 + reg = <0>; 90 + adi,output-range-microvolt = <(-10000000) (10000000)>; 91 + }; 92 + }; 92 93 }; 93 94 ...