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clk: renesas: r9a09g057: Add clock and reset entries for GIC

Add clock and reset entries for GIC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250102181839.352599-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven
05031de3 7e3557b4

+4
+4
drivers/clk/renesas/r9a09g057-cpg.c
··· 117 117 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 118 118 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 119 119 BUS_MSTOP_NONE), 120 + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 121 + BUS_MSTOP(3, BIT(5))), 120 122 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 121 123 BUS_MSTOP(5, BIT(10))), 122 124 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, ··· 224 222 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 225 223 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 226 224 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 225 + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 226 + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 227 227 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 228 228 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 229 229 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */