Merge tag 'renesas-pinctrl-for-v6.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

+172

Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller 8 + 9 + maintainers: 10 + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 11 + 12 + description: 13 + The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller. 14 + Pin multiplexing and GPIO configuration are performed on a per-pin basis. 15 + Each port supports up to 8 pins, each configurable for either GPIO (port mode) 16 + or alternate function mode. Each pin supports function mode values ranging from 17 + 0x0 to 0x2A, allowing selection from up to 43 different functions. 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - renesas,r9a09g077-pinctrl # RZ/T2H 23 + - renesas,r9a09g087-pinctrl # RZ/N2H 24 + 25 + reg: 26 + minItems: 1 27 + items: 28 + - description: Non-safety I/O Port base 29 + - description: Safety I/O Port safety region base 30 + - description: Safety I/O Port Non-safety region base 31 + 32 + reg-names: 33 + minItems: 1 34 + items: 35 + - const: nsr 36 + - const: srs 37 + - const: srn 38 + 39 + gpio-controller: true 40 + 41 + '#gpio-cells': 42 + const: 2 43 + description: 44 + The first cell contains the global GPIO port index, constructed using the 45 + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 46 + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer 47 + flag. Use the macros defined in include/dt-bindings/gpio/gpio.h. 48 + 49 + gpio-ranges: 50 + maxItems: 1 51 + 52 + clocks: 53 + maxItems: 1 54 + 55 + power-domains: 56 + maxItems: 1 57 + 58 + definitions: 59 + renesas-rzt2h-n2h-pins-node: 60 + type: object 61 + allOf: 62 + - $ref: pincfg-node.yaml# 63 + - $ref: pinmux-node.yaml# 64 + properties: 65 + pinmux: 66 + description: 67 + Values are constructed from I/O port number, pin number, and 68 + alternate function configuration number using the RZT2H_PORT_PINMUX() 69 + helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>. 70 + pins: true 71 + phandle: true 72 + input: true 73 + input-enable: true 74 + output-enable: true 75 + oneOf: 76 + - required: [pinmux] 77 + - required: [pins] 78 + additionalProperties: false 79 + 80 + patternProperties: 81 + # Grouping nodes: allow multiple "-pins" subnodes within a "-group" 82 + '.*-group$': 83 + type: object 84 + description: 85 + Pin controller client devices can organize pin configuration entries into 86 + grouping nodes ending in "-group". These group nodes may contain multiple 87 + child nodes each ending in "-pins" to configure distinct sets of pins. 88 + additionalProperties: false 89 + patternProperties: 90 + '-pins$': 91 + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' 92 + 93 + # Standalone "-pins" nodes under client devices or groups 94 + '-pins$': 95 + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' 96 + 97 + '-hog$': 98 + type: object 99 + description: GPIO hog node 100 + properties: 101 + gpio-hog: true 102 + gpios: true 103 + input: true 104 + output-high: true 105 + output-low: true 106 + line-name: true 107 + required: 108 + - gpio-hog 109 + - gpios 110 + additionalProperties: false 111 + 112 + allOf: 113 + - $ref: pinctrl.yaml# 114 + 115 + required: 116 + - compatible 117 + - reg 118 + - reg-names 119 + - gpio-controller 120 + - '#gpio-cells' 121 + - gpio-ranges 122 + - clocks 123 + - power-domains 124 + 125 + unevaluatedProperties: false 126 + 127 + examples: 128 + - | 129 + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> 130 + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 131 + 132 + pinctrl@802c0000 { 133 + compatible = "renesas,r9a09g077-pinctrl"; 134 + reg = <0x802c0000 0x2000>, 135 + <0x812c0000 0x2000>, 136 + <0x802b0000 0x2000>; 137 + reg-names = "nsr", "srs", "srn"; 138 + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 139 + gpio-controller; 140 + #gpio-cells = <2>; 141 + gpio-ranges = <&pinctrl 0 0 288>; 142 + power-domains = <&cpg>; 143 + 144 + serial0-pins { 145 + pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */ 146 + <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */ 147 + }; 148 + 149 + sd1-pwr-en-hog { 150 + gpio-hog; 151 + gpios = <RZT2H_GPIO(39, 2) 0>; 152 + output-high; 153 + line-name = "sd1_pwr_en"; 154 + }; 155 + 156 + i2c0-pins { 157 + pins = "RIIC0_SDA", "RIIC0_SCL"; 158 + input-enable; 159 + }; 160 + 161 + sd0-sd-group { 162 + ctrl-pins { 163 + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ 164 + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ 165 + }; 166 + 167 + data-pins { 168 + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ 169 + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ 170 + }; 171 + }; 172 + };

+13

drivers/pinctrl/renesas/Kconfig

··· 44 44 select PINCTRL_RZG2L if ARCH_R9A09G047 45 45 select PINCTRL_RZG2L if ARCH_R9A09G056 46 46 select PINCTRL_RZG2L if ARCH_R9A09G057 47 + select PINCTRL_RZT2H if ARCH_R9A09G077 48 + select PINCTRL_RZT2H if ARCH_R9A09G087 47 49 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 48 50 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 49 51 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 ··· 303 301 select PINMUX 304 302 help 305 303 This selects pinctrl driver for Renesas RZ/N1 devices. 304 + 305 + config PINCTRL_RZT2H 306 + bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST 307 + depends on 64BIT && OF 308 + select GPIOLIB 309 + select GENERIC_PINCTRL_GROUPS 310 + select GENERIC_PINMUX_FUNCTIONS 311 + select GENERIC_PINCONF 312 + help 313 + This selects GPIO and pinctrl driver for Renesas RZ/T2H 314 + platforms. 306 315 307 316 config PINCTRL_RZV2M 308 317 bool "pin control support for RZ/V2M" if COMPILE_TEST

+1

drivers/pinctrl/renesas/Makefile

··· 50 50 obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o 51 51 obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o 52 52 obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o 53 + obj-$(CONFIG_PINCTRL_RZT2H) += pinctrl-rzt2h.o 53 54 obj-$(CONFIG_PINCTRL_RZV2M) += pinctrl-rzv2m.o 54 55 55 56 ifeq ($(CONFIG_COMPILE_TEST),y)

+90 -107

drivers/pinctrl/renesas/pinctrl-rzg2l.c

··· 146 146 #define SD_CH(off, ch) ((off) + (ch) * 4) 147 147 #define ETH_POC(off, ch) ((off) + (ch) * 4) 148 148 #define QSPI (0x3008) 149 - #define ETH_MODE (0x3018) 150 - #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ 151 149 152 150 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ 153 151 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ ··· 219 221 * @pwpr: PWPR register offset 220 222 * @sd_ch: SD_CH register offset 221 223 * @eth_poc: ETH_POC register offset 224 + * @oen: OEN register offset 222 225 */ 223 226 struct rzg2l_register_offsets { 224 227 u16 pwpr; 225 228 u16 sd_ch; 226 229 u16 eth_poc; 230 + u16 oen; 227 231 }; 228 232 229 233 /** ··· 254 254 * @iolh_groupb_oi: IOLH group B output impedance specific values 255 255 * @tint_start_index: the start index for the TINT interrupts 256 256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 257 + * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR 257 258 * @func_base: base number for port function (see register PFC) 258 259 * @oen_max_pin: the maximum pin number supporting output enable 259 260 * @oen_max_port: the maximum port number supporting output enable ··· 267 266 u16 iolh_groupb_oi[4]; 268 267 u16 tint_start_index; 269 268 bool drive_strength_ua; 269 + bool oen_pwpr_lock; 270 270 u8 func_base; 271 271 u8 oen_max_pin; 272 272 u8 oen_max_port; ··· 297 295 #endif 298 296 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); 299 297 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); 300 - u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 301 - int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); 298 + int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 302 299 int (*hw_to_bias_param)(unsigned int val); 303 300 int (*bias_param_to_hw)(enum pin_config_param param); 304 301 }; ··· 323 322 * @ien: IEN registers cache 324 323 * @sd_ch: SD_CH registers cache 325 324 * @eth_poc: ET_POC registers cache 326 - * @eth_mode: ETH_MODE register cache 325 + * @oen: Output Enable register cache 327 326 * @qspi: QSPI registers cache 328 327 */ 329 328 struct rzg2l_pinctrl_reg_cache { ··· 336 335 u32 *pupd[2]; 337 336 u8 sd_ch[2]; 338 337 u8 eth_poc[2]; 339 - u8 eth_mode; 338 + u8 oen; 340 339 u8 qspi; 341 340 }; 342 341 ··· 395 394 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), 396 395 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), 397 396 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), 397 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), 398 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 399 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), 400 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), 401 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), 402 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), 403 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), 404 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), 398 405 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 399 406 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), 400 407 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), ··· 411 402 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), 412 403 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), 413 404 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), 405 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), 406 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 407 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), 408 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), 409 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), 410 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), 411 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), 412 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), 414 413 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), 415 414 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 416 415 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), ··· 438 421 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), 439 422 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), 440 423 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), 424 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 425 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 426 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 427 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), 428 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 429 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), 430 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), 431 + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), 441 432 }; 442 433 443 434 static const u64 r9a09g057_variable_pin_cfg[] = { ··· 1090 1065 return -EINVAL; 1091 1066 } 1092 1067 1093 - static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1068 + static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1094 1069 { 1095 1070 int bit; 1096 1071 1097 - bit = rzg2l_pin_to_oen_bit(pctrl, _pin); 1098 - if (bit < 0) 1099 - return 0; 1072 + if (!pctrl->data->pin_to_oen_bit) 1073 + return -EOPNOTSUPP; 1100 1074 1101 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1075 + bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1076 + if (bit < 0) 1077 + return -EINVAL; 1078 + 1079 + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); 1102 1080 } 1103 1081 1104 1082 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1105 1083 { 1084 + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 1085 + u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1106 1086 unsigned long flags; 1087 + u8 val, pwpr; 1107 1088 int bit; 1108 - u8 val; 1109 1089 1110 - bit = rzg2l_pin_to_oen_bit(pctrl, _pin); 1090 + if (!pctrl->data->pin_to_oen_bit) 1091 + return -EOPNOTSUPP; 1092 + 1093 + bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1111 1094 if (bit < 0) 1112 - return bit; 1095 + return -EINVAL; 1113 1096 1114 1097 spin_lock_irqsave(&pctrl->lock, flags); 1115 - val = readb(pctrl->base + ETH_MODE); 1098 + val = readb(pctrl->base + oen_offset); 1116 1099 if (oen) 1117 1100 val &= ~BIT(bit); 1118 1101 else 1119 1102 val |= BIT(bit); 1120 - writeb(val, pctrl->base + ETH_MODE); 1103 + if (pctrl->data->hwcfg->oen_pwpr_lock) { 1104 + pwpr = readb(pctrl->base + regs->pwpr); 1105 + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1106 + } 1107 + writeb(val, pctrl->base + oen_offset); 1108 + if (pctrl->data->hwcfg->oen_pwpr_lock) 1109 + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1121 1110 spin_unlock_irqrestore(&pctrl->lock, flags); 1122 1111 1123 1112 return 0; ··· 1155 1116 bit += 1; 1156 1117 1157 1118 return bit; 1158 - } 1159 - 1160 - static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1161 - { 1162 - int bit; 1163 - 1164 - bit = rzg3s_pin_to_oen_bit(pctrl, _pin); 1165 - if (bit < 0) 1166 - return bit; 1167 - 1168 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); 1169 - } 1170 - 1171 - static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1172 - { 1173 - unsigned long flags; 1174 - int bit; 1175 - u8 val; 1176 - 1177 - bit = rzg3s_pin_to_oen_bit(pctrl, _pin); 1178 - if (bit < 0) 1179 - return bit; 1180 - 1181 - spin_lock_irqsave(&pctrl->lock, flags); 1182 - val = readb(pctrl->base + ETH_MODE); 1183 - if (oen) 1184 - val &= ~BIT(bit); 1185 - else 1186 - val |= BIT(bit); 1187 - writeb(val, pctrl->base + ETH_MODE); 1188 - spin_unlock_irqrestore(&pctrl->lock, flags); 1189 - 1190 - return 0; 1191 1119 } 1192 1120 1193 1121 static int rzg2l_hw_to_bias_param(unsigned int bias) ··· 1222 1216 return -EINVAL; 1223 1217 } 1224 1218 1225 - static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1219 + static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin, 1220 + const char * const pin_names[], unsigned int count) 1226 1221 { 1227 - static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", 1228 - "XSPI0_RESET0N", "XSPI0_CS0N", 1229 - "XSPI0_CKN", "XSPI0_CKP" }; 1230 1222 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; 1231 1223 unsigned int i; 1232 1224 1233 - for (i = 0; i < ARRAY_SIZE(pin_names); i++) { 1225 + for (i = 0; i < count; i++) { 1234 1226 if (!strcmp(pin_desc->name, pin_names[i])) 1235 1227 return i; 1236 1228 } 1237 1229 1238 - /* Should not happen. */ 1239 - return 0; 1230 + return -EINVAL; 1240 1231 } 1241 1232 1242 - static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1233 + static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1243 1234 { 1244 - u8 bit; 1235 + static const char * const pin_names[] = { 1236 + "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", 1237 + "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" 1238 + }; 1245 1239 1246 - bit = rzv2h_pin_to_oen_bit(pctrl, _pin); 1247 - 1248 - return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); 1240 + return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1249 1241 } 1250 1242 1251 - static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1243 + static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1252 1244 { 1253 - const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1254 - const struct rzg2l_register_offsets *regs = &hwcfg->regs; 1255 - unsigned long flags; 1256 - u8 val, bit; 1257 - u8 pwpr; 1245 + static const char * const pin_names[] = { 1246 + "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" 1247 + }; 1258 1248 1259 - bit = rzv2h_pin_to_oen_bit(pctrl, _pin); 1260 - spin_lock_irqsave(&pctrl->lock, flags); 1261 - val = readb(pctrl->base + PFC_OEN); 1262 - if (oen) 1263 - val &= ~BIT(bit); 1264 - else 1265 - val |= BIT(bit); 1266 - 1267 - pwpr = readb(pctrl->base + regs->pwpr); 1268 - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1269 - writeb(val, pctrl->base + PFC_OEN); 1270 - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1271 - spin_unlock_irqrestore(&pctrl->lock, flags); 1272 - 1273 - return 0; 1249 + return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1274 1250 } 1275 1251 1276 1252 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, ··· 1296 1308 case PIN_CONFIG_OUTPUT_ENABLE: 1297 1309 if (!(cfg & PIN_CFG_OEN)) 1298 1310 return -EINVAL; 1299 - if (!pctrl->data->oen_read) 1300 - return -EOPNOTSUPP; 1301 - arg = pctrl->data->oen_read(pctrl, _pin); 1302 - if (!arg) 1303 - return -EINVAL; 1311 + ret = rzg2l_read_oen(pctrl, _pin); 1312 + if (ret < 0) 1313 + return ret; 1314 + arg = ret; 1304 1315 break; 1305 1316 1306 1317 case PIN_CONFIG_POWER_SOURCE: ··· 1458 1471 case PIN_CONFIG_OUTPUT_ENABLE: 1459 1472 if (!(cfg & PIN_CFG_OEN)) 1460 1473 return -EINVAL; 1461 - if (!pctrl->data->oen_write) 1462 - return -EOPNOTSUPP; 1463 - ret = pctrl->data->oen_write(pctrl, _pin, !!arg); 1474 + ret = rzg2l_write_oen(pctrl, _pin, !!arg); 1464 1475 if (ret) 1465 1476 return ret; 1466 1477 break; ··· 2043 2058 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 2044 2059 0x0, 2045 2060 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ 2046 - RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */ 2061 + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ 2047 2062 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ 2048 2063 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ 2049 - RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */ 2064 + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ 2050 2065 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ 2051 2066 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ 2052 2067 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 2053 2068 0x0, 2054 2069 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ 2055 2070 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ 2056 - RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */ 2071 + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ 2057 2072 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 2058 2073 0x0, 2059 2074 0x0, ··· 3149 3164 } 3150 3165 3151 3166 cache->qspi = readb(pctrl->base + QSPI); 3152 - cache->eth_mode = readb(pctrl->base + ETH_MODE); 3167 + cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); 3153 3168 3154 3169 if (!atomic_read(&pctrl->wakeup_path)) 3155 3170 clk_disable_unprepare(pctrl->clk); ··· 3174 3189 } 3175 3190 3176 3191 writeb(cache->qspi, pctrl->base + QSPI); 3177 - writeb(cache->eth_mode, pctrl->base + ETH_MODE); 3192 + writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); 3178 3193 for (u8 i = 0; i < 2; i++) { 3179 3194 if (regs->sd_ch) 3180 3195 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); ··· 3226 3241 .pwpr = 0x3014, 3227 3242 .sd_ch = 0x3000, 3228 3243 .eth_poc = 0x300c, 3244 + .oen = 0x3018, 3229 3245 }, 3230 3246 .iolh_groupa_ua = { 3231 3247 /* 3v3 power source */ ··· 3242 3256 .pwpr = 0x3000, 3243 3257 .sd_ch = 0x3004, 3244 3258 .eth_poc = 0x3010, 3259 + .oen = 0x3018, 3245 3260 }, 3246 3261 .iolh_groupa_ua = { 3247 3262 /* 1v8 power source */ ··· 3274 3287 static const struct rzg2l_hwcfg rzv2h_hwcfg = { 3275 3288 .regs = { 3276 3289 .pwpr = 0x3c04, 3290 + .oen = 0x3c40, 3277 3291 }, 3278 3292 .tint_start_index = 17, 3293 + .oen_pwpr_lock = true, 3279 3294 }; 3280 3295 3281 3296 static struct rzg2l_pinctrl_data r9a07g043_data = { ··· 3294 3305 #endif 3295 3306 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3296 3307 .pmc_writeb = &rzg2l_pmc_writeb, 3297 - .oen_read = &rzg2l_read_oen, 3298 - .oen_write = &rzg2l_write_oen, 3308 + .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3299 3309 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3300 3310 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3301 3311 }; ··· 3310 3322 .hwcfg = &rzg2l_hwcfg, 3311 3323 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3312 3324 .pmc_writeb = &rzg2l_pmc_writeb, 3313 - .oen_read = &rzg2l_read_oen, 3314 - .oen_write = &rzg2l_write_oen, 3325 + .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3315 3326 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3316 3327 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3317 3328 }; ··· 3325 3338 .hwcfg = &rzg3s_hwcfg, 3326 3339 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3327 3340 .pmc_writeb = &rzg2l_pmc_writeb, 3328 - .oen_read = &rzg3s_oen_read, 3329 - .oen_write = &rzg3s_oen_write, 3341 + .pin_to_oen_bit = &rzg3s_pin_to_oen_bit, 3330 3342 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3331 3343 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3332 3344 }; ··· 3347 3361 #endif 3348 3362 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3349 3363 .pmc_writeb = &rzv2h_pmc_writeb, 3350 - .oen_read = &rzv2h_oen_read, 3351 - .oen_write = &rzv2h_oen_write, 3364 + .pin_to_oen_bit = &rzg3e_pin_to_oen_bit, 3352 3365 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3353 3366 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3354 3367 }; ··· 3369 3384 #endif 3370 3385 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3371 3386 .pmc_writeb = &rzv2h_pmc_writeb, 3372 - .oen_read = &rzv2h_oen_read, 3373 - .oen_write = &rzv2h_oen_write, 3387 + .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3374 3388 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3375 3389 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3376 3390 }; ··· 3392 3408 #endif 3393 3409 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3394 3410 .pmc_writeb = &rzv2h_pmc_writeb, 3395 - .oen_read = &rzv2h_oen_read, 3396 - .oen_write = &rzv2h_oen_write, 3411 + .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3397 3412 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3398 3413 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3399 3414 };

+813

drivers/pinctrl/renesas/pinctrl-rzt2h.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Renesas RZ/T2H Pin Control and GPIO driver core 4 + * 5 + * Based on drivers/pinctrl/renesas/pinctrl-rzg2l.c 6 + * 7 + * Copyright (C) 2025 Renesas Electronics Corporation. 8 + */ 9 + 10 + #include <linux/bitfield.h> 11 + #include <linux/bitops.h> 12 + #include <linux/bits.h> 13 + #include <linux/cleanup.h> 14 + #include <linux/clk.h> 15 + #include <linux/gpio/driver.h> 16 + #include <linux/io.h> 17 + #include <linux/ioport.h> 18 + #include <linux/module.h> 19 + #include <linux/mutex.h> 20 + #include <linux/of_device.h> 21 + #include <linux/platform_device.h> 22 + #include <linux/pm_runtime.h> 23 + #include <linux/spinlock.h> 24 + #include <linux/types.h> 25 + 26 + #include <linux/pinctrl/consumer.h> 27 + #include <linux/pinctrl/pinconf-generic.h> 28 + #include <linux/pinctrl/pinconf.h> 29 + #include <linux/pinctrl/pinctrl.h> 30 + #include <linux/pinctrl/pinmux.h> 31 + 32 + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> 33 + 34 + #include "../core.h" 35 + #include "../pinconf.h" 36 + #include "../pinmux.h" 37 + 38 + #define DRV_NAME "pinctrl-rzt2h" 39 + 40 + #define P(m) (0x001 * (m)) 41 + #define PM(m) (0x200 + 2 * (m)) 42 + #define PMC(m) (0x400 + (m)) 43 + #define PFC(m) (0x600 + 8 * (m)) 44 + #define PIN(m) (0x800 + (m)) 45 + #define RSELP(m) (0xc00 + (m)) 46 + 47 + #define PM_MASK GENMASK(1, 0) 48 + #define PM_PIN_MASK(pin) (PM_MASK << ((pin) * 2)) 49 + #define PM_INPUT BIT(0) 50 + #define PM_OUTPUT BIT(1) 51 + 52 + #define PFC_MASK GENMASK_ULL(5, 0) 53 + #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) 54 + 55 + /* 56 + * Use 16 lower bits [15:0] for pin identifier 57 + * Use 8 higher bits [23:16] for pin mux function 58 + */ 59 + #define MUX_PIN_ID_MASK GENMASK(15, 0) 60 + #define MUX_FUNC_MASK GENMASK(23, 16) 61 + 62 + #define RZT2H_PIN_ID_TO_PORT(id) ((id) / RZT2H_PINS_PER_PORT) 63 + #define RZT2H_PIN_ID_TO_PIN(id) ((id) % RZT2H_PINS_PER_PORT) 64 + 65 + #define RZT2H_MAX_SAFETY_PORTS 12 66 + 67 + struct rzt2h_pinctrl_data { 68 + unsigned int n_port_pins; 69 + const u8 *port_pin_configs; 70 + unsigned int n_ports; 71 + }; 72 + 73 + struct rzt2h_pinctrl { 74 + struct pinctrl_dev *pctl; 75 + struct pinctrl_desc desc; 76 + struct pinctrl_pin_desc *pins; 77 + const struct rzt2h_pinctrl_data *data; 78 + void __iomem *base0, *base1; 79 + struct device *dev; 80 + struct gpio_chip gpio_chip; 81 + struct pinctrl_gpio_range gpio_range; 82 + spinlock_t lock; /* lock read/write registers */ 83 + struct mutex mutex; /* serialize adding groups and functions */ 84 + bool safety_port_enabled; 85 + }; 86 + 87 + #define RZT2H_GET_BASE(pctrl, port) \ 88 + ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1) 89 + 90 + #define RZT2H_PINCTRL_REG_ACCESS(size, type) \ 91 + static inline void rzt2h_pinctrl_write##size(struct rzt2h_pinctrl *pctrl, u8 port, \ 92 + type val, unsigned int offset) \ 93 + { \ 94 + write##size(val, RZT2H_GET_BASE(pctrl, port) + offset); \ 95 + } \ 96 + static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port, \ 97 + unsigned int offset) \ 98 + { \ 99 + return read##size(RZT2H_GET_BASE(pctrl, port) + offset); \ 100 + } 101 + 102 + RZT2H_PINCTRL_REG_ACCESS(b, u8) 103 + RZT2H_PINCTRL_REG_ACCESS(w, u16) 104 + RZT2H_PINCTRL_REG_ACCESS(q, u64) 105 + 106 + static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset) 107 + { 108 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 109 + u8 pin = RZT2H_PIN_ID_TO_PIN(offset); 110 + u8 pincfg; 111 + 112 + if (offset >= pctrl->data->n_port_pins || port >= pctrl->data->n_ports) 113 + return -EINVAL; 114 + 115 + if (!pctrl->safety_port_enabled && port <= RZT2H_MAX_SAFETY_PORTS) 116 + return -EINVAL; 117 + 118 + pincfg = pctrl->data->port_pin_configs[port]; 119 + return (pincfg & BIT(pin)) ? 0 : -EINVAL; 120 + } 121 + 122 + static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, 123 + u8 port, u8 pin, u8 func) 124 + { 125 + u64 reg64; 126 + u16 reg16; 127 + 128 + guard(spinlock_irqsave)(&pctrl->lock); 129 + 130 + /* Set pin to 'Non-use (Hi-Z input protection)' */ 131 + reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 132 + reg16 &= ~PM_PIN_MASK(pin); 133 + rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port)); 134 + 135 + /* Temporarily switch to GPIO mode with PMC register */ 136 + reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 137 + rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port)); 138 + 139 + /* Select Pin function mode with PFC register */ 140 + reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port)); 141 + reg64 &= ~PFC_PIN_MASK(pin); 142 + rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port)); 143 + 144 + /* Switch to Peripheral pin function with PMC register */ 145 + reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 146 + rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port)); 147 + }; 148 + 149 + static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, 150 + unsigned int func_selector, 151 + unsigned int group_selector) 152 + { 153 + struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 154 + const struct function_desc *func; 155 + struct group_desc *group; 156 + const unsigned int *pins; 157 + unsigned int i; 158 + u8 *psel_val; 159 + int ret; 160 + 161 + func = pinmux_generic_get_function(pctldev, func_selector); 162 + if (!func) 163 + return -EINVAL; 164 + 165 + group = pinctrl_generic_get_group(pctldev, group_selector); 166 + if (!group) 167 + return -EINVAL; 168 + 169 + psel_val = func->data; 170 + pins = group->grp.pins; 171 + 172 + for (i = 0; i < group->grp.npins; i++) { 173 + dev_dbg(pctrl->dev, "port:%u pin:%u PSEL:%u\n", 174 + RZT2H_PIN_ID_TO_PORT(pins[i]), RZT2H_PIN_ID_TO_PIN(pins[i]), 175 + psel_val[i]); 176 + ret = rzt2h_validate_pin(pctrl, pins[i]); 177 + if (ret) 178 + return ret; 179 + 180 + rzt2h_pinctrl_set_pfc_mode(pctrl, RZT2H_PIN_ID_TO_PORT(pins[i]), 181 + RZT2H_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 182 + } 183 + 184 + return 0; 185 + }; 186 + 187 + static int rzt2h_map_add_config(struct pinctrl_map *map, 188 + const char *group_or_pin, 189 + enum pinctrl_map_type type, 190 + unsigned long *configs, 191 + unsigned int num_configs) 192 + { 193 + unsigned long *cfgs; 194 + 195 + cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 196 + if (!cfgs) 197 + return -ENOMEM; 198 + 199 + map->type = type; 200 + map->data.configs.group_or_pin = group_or_pin; 201 + map->data.configs.configs = cfgs; 202 + map->data.configs.num_configs = num_configs; 203 + 204 + return 0; 205 + } 206 + 207 + static int rzt2h_dt_subnode_to_map(struct pinctrl_dev *pctldev, 208 + struct device_node *np, 209 + struct device_node *parent, 210 + struct pinctrl_map **map, 211 + unsigned int *num_maps, 212 + unsigned int *index) 213 + { 214 + struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 215 + struct pinctrl_map *maps = *map; 216 + unsigned int nmaps = *num_maps; 217 + unsigned long *configs = NULL; 218 + unsigned int num_pinmux = 0; 219 + unsigned int idx = *index; 220 + unsigned int num_pins, i; 221 + unsigned int num_configs; 222 + struct property *pinmux; 223 + struct property *prop; 224 + int ret, gsel, fsel; 225 + const char **pin_fn; 226 + unsigned int *pins; 227 + const char *name; 228 + const char *pin; 229 + u8 *psel_val; 230 + 231 + pinmux = of_find_property(np, "pinmux", NULL); 232 + if (pinmux) 233 + num_pinmux = pinmux->length / sizeof(u32); 234 + 235 + ret = of_property_count_strings(np, "pins"); 236 + if (ret == -EINVAL) { 237 + num_pins = 0; 238 + } else if (ret < 0) { 239 + dev_err(pctrl->dev, "Invalid pins list in DT\n"); 240 + return ret; 241 + } else { 242 + num_pins = ret; 243 + } 244 + 245 + if (!num_pinmux && !num_pins) 246 + return 0; 247 + 248 + if (num_pinmux && num_pins) { 249 + dev_err(pctrl->dev, 250 + "DT node must contain either a pinmux or pins and not both\n"); 251 + return -EINVAL; 252 + } 253 + 254 + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 255 + if (ret < 0) 256 + return ret; 257 + 258 + if (num_pins && !num_configs) { 259 + dev_err(pctrl->dev, "DT node must contain a config\n"); 260 + ret = -ENODEV; 261 + goto done; 262 + } 263 + 264 + if (num_pinmux) { 265 + nmaps += 1; 266 + if (num_configs) 267 + nmaps += 1; 268 + } 269 + 270 + if (num_pins) 271 + nmaps += num_pins; 272 + 273 + maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 274 + if (!maps) { 275 + ret = -ENOMEM; 276 + goto done; 277 + } 278 + 279 + *map = maps; 280 + *num_maps = nmaps; 281 + if (num_pins) { 282 + of_property_for_each_string(np, "pins", prop, pin) { 283 + ret = rzt2h_map_add_config(&maps[idx], pin, 284 + PIN_MAP_TYPE_CONFIGS_PIN, 285 + configs, num_configs); 286 + if (ret < 0) 287 + goto done; 288 + 289 + idx++; 290 + } 291 + ret = 0; 292 + goto done; 293 + } 294 + 295 + pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 296 + psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 297 + GFP_KERNEL); 298 + pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 299 + if (!pins || !psel_val || !pin_fn) { 300 + ret = -ENOMEM; 301 + goto done; 302 + } 303 + 304 + /* Collect pin locations and mux settings from DT properties */ 305 + for (i = 0; i < num_pinmux; ++i) { 306 + u32 value; 307 + 308 + ret = of_property_read_u32_index(np, "pinmux", i, &value); 309 + if (ret) 310 + goto done; 311 + pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 312 + psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 313 + } 314 + 315 + if (parent) { 316 + name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 317 + parent, np); 318 + if (!name) { 319 + ret = -ENOMEM; 320 + goto done; 321 + } 322 + } else { 323 + name = np->name; 324 + } 325 + 326 + if (num_configs) { 327 + ret = rzt2h_map_add_config(&maps[idx], name, 328 + PIN_MAP_TYPE_CONFIGS_GROUP, 329 + configs, num_configs); 330 + if (ret < 0) 331 + goto done; 332 + 333 + idx++; 334 + } 335 + 336 + scoped_guard(mutex, &pctrl->mutex) { 337 + /* Register a single pin group listing all the pins we read from DT */ 338 + gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 339 + if (gsel < 0) { 340 + ret = gsel; 341 + goto done; 342 + } 343 + 344 + /* 345 + * Register a single group function where the 'data' is an array PSEL 346 + * register values read from DT. 347 + */ 348 + pin_fn[0] = name; 349 + fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 350 + if (fsel < 0) { 351 + ret = fsel; 352 + goto remove_group; 353 + } 354 + } 355 + 356 + maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 357 + maps[idx].data.mux.group = name; 358 + maps[idx].data.mux.function = name; 359 + idx++; 360 + 361 + dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 362 + ret = 0; 363 + goto done; 364 + 365 + remove_group: 366 + pinctrl_generic_remove_group(pctldev, gsel); 367 + done: 368 + *index = idx; 369 + kfree(configs); 370 + return ret; 371 + } 372 + 373 + static void rzt2h_dt_free_map(struct pinctrl_dev *pctldev, 374 + struct pinctrl_map *map, 375 + unsigned int num_maps) 376 + { 377 + unsigned int i; 378 + 379 + if (!map) 380 + return; 381 + 382 + for (i = 0; i < num_maps; ++i) { 383 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 384 + map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 385 + kfree(map[i].data.configs.configs); 386 + } 387 + kfree(map); 388 + } 389 + 390 + static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev, 391 + struct device_node *np, 392 + struct pinctrl_map **map, 393 + unsigned int *num_maps) 394 + { 395 + struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 396 + unsigned int index; 397 + int ret; 398 + 399 + *map = NULL; 400 + *num_maps = 0; 401 + index = 0; 402 + 403 + for_each_child_of_node_scoped(np, child) { 404 + ret = rzt2h_dt_subnode_to_map(pctldev, child, np, map, 405 + num_maps, &index); 406 + if (ret < 0) 407 + goto done; 408 + } 409 + 410 + if (*num_maps == 0) { 411 + ret = rzt2h_dt_subnode_to_map(pctldev, np, NULL, map, 412 + num_maps, &index); 413 + if (ret < 0) 414 + goto done; 415 + } 416 + 417 + if (*num_maps) 418 + return 0; 419 + 420 + dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 421 + ret = -EINVAL; 422 + 423 + done: 424 + rzt2h_dt_free_map(pctldev, *map, *num_maps); 425 + return ret; 426 + } 427 + 428 + static const struct pinctrl_ops rzt2h_pinctrl_pctlops = { 429 + .get_groups_count = pinctrl_generic_get_group_count, 430 + .get_group_name = pinctrl_generic_get_group_name, 431 + .get_group_pins = pinctrl_generic_get_group_pins, 432 + .dt_node_to_map = rzt2h_dt_node_to_map, 433 + .dt_free_map = rzt2h_dt_free_map, 434 + }; 435 + 436 + static const struct pinmux_ops rzt2h_pinctrl_pmxops = { 437 + .get_functions_count = pinmux_generic_get_function_count, 438 + .get_function_name = pinmux_generic_get_function_name, 439 + .get_function_groups = pinmux_generic_get_function_groups, 440 + .set_mux = rzt2h_pinctrl_set_mux, 441 + .strict = true, 442 + }; 443 + 444 + static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset) 445 + { 446 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 447 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 448 + u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 449 + int ret; 450 + u8 reg; 451 + 452 + ret = rzt2h_validate_pin(pctrl, offset); 453 + if (ret) 454 + return ret; 455 + 456 + ret = pinctrl_gpio_request(chip, offset); 457 + if (ret) 458 + return ret; 459 + 460 + guard(spinlock_irqsave)(&pctrl->lock); 461 + 462 + /* Select GPIO mode in PMC Register */ 463 + reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port)); 464 + reg &= ~BIT(bit); 465 + rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); 466 + 467 + return 0; 468 + } 469 + 470 + static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port, 471 + u8 bit, bool output) 472 + { 473 + u16 reg; 474 + 475 + guard(spinlock_irqsave)(&pctrl->lock); 476 + 477 + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 478 + reg &= ~PM_PIN_MASK(bit); 479 + 480 + reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 481 + rzt2h_pinctrl_writew(pctrl, port, reg, PM(port)); 482 + } 483 + 484 + static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 485 + { 486 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 487 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 488 + u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 489 + u16 reg; 490 + int ret; 491 + 492 + ret = rzt2h_validate_pin(pctrl, offset); 493 + if (ret) 494 + return ret; 495 + 496 + if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) 497 + return -EINVAL; 498 + 499 + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 500 + reg = (reg >> (bit * 2)) & PM_MASK; 501 + if (reg & PM_OUTPUT) 502 + return GPIO_LINE_DIRECTION_OUT; 503 + if (reg & PM_INPUT) 504 + return GPIO_LINE_DIRECTION_IN; 505 + 506 + return -EINVAL; 507 + } 508 + 509 + static int rzt2h_gpio_set(struct gpio_chip *chip, unsigned int offset, 510 + int value) 511 + { 512 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 513 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 514 + u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 515 + u8 reg; 516 + 517 + guard(spinlock_irqsave)(&pctrl->lock); 518 + 519 + reg = rzt2h_pinctrl_readb(pctrl, port, P(port)); 520 + if (value) 521 + rzt2h_pinctrl_writeb(pctrl, port, reg | BIT(bit), P(port)); 522 + else 523 + rzt2h_pinctrl_writeb(pctrl, port, reg & ~BIT(bit), P(port)); 524 + 525 + return 0; 526 + } 527 + 528 + static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset) 529 + { 530 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 531 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 532 + u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 533 + u16 reg; 534 + 535 + reg = rzt2h_pinctrl_readw(pctrl, port, PM(port)); 536 + reg = (reg >> (bit * 2)) & PM_MASK; 537 + if (reg & PM_INPUT) 538 + return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit)); 539 + if (reg & PM_OUTPUT) 540 + return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit)); 541 + 542 + return -EINVAL; 543 + } 544 + 545 + static int rzt2h_gpio_direction_input(struct gpio_chip *chip, 546 + unsigned int offset) 547 + { 548 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 549 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 550 + u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 551 + 552 + rzt2h_gpio_set_direction(pctrl, port, bit, false); 553 + 554 + return 0; 555 + } 556 + 557 + static int rzt2h_gpio_direction_output(struct gpio_chip *chip, 558 + unsigned int offset, int value) 559 + { 560 + struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip); 561 + u8 port = RZT2H_PIN_ID_TO_PORT(offset); 562 + u8 bit = RZT2H_PIN_ID_TO_PIN(offset); 563 + 564 + rzt2h_gpio_set(chip, offset, value); 565 + rzt2h_gpio_set_direction(pctrl, port, bit, true); 566 + 567 + return 0; 568 + } 569 + 570 + static void rzt2h_gpio_free(struct gpio_chip *chip, unsigned int offset) 571 + { 572 + pinctrl_gpio_free(chip, offset); 573 + 574 + /* 575 + * Set the GPIO as an input to ensure that the next GPIO request won't 576 + * drive the GPIO pin as an output. 577 + */ 578 + rzt2h_gpio_direction_input(chip, offset); 579 + } 580 + 581 + static const char * const rzt2h_gpio_names[] = { 582 + "P00_0", "P00_1", "P00_2", "P00_3", "P00_4", "P00_5", "P00_6", "P00_7", 583 + "P01_0", "P01_1", "P01_2", "P01_3", "P01_4", "P01_5", "P01_6", "P01_7", 584 + "P02_0", "P02_1", "P02_2", "P02_3", "P02_4", "P02_5", "P02_6", "P02_7", 585 + "P03_0", "P03_1", "P03_2", "P03_3", "P03_4", "P03_5", "P03_6", "P03_7", 586 + "P04_0", "P04_1", "P04_2", "P04_3", "P04_4", "P04_5", "P04_6", "P04_7", 587 + "P05_0", "P05_1", "P05_2", "P05_3", "P05_4", "P05_5", "P05_6", "P05_7", 588 + "P06_0", "P06_1", "P06_2", "P06_3", "P06_4", "P06_5", "P06_6", "P06_7", 589 + "P07_0", "P07_1", "P07_2", "P07_3", "P07_4", "P07_5", "P07_6", "P07_7", 590 + "P08_0", "P08_1", "P08_2", "P08_3", "P08_4", "P08_5", "P08_6", "P08_7", 591 + "P09_0", "P09_1", "P09_2", "P09_3", "P09_4", "P09_5", "P09_6", "P09_7", 592 + "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 593 + "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 594 + "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 595 + "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 596 + "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 597 + "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 598 + "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 599 + "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 600 + "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 601 + "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 602 + "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 603 + "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 604 + "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 605 + "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 606 + "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 607 + "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 608 + "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 609 + "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 610 + "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 611 + "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 612 + "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 613 + "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 614 + "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 615 + "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 616 + "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 617 + "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 618 + }; 619 + 620 + static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) 621 + { 622 + struct pinctrl_gpio_range *range = &pctrl->gpio_range; 623 + struct gpio_chip *chip = &pctrl->gpio_chip; 624 + struct device *dev = pctrl->dev; 625 + struct of_phandle_args of_args; 626 + int ret; 627 + 628 + ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args); 629 + if (ret) 630 + return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n"); 631 + 632 + if (of_args.args[0] != 0 || of_args.args[1] != 0 || 633 + of_args.args[2] != pctrl->data->n_port_pins) 634 + return dev_err_probe(dev, -EINVAL, 635 + "gpio-ranges does not match selected SOC\n"); 636 + 637 + chip->base = -1; 638 + chip->parent = dev; 639 + chip->owner = THIS_MODULE; 640 + chip->ngpio = of_args.args[2]; 641 + chip->names = rzt2h_gpio_names; 642 + chip->request = rzt2h_gpio_request; 643 + chip->free = rzt2h_gpio_free; 644 + chip->get_direction = rzt2h_gpio_get_direction; 645 + chip->direction_input = rzt2h_gpio_direction_input; 646 + chip->direction_output = rzt2h_gpio_direction_output; 647 + chip->get = rzt2h_gpio_get; 648 + chip->set = rzt2h_gpio_set; 649 + chip->label = dev_name(dev); 650 + 651 + range->id = 0; 652 + range->pin_base = 0; 653 + range->base = 0; 654 + range->npins = chip->ngpio; 655 + range->name = chip->label; 656 + range->gc = chip; 657 + 658 + ret = devm_gpiochip_add_data(dev, chip, pctrl); 659 + if (ret) 660 + return dev_err_probe(dev, ret, "gpiochip registration failed\n"); 661 + 662 + return ret; 663 + } 664 + 665 + static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl) 666 + { 667 + struct pinctrl_desc *desc = &pctrl->desc; 668 + struct device *dev = pctrl->dev; 669 + struct pinctrl_pin_desc *pins; 670 + unsigned int i, j; 671 + int ret; 672 + 673 + desc->name = DRV_NAME; 674 + desc->npins = pctrl->data->n_port_pins; 675 + desc->pctlops = &rzt2h_pinctrl_pctlops; 676 + desc->pmxops = &rzt2h_pinctrl_pmxops; 677 + desc->owner = THIS_MODULE; 678 + 679 + pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL); 680 + if (!pins) 681 + return -ENOMEM; 682 + 683 + pctrl->pins = pins; 684 + desc->pins = pins; 685 + 686 + for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 687 + pins[i].number = i; 688 + pins[i].name = rzt2h_gpio_names[i]; 689 + if (i && !(i % RZT2H_PINS_PER_PORT)) 690 + j++; 691 + } 692 + 693 + ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl); 694 + if (ret) 695 + return dev_err_probe(dev, ret, "pinctrl registration failed\n"); 696 + 697 + ret = pinctrl_enable(pctrl->pctl); 698 + if (ret) 699 + return dev_err_probe(dev, ret, "pinctrl enable failed\n"); 700 + 701 + return rzt2h_gpio_register(pctrl); 702 + } 703 + 704 + static int rzt2h_pinctrl_cfg_regions(struct platform_device *pdev, 705 + struct rzt2h_pinctrl *pctrl) 706 + { 707 + struct resource *res; 708 + 709 + pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr"); 710 + if (IS_ERR(pctrl->base0)) 711 + return PTR_ERR(pctrl->base0); 712 + 713 + /* 714 + * Open-coded instead of using devm_platform_ioremap_resource_byname() 715 + * because the "srs" region is optional. 716 + */ 717 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "srs"); 718 + if (res) { 719 + u8 port; 720 + 721 + pctrl->base1 = devm_ioremap_resource(&pdev->dev, res); 722 + if (IS_ERR(pctrl->base1)) 723 + return PTR_ERR(pctrl->base1); 724 + 725 + pctrl->safety_port_enabled = true; 726 + 727 + /* Configure to select safety region 0x812c0xxx */ 728 + for (port = 0; port <= RZT2H_MAX_SAFETY_PORTS; port++) 729 + writeb(0x0, pctrl->base1 + RSELP(port)); 730 + } 731 + 732 + return 0; 733 + } 734 + 735 + static int rzt2h_pinctrl_probe(struct platform_device *pdev) 736 + { 737 + struct device *dev = &pdev->dev; 738 + struct rzt2h_pinctrl *pctrl; 739 + int ret; 740 + 741 + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 742 + if (!pctrl) 743 + return -ENOMEM; 744 + 745 + pctrl->dev = dev; 746 + pctrl->data = of_device_get_match_data(dev); 747 + 748 + ret = rzt2h_pinctrl_cfg_regions(pdev, pctrl); 749 + if (ret) 750 + return ret; 751 + 752 + spin_lock_init(&pctrl->lock); 753 + mutex_init(&pctrl->mutex); 754 + platform_set_drvdata(pdev, pctrl); 755 + 756 + return rzt2h_pinctrl_register(pctrl); 757 + } 758 + 759 + static const u8 r9a09g077_gpio_configs[] = { 760 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 761 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 762 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 763 + }; 764 + 765 + static const u8 r9a09g087_gpio_configs[] = { 766 + 0x1f, 0xff, 0xff, 0x1f, 0x00, 0xfe, 0xff, 0x00, 0x7e, 0xf0, 0xff, 0x01, 767 + 0xff, 0xff, 0xff, 0x00, 0xe0, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x01, 768 + 0xe0, 0xff, 0xff, 0x7f, 0x00, 0xfe, 0xff, 0x7f, 0x00, 0xfc, 0x7f, 769 + }; 770 + 771 + static struct rzt2h_pinctrl_data r9a09g077_data = { 772 + .n_port_pins = ARRAY_SIZE(r9a09g077_gpio_configs) * RZT2H_PINS_PER_PORT, 773 + .port_pin_configs = r9a09g077_gpio_configs, 774 + .n_ports = ARRAY_SIZE(r9a09g077_gpio_configs), 775 + }; 776 + 777 + static struct rzt2h_pinctrl_data r9a09g087_data = { 778 + .n_port_pins = ARRAY_SIZE(r9a09g087_gpio_configs) * RZT2H_PINS_PER_PORT, 779 + .port_pin_configs = r9a09g087_gpio_configs, 780 + .n_ports = ARRAY_SIZE(r9a09g087_gpio_configs), 781 + }; 782 + 783 + static const struct of_device_id rzt2h_pinctrl_of_table[] = { 784 + { 785 + .compatible = "renesas,r9a09g077-pinctrl", 786 + .data = &r9a09g077_data, 787 + }, 788 + { 789 + .compatible = "renesas,r9a09g087-pinctrl", 790 + .data = &r9a09g087_data, 791 + }, 792 + { /* sentinel */ } 793 + }; 794 + 795 + static struct platform_driver rzt2h_pinctrl_driver = { 796 + .driver = { 797 + .name = DRV_NAME, 798 + .of_match_table = of_match_ptr(rzt2h_pinctrl_of_table), 799 + .suppress_bind_attrs = true, 800 + }, 801 + .probe = rzt2h_pinctrl_probe, 802 + }; 803 + 804 + static int __init rzt2h_pinctrl_init(void) 805 + { 806 + return platform_driver_register(&rzt2h_pinctrl_driver); 807 + } 808 + core_initcall(rzt2h_pinctrl_init); 809 + 810 + MODULE_LICENSE("GPL"); 811 + MODULE_AUTHOR("Thierry Bultel <thierry.bultel.yh@bp.renesas.com>"); 812 + MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 813 + MODULE_DESCRIPTION("Pin and gpio controller driver for the RZ/T2H family");

+1

include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

··· 25 25 #define R9A09G077_CLK_PCLKM 13 26 26 #define R9A09G077_CLK_PCLKL 14 27 27 #define R9A09G077_SDHI_CLKHS 15 28 + #define R9A09G077_USB_CLK 16 28 29 29 30 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

+1

include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h

··· 25 25 #define R9A09G087_CLK_PCLKM 13 26 26 #define R9A09G087_CLK_PCLKL 14 27 27 #define R9A09G087_SDHI_CLKHS 15 28 + #define R9A09G087_USB_CLK 16 28 29 29 30 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */

+22

include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * This header provides constants for Renesas RZ/T2H family pinctrl bindings. 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ 9 + #define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ 10 + 11 + #define RZT2H_PINS_PER_PORT 8 12 + 13 + /* 14 + * Create the pin index from its bank and position numbers and store in 15 + * the upper 16 bits the alternate function identifier 16 + */ 17 + #define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16)) 18 + 19 + /* Convert a port and pin label to its global pin index */ 20 + #define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin)) 21 + 22 + #endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */

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