Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: adjust xcc_id program logic for sdma v7_1
Adjust program logic for sdam v7_1, only use physical xcc_id
when program register to support compute partition.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
05282873
98320bf3
+11
-8
+11
-8
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+11
-8
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
···
369
369
u32 rb_cntl, ib_cntl;
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int i;
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-
for (i = 0; i < NUM_XCC(inst_mask); i++) {
372
+
for_each_inst(i, inst_mask) {
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rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL));
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 0);
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WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);
···
436
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if (amdgpu_sriov_vf(adev))
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return;
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-
for (i = 0; i < NUM_XCC(inst_mask); i++) {
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+
for_each_inst(i, inst_mask) {
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mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL));
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mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_SDMA_MCU_CNTL, HALT, enable ? 0 : 1);
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WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), mcu_cntl);
···
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617
{
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int i, r;
619
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-
for (i = 0; i < NUM_XCC(inst_mask); i++) {
620
+
for_each_inst(i, inst_mask) {
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r = sdma_v7_1_gfx_resume_instance(adev, i, false);
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if (r)
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return r;
···
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{
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int i;
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-
for (i = 0; i < NUM_XCC(inst_mask); i++) {
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+
for_each_inst(i, inst_mask) {
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amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj,
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&adev->sdma.instance[i].sdma_fw_gpu_addr,
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(void **)&adev->sdma.instance[i].sdma_fw_ptr);
···
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686
le32_to_cpu(hdr->ucode_offset_bytes));
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fw_size = le32_to_cpu(hdr->ucode_size_bytes);
688
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689
-
for (i = 0; i < NUM_XCC(inst_mask); i++) {
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+
for_each_inst(i, inst_mask) {
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r = amdgpu_bo_create_reserved(adev, fw_size,
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
···
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u32 tmp;
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int i;
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-
inst_mask = adev->sdma.sdma_mask;
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+
inst_mask = GENMASK(NUM_XCC(adev->sdma.sdma_mask) - 1, 0);
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sdma_v7_1_inst_gfx_stop(adev, inst_mask);
749
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750
-
for (i = 0; i < NUM_XCC(inst_mask); i++) {
750
+
for_each_inst(i, inst_mask) {
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//tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FREEZE));
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//tmp |= SDMA0_SDMA_FREEZE__FREEZE_MASK;
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//WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FREEZE), tmp);
···
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static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block)
1358
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{
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struct amdgpu_device *adev = ip_block->adev;
1360
+
uint32_t inst_mask;
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1361
-
return sdma_v7_1_inst_start(adev, adev->sdma.sdma_mask);
1362
+
inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
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+
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+
return sdma_v7_1_inst_start(adev, inst_mask);
1362
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}
1363
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static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block)