Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: Rename msm_gem_address_space -> msm_gem_vm
Re-aligning naming to better match drm_gpuvm terminology will make
things less confusing at the end of the drm_gpuvm conversion.
This is just rename churn, no functional change.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Tested-by: Antonino Maniscalco <antomani103@gmail.com>
Reviewed-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/661466/
+345
-349
+9
-9
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+9
-9
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
···
113
113
uint32_t *ptr, len;
114
114
int i, ret;
115
115
116
-
a2xx_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
116
+
a2xx_gpummu_params(gpu->vm->mmu, &pt_base, &tran_error);
117
117
118
118
DBG("%s", gpu->name);
119
119
···
466
466
return state;
467
467
}
468
468
469
-
static struct msm_gem_address_space *
470
-
a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
469
+
static struct msm_gem_vm *
470
+
a2xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev)
471
471
{
472
472
struct msm_mmu *mmu = a2xx_gpummu_new(&pdev->dev, gpu);
473
-
struct msm_gem_address_space *aspace;
473
+
struct msm_gem_vm *vm;
474
474
475
-
aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
475
+
vm = msm_gem_vm_create(mmu, "gpu", SZ_16M,
476
476
0xfff * SZ_64K);
477
477
478
-
if (IS_ERR(aspace) && !IS_ERR(mmu))
478
+
if (IS_ERR(vm) && !IS_ERR(mmu))
479
479
mmu->funcs->destroy(mmu);
480
480
481
-
return aspace;
481
+
return vm;
482
482
}
483
483
484
484
static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
···
504
504
#endif
505
505
.gpu_state_get = a2xx_gpu_state_get,
506
506
.gpu_state_put = adreno_gpu_state_put,
507
-
.create_address_space = a2xx_create_address_space,
507
+
.create_vm = a2xx_create_vm,
508
508
.get_rptr = a2xx_get_rptr,
509
509
},
510
510
};
···
551
551
else
552
552
adreno_gpu->registers = a220_registers;
553
553
554
-
if (!gpu->aspace) {
554
+
if (!gpu->vm) {
555
555
dev_err(dev->dev, "No memory protection without MMU\n");
556
556
if (!allow_vram_carveout) {
557
557
ret = -ENXIO;
+2
-2
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+2
-2
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
···
526
526
.gpu_busy = a3xx_gpu_busy,
527
527
.gpu_state_get = a3xx_gpu_state_get,
528
528
.gpu_state_put = adreno_gpu_state_put,
529
-
.create_address_space = adreno_create_address_space,
529
+
.create_vm = adreno_create_vm,
530
530
.get_rptr = a3xx_get_rptr,
531
531
},
532
532
};
···
581
581
goto fail;
582
582
}
583
583
584
-
if (!gpu->aspace) {
584
+
if (!gpu->vm) {
585
585
/* TODO we think it is possible to configure the GPU to
586
586
* restrict access to VRAM carveout. But the required
587
587
* registers are unknown. For now just bail out and
+2
-2
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+2
-2
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
···
645
645
.gpu_busy = a4xx_gpu_busy,
646
646
.gpu_state_get = a4xx_gpu_state_get,
647
647
.gpu_state_put = adreno_gpu_state_put,
648
-
.create_address_space = adreno_create_address_space,
648
+
.create_vm = adreno_create_vm,
649
649
.get_rptr = a4xx_get_rptr,
650
650
},
651
651
.get_timestamp = a4xx_get_timestamp,
···
695
695
696
696
adreno_gpu->uche_trap_base = 0xffff0000ffff0000ull;
697
697
698
-
if (!gpu->aspace) {
698
+
if (!gpu->vm) {
699
699
/* TODO we think it is possible to configure the GPU to
700
700
* restrict access to VRAM carveout. But the required
701
701
* registers are unknown. For now just bail out and
+2
-2
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c
+2
-2
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c
···
116
116
adreno_gpu->fw[ADRENO_FW_PFP] = NULL;
117
117
118
118
if (a5xx_gpu->pm4_bo) {
119
-
msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);
119
+
msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->vm);
120
120
drm_gem_object_put(a5xx_gpu->pm4_bo);
121
121
a5xx_gpu->pm4_bo = NULL;
122
122
}
123
123
124
124
if (a5xx_gpu->pfp_bo) {
125
-
msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);
125
+
msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->vm);
126
126
drm_gem_object_put(a5xx_gpu->pfp_bo);
127
127
a5xx_gpu->pfp_bo = NULL;
128
128
}
+11
-11
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+11
-11
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
···
622
622
a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
623
623
sizeof(u32) * gpu->nr_rings,
624
624
MSM_BO_WC | MSM_BO_MAP_PRIV,
625
-
gpu->aspace, &a5xx_gpu->shadow_bo,
625
+
gpu->vm, &a5xx_gpu->shadow_bo,
626
626
&a5xx_gpu->shadow_iova);
627
627
628
628
if (IS_ERR(a5xx_gpu->shadow))
···
1042
1042
a5xx_preempt_fini(gpu);
1043
1043
1044
1044
if (a5xx_gpu->pm4_bo) {
1045
-
msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);
1045
+
msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->vm);
1046
1046
drm_gem_object_put(a5xx_gpu->pm4_bo);
1047
1047
}
1048
1048
1049
1049
if (a5xx_gpu->pfp_bo) {
1050
-
msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);
1050
+
msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->vm);
1051
1051
drm_gem_object_put(a5xx_gpu->pfp_bo);
1052
1052
}
1053
1053
1054
1054
if (a5xx_gpu->gpmu_bo) {
1055
-
msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
1055
+
msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->vm);
1056
1056
drm_gem_object_put(a5xx_gpu->gpmu_bo);
1057
1057
}
1058
1058
1059
1059
if (a5xx_gpu->shadow_bo) {
1060
-
msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->aspace);
1060
+
msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->vm);
1061
1061
drm_gem_object_put(a5xx_gpu->shadow_bo);
1062
1062
}
1063
1063
···
1457
1457
struct a5xx_crashdumper *dumper)
1458
1458
{
1459
1459
dumper->ptr = msm_gem_kernel_new(gpu->dev,
1460
-
SZ_1M, MSM_BO_WC, gpu->aspace,
1460
+
SZ_1M, MSM_BO_WC, gpu->vm,
1461
1461
&dumper->bo, &dumper->iova);
1462
1462
1463
1463
if (!IS_ERR(dumper->ptr))
···
1557
1557
1558
1558
if (a5xx_crashdumper_run(gpu, &dumper)) {
1559
1559
kfree(a5xx_state->hlsqregs);
1560
-
msm_gem_kernel_put(dumper.bo, gpu->aspace);
1560
+
msm_gem_kernel_put(dumper.bo, gpu->vm);
1561
1561
return;
1562
1562
}
1563
1563
···
1565
1565
memcpy(a5xx_state->hlsqregs, dumper.ptr + (256 * SZ_1K),
1566
1566
count * sizeof(u32));
1567
1567
1568
-
msm_gem_kernel_put(dumper.bo, gpu->aspace);
1568
+
msm_gem_kernel_put(dumper.bo, gpu->vm);
1569
1569
}
1570
1570
1571
1571
static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu)
···
1713
1713
.gpu_busy = a5xx_gpu_busy,
1714
1714
.gpu_state_get = a5xx_gpu_state_get,
1715
1715
.gpu_state_put = a5xx_gpu_state_put,
1716
-
.create_address_space = adreno_create_address_space,
1716
+
.create_vm = adreno_create_vm,
1717
1717
.get_rptr = a5xx_get_rptr,
1718
1718
},
1719
1719
.get_timestamp = a5xx_get_timestamp,
···
1786
1786
return ERR_PTR(ret);
1787
1787
}
1788
1788
1789
-
if (gpu->aspace)
1790
-
msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a5xx_fault_handler);
1789
+
if (gpu->vm)
1790
+
msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a5xx_fault_handler);
1791
1791
1792
1792
/* Set up the preemption specific bits and pieces for each ringbuffer */
1793
1793
a5xx_preempt_init(gpu);
+1
-1
drivers/gpu/drm/msm/adreno/a5xx_power.c
+1
-1
drivers/gpu/drm/msm/adreno/a5xx_power.c
···
363
363
bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
364
364
365
365
ptr = msm_gem_kernel_new(drm, bosize,
366
-
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace,
366
+
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->vm,
367
367
&a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova);
368
368
if (IS_ERR(ptr))
369
369
return;
+5
-5
drivers/gpu/drm/msm/adreno/a5xx_preempt.c
+5
-5
drivers/gpu/drm/msm/adreno/a5xx_preempt.c
···
255
255
256
256
ptr = msm_gem_kernel_new(gpu->dev,
257
257
A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,
258
-
MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
258
+
MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->vm, &bo, &iova);
259
259
260
260
if (IS_ERR(ptr))
261
261
return PTR_ERR(ptr);
···
263
263
/* The buffer to store counters needs to be unprivileged */
264
264
counters = msm_gem_kernel_new(gpu->dev,
265
265
A5XX_PREEMPT_COUNTER_SIZE,
266
-
MSM_BO_WC, gpu->aspace, &counters_bo, &counters_iova);
266
+
MSM_BO_WC, gpu->vm, &counters_bo, &counters_iova);
267
267
if (IS_ERR(counters)) {
268
-
msm_gem_kernel_put(bo, gpu->aspace);
268
+
msm_gem_kernel_put(bo, gpu->vm);
269
269
return PTR_ERR(counters);
270
270
}
271
271
···
296
296
int i;
297
297
298
298
for (i = 0; i < gpu->nr_rings; i++) {
299
-
msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->aspace);
300
-
msm_gem_kernel_put(a5xx_gpu->preempt_counters_bo[i], gpu->aspace);
299
+
msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->vm);
300
+
msm_gem_kernel_put(a5xx_gpu->preempt_counters_bo[i], gpu->vm);
301
301
}
302
302
}
303
303
+12
-12
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+12
-12
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
1259
1259
1260
1260
static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1261
1261
{
1262
-
msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1263
-
msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1264
-
msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1265
-
msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1266
-
msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1267
-
msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1262
+
msm_gem_kernel_put(gmu->hfi.obj, gmu->vm);
1263
+
msm_gem_kernel_put(gmu->debug.obj, gmu->vm);
1264
+
msm_gem_kernel_put(gmu->icache.obj, gmu->vm);
1265
+
msm_gem_kernel_put(gmu->dcache.obj, gmu->vm);
1266
+
msm_gem_kernel_put(gmu->dummy.obj, gmu->vm);
1267
+
msm_gem_kernel_put(gmu->log.obj, gmu->vm);
1268
1268
1269
-
gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1270
-
msm_gem_address_space_put(gmu->aspace);
1269
+
gmu->vm->mmu->funcs->detach(gmu->vm->mmu);
1270
+
msm_gem_vm_put(gmu->vm);
1271
1271
}
1272
1272
1273
1273
static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
···
1296
1296
if (IS_ERR(bo->obj))
1297
1297
return PTR_ERR(bo->obj);
1298
1298
1299
-
ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1299
+
ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->vm, &bo->iova,
1300
1300
range_start, range_end);
1301
1301
if (ret) {
1302
1302
drm_gem_object_put(bo->obj);
···
1321
1321
if (IS_ERR(mmu))
1322
1322
return PTR_ERR(mmu);
1323
1323
1324
-
gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1325
-
if (IS_ERR(gmu->aspace))
1326
-
return PTR_ERR(gmu->aspace);
1324
+
gmu->vm = msm_gem_vm_create(mmu, "gmu", 0x0, 0x80000000);
1325
+
if (IS_ERR(gmu->vm))
1326
+
return PTR_ERR(gmu->vm);
1327
1327
1328
1328
return 0;
1329
1329
}
+1
-1
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+1
-1
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+22
-23
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+22
-23
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
120
120
if (ctx->seqno == ring->cur_ctx_seqno)
121
121
return;
122
122
123
-
if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
123
+
if (msm_iommu_pagetable_params(ctx->vm->mmu, &ttbr, &asid))
124
124
return;
125
125
126
126
if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) {
···
970
970
971
971
msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
972
972
if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
973
-
msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
973
+
msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm);
974
974
drm_gem_object_put(a6xx_gpu->sqe_bo);
975
975
976
976
a6xx_gpu->sqe_bo = NULL;
···
987
987
a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
988
988
sizeof(u32) * gpu->nr_rings,
989
989
MSM_BO_WC | MSM_BO_MAP_PRIV,
990
-
gpu->aspace, &a6xx_gpu->shadow_bo,
990
+
gpu->vm, &a6xx_gpu->shadow_bo,
991
991
&a6xx_gpu->shadow_iova);
992
992
993
993
if (IS_ERR(a6xx_gpu->shadow))
···
998
998
999
999
a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE,
1000
1000
MSM_BO_WC | MSM_BO_MAP_PRIV,
1001
-
gpu->aspace, &a6xx_gpu->pwrup_reglist_bo,
1001
+
gpu->vm, &a6xx_gpu->pwrup_reglist_bo,
1002
1002
&a6xx_gpu->pwrup_reglist_iova);
1003
1003
1004
1004
if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr))
···
2211
2211
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2212
2212
2213
2213
if (a6xx_gpu->sqe_bo) {
2214
-
msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
2214
+
msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm);
2215
2215
drm_gem_object_put(a6xx_gpu->sqe_bo);
2216
2216
}
2217
2217
2218
2218
if (a6xx_gpu->shadow_bo) {
2219
-
msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
2219
+
msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm);
2220
2220
drm_gem_object_put(a6xx_gpu->shadow_bo);
2221
2221
}
2222
2222
···
2256
2256
mutex_unlock(&a6xx_gpu->gmu.lock);
2257
2257
}
2258
2258
2259
-
static struct msm_gem_address_space *
2260
-
a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
2259
+
static struct msm_gem_vm *
2260
+
a6xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev)
2261
2261
{
2262
2262
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2263
2263
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
···
2271
2271
!device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY))
2272
2272
quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
2273
2273
2274
-
return adreno_iommu_create_address_space(gpu, pdev, quirks);
2274
+
return adreno_iommu_create_vm(gpu, pdev, quirks);
2275
2275
}
2276
2276
2277
-
static struct msm_gem_address_space *
2278
-
a6xx_create_private_address_space(struct msm_gpu *gpu)
2277
+
static struct msm_gem_vm *
2278
+
a6xx_create_private_vm(struct msm_gpu *gpu)
2279
2279
{
2280
2280
struct msm_mmu *mmu;
2281
2281
2282
-
mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
2282
+
mmu = msm_iommu_pagetable_create(gpu->vm->mmu);
2283
2283
2284
2284
if (IS_ERR(mmu))
2285
2285
return ERR_CAST(mmu);
2286
2286
2287
-
return msm_gem_address_space_create(mmu,
2287
+
return msm_gem_vm_create(mmu,
2288
2288
"gpu", ADRENO_VM_START,
2289
-
adreno_private_address_space_size(gpu));
2289
+
adreno_private_vm_size(gpu));
2290
2290
}
2291
2291
2292
2292
static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
···
2403
2403
.gpu_state_get = a6xx_gpu_state_get,
2404
2404
.gpu_state_put = a6xx_gpu_state_put,
2405
2405
#endif
2406
-
.create_address_space = a6xx_create_address_space,
2407
-
.create_private_address_space = a6xx_create_private_address_space,
2406
+
.create_vm = a6xx_create_vm,
2407
+
.create_private_vm = a6xx_create_private_vm,
2408
2408
.get_rptr = a6xx_get_rptr,
2409
2409
.progress = a6xx_progress,
2410
2410
},
···
2432
2432
.gpu_state_get = a6xx_gpu_state_get,
2433
2433
.gpu_state_put = a6xx_gpu_state_put,
2434
2434
#endif
2435
-
.create_address_space = a6xx_create_address_space,
2436
-
.create_private_address_space = a6xx_create_private_address_space,
2435
+
.create_vm = a6xx_create_vm,
2436
+
.create_private_vm = a6xx_create_private_vm,
2437
2437
.get_rptr = a6xx_get_rptr,
2438
2438
.progress = a6xx_progress,
2439
2439
},
···
2463
2463
.gpu_state_get = a6xx_gpu_state_get,
2464
2464
.gpu_state_put = a6xx_gpu_state_put,
2465
2465
#endif
2466
-
.create_address_space = a6xx_create_address_space,
2467
-
.create_private_address_space = a6xx_create_private_address_space,
2466
+
.create_vm = a6xx_create_vm,
2467
+
.create_private_vm = a6xx_create_private_vm,
2468
2468
.get_rptr = a6xx_get_rptr,
2469
2469
.progress = a6xx_progress,
2470
2470
},
···
2560
2560
2561
2561
adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
2562
2562
2563
-
if (gpu->aspace)
2564
-
msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
2565
-
a6xx_fault_handler);
2563
+
if (gpu->vm)
2564
+
msm_mmu_set_fault_handler(gpu->vm->mmu, gpu, a6xx_fault_handler);
2566
2565
2567
2566
a6xx_calc_ubwc_config(adreno_gpu);
2568
2567
/* Set up the preemption specific bits and pieces for each ringbuffer */
+3
-3
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+3
-3
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
132
132
struct a6xx_crashdumper *dumper)
133
133
{
134
134
dumper->ptr = msm_gem_kernel_new(gpu->dev,
135
-
SZ_1M, MSM_BO_WC, gpu->aspace,
135
+
SZ_1M, MSM_BO_WC, gpu->vm,
136
136
&dumper->bo, &dumper->iova);
137
137
138
138
if (!IS_ERR(dumper->ptr))
···
1619
1619
a7xx_get_clusters(gpu, a6xx_state, dumper);
1620
1620
a7xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
1621
1621
1622
-
msm_gem_kernel_put(dumper->bo, gpu->aspace);
1622
+
msm_gem_kernel_put(dumper->bo, gpu->vm);
1623
1623
}
1624
1624
1625
1625
a7xx_get_post_crashdumper_registers(gpu, a6xx_state);
···
1631
1631
a6xx_get_clusters(gpu, a6xx_state, dumper);
1632
1632
a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
1633
1633
1634
-
msm_gem_kernel_put(dumper->bo, gpu->aspace);
1634
+
msm_gem_kernel_put(dumper->bo, gpu->vm);
1635
1635
}
1636
1636
}
1637
1637
+5
-5
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
+5
-5
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
···
344
344
345
345
ptr = msm_gem_kernel_new(gpu->dev,
346
346
PREEMPT_RECORD_SIZE(adreno_gpu),
347
-
MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
347
+
MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->vm, &bo, &iova);
348
348
349
349
if (IS_ERR(ptr))
350
350
return PTR_ERR(ptr);
···
362
362
ptr = msm_gem_kernel_new(gpu->dev,
363
363
PREEMPT_SMMU_INFO_SIZE,
364
364
MSM_BO_WC | MSM_BO_MAP_PRIV | MSM_BO_GPU_READONLY,
365
-
gpu->aspace, &bo, &iova);
365
+
gpu->vm, &bo, &iova);
366
366
367
367
if (IS_ERR(ptr))
368
368
return PTR_ERR(ptr);
···
377
377
378
378
struct a7xx_cp_smmu_info *smmu_info_ptr = ptr;
379
379
380
-
msm_iommu_pagetable_params(gpu->aspace->mmu, &ttbr, &asid);
380
+
msm_iommu_pagetable_params(gpu->vm->mmu, &ttbr, &asid);
381
381
382
382
smmu_info_ptr->magic = GEN7_CP_SMMU_INFO_MAGIC;
383
383
smmu_info_ptr->ttbr0 = ttbr;
···
405
405
int i;
406
406
407
407
for (i = 0; i < gpu->nr_rings; i++)
408
-
msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->aspace);
408
+
msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->vm);
409
409
}
410
410
411
411
void a6xx_preempt_init(struct msm_gpu *gpu)
···
431
431
a6xx_gpu->preempt_postamble_ptr = msm_gem_kernel_new(gpu->dev,
432
432
PAGE_SIZE,
433
433
MSM_BO_WC | MSM_BO_MAP_PRIV | MSM_BO_GPU_READONLY,
434
-
gpu->aspace, &a6xx_gpu->preempt_postamble_bo,
434
+
gpu->vm, &a6xx_gpu->preempt_postamble_bo,
435
435
&a6xx_gpu->preempt_postamble_iova);
436
436
437
437
preempt_prepare_postamble(a6xx_gpu);
+23
-23
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+23
-23
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
191
191
return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
192
192
}
193
193
194
-
struct msm_gem_address_space *
195
-
adreno_create_address_space(struct msm_gpu *gpu,
196
-
struct platform_device *pdev)
194
+
struct msm_gem_vm *
195
+
adreno_create_vm(struct msm_gpu *gpu,
196
+
struct platform_device *pdev)
197
197
{
198
-
return adreno_iommu_create_address_space(gpu, pdev, 0);
198
+
return adreno_iommu_create_vm(gpu, pdev, 0);
199
199
}
200
200
201
-
struct msm_gem_address_space *
202
-
adreno_iommu_create_address_space(struct msm_gpu *gpu,
203
-
struct platform_device *pdev,
204
-
unsigned long quirks)
201
+
struct msm_gem_vm *
202
+
adreno_iommu_create_vm(struct msm_gpu *gpu,
203
+
struct platform_device *pdev,
204
+
unsigned long quirks)
205
205
{
206
206
struct iommu_domain_geometry *geometry;
207
207
struct msm_mmu *mmu;
208
-
struct msm_gem_address_space *aspace;
208
+
struct msm_gem_vm *vm;
209
209
u64 start, size;
210
210
211
211
mmu = msm_iommu_gpu_new(&pdev->dev, gpu, quirks);
···
224
224
start = max_t(u64, SZ_16M, geometry->aperture_start);
225
225
size = geometry->aperture_end - start + 1;
226
226
227
-
aspace = msm_gem_address_space_create(mmu, "gpu",
228
-
start & GENMASK_ULL(48, 0), size);
227
+
vm = msm_gem_vm_create(mmu, "gpu", start & GENMASK_ULL(48, 0), size);
229
228
230
-
if (IS_ERR(aspace) && !IS_ERR(mmu))
229
+
if (IS_ERR(vm) && !IS_ERR(mmu))
231
230
mmu->funcs->destroy(mmu);
232
231
233
-
return aspace;
232
+
return vm;
234
233
}
235
234
236
-
u64 adreno_private_address_space_size(struct msm_gpu *gpu)
235
+
u64 adreno_private_vm_size(struct msm_gpu *gpu)
237
236
{
238
237
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
239
238
struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
···
274
275
!READ_ONCE(gpu->crashstate)) {
275
276
priv->stall_enabled = true;
276
277
277
-
gpu->aspace->mmu->funcs->set_stall(gpu->aspace->mmu, true);
278
+
gpu->vm->mmu->funcs->set_stall(gpu->vm->mmu, true);
278
279
}
279
280
spin_unlock_irqrestore(&priv->fault_stall_lock, flags);
280
281
}
···
302
303
if (priv->stall_enabled) {
303
304
priv->stall_enabled = false;
304
305
305
-
gpu->aspace->mmu->funcs->set_stall(gpu->aspace->mmu, false);
306
+
gpu->vm->mmu->funcs->set_stall(gpu->vm->mmu, false);
306
307
}
308
+
307
309
priv->stall_reenable_time = ktime_add_ms(ktime_get(), 500);
308
310
spin_unlock_irqrestore(&priv->fault_stall_lock, irq_flags);
309
311
···
401
401
*value = 0;
402
402
return 0;
403
403
case MSM_PARAM_FAULTS:
404
-
if (ctx->aspace)
405
-
*value = gpu->global_faults + ctx->aspace->faults;
404
+
if (ctx->vm)
405
+
*value = gpu->global_faults + ctx->vm->faults;
406
406
else
407
407
*value = gpu->global_faults;
408
408
return 0;
···
410
410
*value = gpu->suspend_count;
411
411
return 0;
412
412
case MSM_PARAM_VA_START:
413
-
if (ctx->aspace == gpu->aspace)
413
+
if (ctx->vm == gpu->vm)
414
414
return UERR(EINVAL, drm, "requires per-process pgtables");
415
-
*value = ctx->aspace->va_start;
415
+
*value = ctx->vm->va_start;
416
416
return 0;
417
417
case MSM_PARAM_VA_SIZE:
418
-
if (ctx->aspace == gpu->aspace)
418
+
if (ctx->vm == gpu->vm)
419
419
return UERR(EINVAL, drm, "requires per-process pgtables");
420
-
*value = ctx->aspace->va_size;
420
+
*value = ctx->vm->va_size;
421
421
return 0;
422
422
case MSM_PARAM_HIGHEST_BANK_BIT:
423
423
*value = adreno_gpu->ubwc_config.highest_bank_bit;
···
607
607
void *ptr;
608
608
609
609
ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
610
-
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
610
+
MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->vm, &bo, iova);
611
611
612
612
if (IS_ERR(ptr))
613
613
return ERR_CAST(ptr);
+8
-8
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+8
-8
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
580
580
581
581
/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
582
582
#define ADRENO_VM_START 0x100000000ULL
583
-
u64 adreno_private_address_space_size(struct msm_gpu *gpu);
583
+
u64 adreno_private_vm_size(struct msm_gpu *gpu);
584
584
int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
585
585
uint32_t param, uint64_t *value, uint32_t *len);
586
586
int adreno_set_param(struct msm_gpu *gpu, struct msm_context *ctx,
···
623
623
* Common helper function to initialize the default address space for arm-smmu
624
624
* attached targets
625
625
*/
626
-
struct msm_gem_address_space *
627
-
adreno_create_address_space(struct msm_gpu *gpu,
628
-
struct platform_device *pdev);
626
+
struct msm_gem_vm *
627
+
adreno_create_vm(struct msm_gpu *gpu,
628
+
struct platform_device *pdev);
629
629
630
-
struct msm_gem_address_space *
631
-
adreno_iommu_create_address_space(struct msm_gpu *gpu,
632
-
struct platform_device *pdev,
633
-
unsigned long quirks);
630
+
struct msm_gem_vm *
631
+
adreno_iommu_create_vm(struct msm_gpu *gpu,
632
+
struct platform_device *pdev,
633
+
unsigned long quirks);
634
634
635
635
int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
636
636
struct adreno_smmu_fault_info *info, const char *block,
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
···
563
563
struct drm_writeback_job *job)
564
564
{
565
565
const struct msm_format *format;
566
-
struct msm_gem_address_space *aspace;
566
+
struct msm_gem_vm *vm;
567
567
struct dpu_hw_wb_cfg *wb_cfg;
568
568
int ret;
569
569
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
···
573
573
574
574
wb_enc->wb_job = job;
575
575
wb_enc->wb_conn = job->connector;
576
-
aspace = phys_enc->dpu_kms->base.aspace;
576
+
vm = phys_enc->dpu_kms->base.vm;
577
577
578
578
wb_cfg = &wb_enc->wb_cfg;
579
579
580
580
memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
581
581
582
-
ret = msm_framebuffer_prepare(job->fb, aspace, false);
582
+
ret = msm_framebuffer_prepare(job->fb, vm, false);
583
583
if (ret) {
584
584
DPU_ERROR("prep fb failed, %d\n", ret);
585
585
return;
···
593
593
return;
594
594
}
595
595
596
-
dpu_format_populate_addrs(aspace, job->fb, &wb_cfg->dest);
596
+
dpu_format_populate_addrs(vm, job->fb, &wb_cfg->dest);
597
597
598
598
wb_cfg->dest.width = job->fb->width;
599
599
wb_cfg->dest.height = job->fb->height;
···
616
616
struct drm_writeback_job *job)
617
617
{
618
618
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
619
-
struct msm_gem_address_space *aspace;
619
+
struct msm_gem_vm *vm;
620
620
621
621
if (!job->fb)
622
622
return;
623
623
624
-
aspace = phys_enc->dpu_kms->base.aspace;
624
+
vm = phys_enc->dpu_kms->base.vm;
625
625
626
-
msm_framebuffer_cleanup(job->fb, aspace, false);
626
+
msm_framebuffer_cleanup(job->fb, vm, false);
627
627
wb_enc->wb_job = NULL;
628
628
wb_enc->wb_conn = NULL;
629
629
}
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
···
274
274
return _dpu_format_populate_plane_sizes_linear(fmt, fb, layout);
275
275
}
276
276
277
-
static void _dpu_format_populate_addrs_ubwc(struct msm_gem_address_space *aspace,
277
+
static void _dpu_format_populate_addrs_ubwc(struct msm_gem_vm *vm,
278
278
struct drm_framebuffer *fb,
279
279
struct dpu_hw_fmt_layout *layout)
280
280
{
···
282
282
uint32_t base_addr = 0;
283
283
bool meta;
284
284
285
-
base_addr = msm_framebuffer_iova(fb, aspace, 0);
285
+
base_addr = msm_framebuffer_iova(fb, vm, 0);
286
286
287
287
fmt = msm_framebuffer_format(fb);
288
288
meta = MSM_FORMAT_IS_UBWC(fmt);
···
355
355
}
356
356
}
357
357
358
-
static void _dpu_format_populate_addrs_linear(struct msm_gem_address_space *aspace,
358
+
static void _dpu_format_populate_addrs_linear(struct msm_gem_vm *vm,
359
359
struct drm_framebuffer *fb,
360
360
struct dpu_hw_fmt_layout *layout)
361
361
{
···
363
363
364
364
/* Populate addresses for simple formats here */
365
365
for (i = 0; i < layout->num_planes; ++i)
366
-
layout->plane_addr[i] = msm_framebuffer_iova(fb, aspace, i);
367
-
}
366
+
layout->plane_addr[i] = msm_framebuffer_iova(fb, vm, i);
367
+
}
368
368
369
369
/**
370
370
* dpu_format_populate_addrs - populate buffer addresses based on
371
371
* mmu, fb, and format found in the fb
372
-
* @aspace: address space pointer
372
+
* @vm: address space pointer
373
373
* @fb: framebuffer pointer
374
374
* @layout: format layout structure to populate
375
375
*/
376
-
void dpu_format_populate_addrs(struct msm_gem_address_space *aspace,
376
+
void dpu_format_populate_addrs(struct msm_gem_vm *vm,
377
377
struct drm_framebuffer *fb,
378
378
struct dpu_hw_fmt_layout *layout)
379
379
{
···
384
384
/* Populate the addresses given the fb */
385
385
if (MSM_FORMAT_IS_UBWC(fmt) ||
386
386
MSM_FORMAT_IS_TILE(fmt))
387
-
_dpu_format_populate_addrs_ubwc(aspace, fb, layout);
387
+
_dpu_format_populate_addrs_ubwc(vm, fb, layout);
388
388
else
389
-
_dpu_format_populate_addrs_linear(aspace, fb, layout);
389
+
_dpu_format_populate_addrs_linear(vm, fb, layout);
390
390
}
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
1095
1095
{
1096
1096
struct msm_mmu *mmu;
1097
1097
1098
-
if (!dpu_kms->base.aspace)
1098
+
if (!dpu_kms->base.vm)
1099
1099
return;
1100
1100
1101
-
mmu = dpu_kms->base.aspace->mmu;
1101
+
mmu = dpu_kms->base.vm->mmu;
1102
1102
1103
1103
mmu->funcs->detach(mmu);
1104
-
msm_gem_address_space_put(dpu_kms->base.aspace);
1104
+
msm_gem_vm_put(dpu_kms->base.vm);
1105
1105
1106
-
dpu_kms->base.aspace = NULL;
1106
+
dpu_kms->base.vm = NULL;
1107
1107
}
1108
1108
1109
1109
static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
1110
1110
{
1111
-
struct msm_gem_address_space *aspace;
1111
+
struct msm_gem_vm *vm;
1112
1112
1113
-
aspace = msm_kms_init_aspace(dpu_kms->dev);
1114
-
if (IS_ERR(aspace))
1115
-
return PTR_ERR(aspace);
1113
+
vm = msm_kms_init_vm(dpu_kms->dev);
1114
+
if (IS_ERR(vm))
1115
+
return PTR_ERR(vm);
1116
1116
1117
-
dpu_kms->base.aspace = aspace;
1117
+
dpu_kms->base.vm = vm;
1118
1118
1119
1119
return 0;
1120
1120
}
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+7
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
···
71
71
72
72
/*
73
73
* struct dpu_plane - local dpu plane structure
74
-
* @aspace: address space pointer
74
+
* @vm: address space pointer
75
75
* @csc_ptr: Points to dpu_csc_cfg structure to use for current
76
76
* @catalog: Points to dpu catalog structure
77
77
* @revalidate: force revalidation of all the plane properties
···
654
654
655
655
DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
656
656
657
-
/* cache aspace */
658
-
pstate->aspace = kms->base.aspace;
657
+
/* cache vm */
658
+
pstate->vm = kms->base.vm;
659
659
660
660
/*
661
661
* TODO: Need to sort out the msm_framebuffer_prepare() call below so
···
664
664
*/
665
665
drm_gem_plane_helper_prepare_fb(plane, new_state);
666
666
667
-
if (pstate->aspace) {
667
+
if (pstate->vm) {
668
668
ret = msm_framebuffer_prepare(new_state->fb,
669
-
pstate->aspace, pstate->needs_dirtyfb);
669
+
pstate->vm, pstate->needs_dirtyfb);
670
670
if (ret) {
671
671
DPU_ERROR("failed to prepare framebuffer\n");
672
672
return ret;
···
689
689
690
690
DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
691
691
692
-
msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace,
692
+
msm_framebuffer_cleanup(old_state->fb, old_pstate->vm,
693
693
old_pstate->needs_dirtyfb);
694
694
}
695
695
···
1457
1457
pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
1458
1458
pdpu->is_rt_pipe = is_rt_pipe;
1459
1459
1460
-
dpu_format_populate_addrs(pstate->aspace, new_state->fb, &pstate->layout);
1460
+
dpu_format_populate_addrs(pstate->vm, new_state->fb, &pstate->layout);
1461
1461
1462
1462
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1463
1463
", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
···
17
17
/**
18
18
* struct dpu_plane_state: Define dpu extension of drm plane state object
19
19
* @base: base drm plane state object
20
-
* @aspace: pointer to address space for input/output buffers
20
+
* @vm: pointer to address space for input/output buffers
21
21
* @pipe: software pipe description
22
22
* @r_pipe: software pipe description of the second pipe
23
23
* @pipe_cfg: software pipe configuration
···
34
34
*/
35
35
struct dpu_plane_state {
36
36
struct drm_plane_state base;
37
-
struct msm_gem_address_space *aspace;
37
+
struct msm_gem_vm *vm;
38
38
struct dpu_sw_pipe pipe;
39
39
struct dpu_sw_pipe r_pipe;
40
40
struct dpu_sw_pipe_cfg pipe_cfg;
+3
-3
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+3
-3
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
···
120
120
struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
121
121
struct msm_kms *kms = &mdp4_kms->base.base;
122
122
123
-
msm_gem_unpin_iova(val, kms->aspace);
123
+
msm_gem_unpin_iova(val, kms->vm);
124
124
drm_gem_object_put(val);
125
125
}
126
126
···
369
369
if (next_bo) {
370
370
/* take a obj ref + iova ref when we start scanning out: */
371
371
drm_gem_object_get(next_bo);
372
-
msm_gem_get_and_pin_iova(next_bo, kms->aspace, &iova);
372
+
msm_gem_get_and_pin_iova(next_bo, kms->vm, &iova);
373
373
374
374
/* enable cursor: */
375
375
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
···
427
427
}
428
428
429
429
if (cursor_bo) {
430
-
ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, &iova);
430
+
ret = msm_gem_get_and_pin_iova(cursor_bo, kms->vm, &iova);
431
431
if (ret)
432
432
goto fail;
433
433
} else {
+12
-12
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+12
-12
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
···
122
122
{
123
123
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
124
124
struct device *dev = mdp4_kms->dev->dev;
125
-
struct msm_gem_address_space *aspace = kms->aspace;
125
+
struct msm_gem_vm *vm = kms->vm;
126
126
127
127
if (mdp4_kms->blank_cursor_iova)
128
-
msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
128
+
msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->vm);
129
129
drm_gem_object_put(mdp4_kms->blank_cursor_bo);
130
130
131
-
if (aspace) {
132
-
aspace->mmu->funcs->detach(aspace->mmu);
133
-
msm_gem_address_space_put(aspace);
131
+
if (vm) {
132
+
vm->mmu->funcs->detach(vm->mmu);
133
+
msm_gem_vm_put(vm);
134
134
}
135
135
136
136
if (mdp4_kms->rpm_enabled)
···
398
398
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms));
399
399
struct msm_kms *kms = NULL;
400
400
struct msm_mmu *mmu;
401
-
struct msm_gem_address_space *aspace;
401
+
struct msm_gem_vm *vm;
402
402
int ret;
403
403
u32 major, minor;
404
404
unsigned long max_clk;
···
467
467
} else if (!mmu) {
468
468
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
469
469
"contig buffers for scanout\n");
470
-
aspace = NULL;
470
+
vm = NULL;
471
471
} else {
472
-
aspace = msm_gem_address_space_create(mmu,
472
+
vm = msm_gem_vm_create(mmu,
473
473
"mdp4", 0x1000, 0x100000000 - 0x1000);
474
474
475
-
if (IS_ERR(aspace)) {
475
+
if (IS_ERR(vm)) {
476
476
if (!IS_ERR(mmu))
477
477
mmu->funcs->destroy(mmu);
478
-
ret = PTR_ERR(aspace);
478
+
ret = PTR_ERR(vm);
479
479
goto fail;
480
480
}
481
481
482
-
kms->aspace = aspace;
482
+
kms->vm = vm;
483
483
}
484
484
485
485
ret = modeset_init(mdp4_kms);
···
496
496
goto fail;
497
497
}
498
498
499
-
ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
499
+
ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->vm,
500
500
&mdp4_kms->blank_cursor_iova);
501
501
if (ret) {
502
502
DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
+6
-6
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+6
-6
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
···
87
87
88
88
drm_gem_plane_helper_prepare_fb(plane, new_state);
89
89
90
-
return msm_framebuffer_prepare(new_state->fb, kms->aspace, false);
90
+
return msm_framebuffer_prepare(new_state->fb, kms->vm, false);
91
91
}
92
92
93
93
static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
···
102
102
return;
103
103
104
104
DBG("%s: cleanup: FB[%u]", mdp4_plane->name, fb->base.id);
105
-
msm_framebuffer_cleanup(fb, kms->aspace, false);
105
+
msm_framebuffer_cleanup(fb, kms->vm, false);
106
106
}
107
107
108
108
···
153
153
MDP4_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
154
154
155
155
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
156
-
msm_framebuffer_iova(fb, kms->aspace, 0));
156
+
msm_framebuffer_iova(fb, kms->vm, 0));
157
157
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
158
-
msm_framebuffer_iova(fb, kms->aspace, 1));
158
+
msm_framebuffer_iova(fb, kms->vm, 1));
159
159
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
160
-
msm_framebuffer_iova(fb, kms->aspace, 2));
160
+
msm_framebuffer_iova(fb, kms->vm, 2));
161
161
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
162
-
msm_framebuffer_iova(fb, kms->aspace, 3));
162
+
msm_framebuffer_iova(fb, kms->vm, 3));
163
163
}
164
164
165
165
static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
···
169
169
struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
170
170
struct msm_kms *kms = &mdp5_kms->base.base;
171
171
172
-
msm_gem_unpin_iova(val, kms->aspace);
172
+
msm_gem_unpin_iova(val, kms->vm);
173
173
drm_gem_object_put(val);
174
174
}
175
175
···
993
993
if (!cursor_bo)
994
994
return -ENOENT;
995
995
996
-
ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace,
996
+
ret = msm_gem_get_and_pin_iova(cursor_bo, kms->vm,
997
997
&mdp5_crtc->cursor.iova);
998
998
if (ret) {
999
999
drm_gem_object_put(cursor_bo);
+9
-9
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+9
-9
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
···
198
198
static void mdp5_kms_destroy(struct msm_kms *kms)
199
199
{
200
200
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
201
-
struct msm_gem_address_space *aspace = kms->aspace;
201
+
struct msm_gem_vm *vm = kms->vm;
202
202
203
-
if (aspace) {
204
-
aspace->mmu->funcs->detach(aspace->mmu);
205
-
msm_gem_address_space_put(aspace);
203
+
if (vm) {
204
+
vm->mmu->funcs->detach(vm->mmu);
205
+
msm_gem_vm_put(vm);
206
206
}
207
207
208
208
mdp_kms_destroy(&mdp5_kms->base);
···
500
500
struct mdp5_kms *mdp5_kms;
501
501
struct mdp5_cfg *config;
502
502
struct msm_kms *kms = priv->kms;
503
-
struct msm_gem_address_space *aspace;
503
+
struct msm_gem_vm *vm;
504
504
int i, ret;
505
505
506
506
ret = mdp5_init(to_platform_device(dev->dev), dev);
···
534
534
}
535
535
mdelay(16);
536
536
537
-
aspace = msm_kms_init_aspace(mdp5_kms->dev);
538
-
if (IS_ERR(aspace)) {
539
-
ret = PTR_ERR(aspace);
537
+
vm = msm_kms_init_vm(mdp5_kms->dev);
538
+
if (IS_ERR(vm)) {
539
+
ret = PTR_ERR(vm);
540
540
goto fail;
541
541
}
542
542
543
-
kms->aspace = aspace;
543
+
kms->vm = vm;
544
544
545
545
pm_runtime_put_sync(&pdev->dev);
546
546
+6
-6
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+6
-6
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
···
144
144
145
145
drm_gem_plane_helper_prepare_fb(plane, new_state);
146
146
147
-
return msm_framebuffer_prepare(new_state->fb, kms->aspace, needs_dirtyfb);
147
+
return msm_framebuffer_prepare(new_state->fb, kms->vm, needs_dirtyfb);
148
148
}
149
149
150
150
static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
···
159
159
return;
160
160
161
161
DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
162
-
msm_framebuffer_cleanup(fb, kms->aspace, needed_dirtyfb);
162
+
msm_framebuffer_cleanup(fb, kms->vm, needed_dirtyfb);
163
163
}
164
164
165
165
static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
···
478
478
MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
479
479
480
480
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
481
-
msm_framebuffer_iova(fb, kms->aspace, 0));
481
+
msm_framebuffer_iova(fb, kms->vm, 0));
482
482
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
483
-
msm_framebuffer_iova(fb, kms->aspace, 1));
483
+
msm_framebuffer_iova(fb, kms->vm, 1));
484
484
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
485
-
msm_framebuffer_iova(fb, kms->aspace, 2));
485
+
msm_framebuffer_iova(fb, kms->vm, 2));
486
486
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
487
-
msm_framebuffer_iova(fb, kms->aspace, 3));
487
+
msm_framebuffer_iova(fb, kms->vm, 3));
488
488
}
489
489
490
490
/* Note: mdp5_plane->pipe_lock must be locked */
+7
-7
drivers/gpu/drm/msm/dsi/dsi_host.c
+7
-7
drivers/gpu/drm/msm/dsi/dsi_host.c
···
152
152
153
153
/* DSI 6G TX buffer*/
154
154
struct drm_gem_object *tx_gem_obj;
155
-
struct msm_gem_address_space *aspace;
155
+
struct msm_gem_vm *vm;
156
156
157
157
/* DSI v2 TX buffer */
158
158
void *tx_buf;
···
1207
1207
uint64_t iova;
1208
1208
u8 *data;
1209
1209
1210
-
msm_host->aspace = msm_gem_address_space_get(priv->kms->aspace);
1210
+
msm_host->vm = msm_gem_vm_get(priv->kms->vm);
1211
1211
1212
1212
data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1213
-
msm_host->aspace,
1213
+
msm_host->vm,
1214
1214
&msm_host->tx_gem_obj, &iova);
1215
1215
1216
1216
if (IS_ERR(data)) {
···
1254
1254
return;
1255
1255
1256
1256
if (msm_host->tx_gem_obj) {
1257
-
msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->aspace);
1258
-
msm_gem_address_space_put(msm_host->aspace);
1257
+
msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm);
1258
+
msm_gem_vm_put(msm_host->vm);
1259
1259
msm_host->tx_gem_obj = NULL;
1260
-
msm_host->aspace = NULL;
1260
+
msm_host->vm = NULL;
1261
1261
}
1262
1262
1263
1263
if (msm_host->tx_buf)
···
1388
1388
return -EINVAL;
1389
1389
1390
1390
return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1391
-
priv->kms->aspace, dma_base);
1391
+
priv->kms->vm, dma_base);
1392
1392
}
1393
1393
1394
1394
int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
+4
-4
drivers/gpu/drm/msm/msm_drv.c
+4
-4
drivers/gpu/drm/msm/msm_drv.c
···
349
349
kref_init(&ctx->ref);
350
350
msm_submitqueue_init(dev, ctx);
351
351
352
-
ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
352
+
ctx->vm = msm_gpu_create_private_vm(priv->gpu, current);
353
353
file->driver_priv = ctx;
354
354
355
355
ctx->seqno = atomic_inc_return(&ident);
···
527
527
* Don't pin the memory here - just get an address so that userspace can
528
528
* be productive
529
529
*/
530
-
return msm_gem_get_iova(obj, ctx->aspace, iova);
530
+
return msm_gem_get_iova(obj, ctx->vm, iova);
531
531
}
532
532
533
533
static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
···
541
541
return -EINVAL;
542
542
543
543
/* Only supported if per-process address space is supported: */
544
-
if (priv->gpu->aspace == ctx->aspace)
544
+
if (priv->gpu->vm == ctx->vm)
545
545
return UERR(EOPNOTSUPP, dev, "requires per-process pgtables");
546
546
547
547
if (should_fail(&fail_gem_iova, obj->size))
548
548
return -ENOMEM;
549
549
550
-
return msm_gem_set_iova(obj, ctx->aspace, iova);
550
+
return msm_gem_set_iova(obj, ctx->vm, iova);
551
551
}
552
552
553
553
static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,
+5
-5
drivers/gpu/drm/msm/msm_drv.h
+5
-5
drivers/gpu/drm/msm/msm_drv.h
···
48
48
struct msm_perf_state;
49
49
struct msm_gem_submit;
50
50
struct msm_fence_context;
51
-
struct msm_gem_address_space;
51
+
struct msm_gem_vm;
52
52
struct msm_gem_vma;
53
53
struct msm_disp_state;
54
54
···
264
264
int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
265
265
void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
266
266
267
-
struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
267
+
struct msm_gem_vm *msm_kms_init_vm(struct drm_device *dev);
268
268
bool msm_use_mmu(struct drm_device *dev);
269
269
270
270
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
···
286
286
void msm_gem_prime_unpin(struct drm_gem_object *obj);
287
287
288
288
int msm_framebuffer_prepare(struct drm_framebuffer *fb,
289
-
struct msm_gem_address_space *aspace, bool needs_dirtyfb);
289
+
struct msm_gem_vm *vm, bool needs_dirtyfb);
290
290
void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
291
-
struct msm_gem_address_space *aspace, bool needed_dirtyfb);
291
+
struct msm_gem_vm *vm, bool needed_dirtyfb);
292
292
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
293
-
struct msm_gem_address_space *aspace, int plane);
293
+
struct msm_gem_vm *vm, int plane);
294
294
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
295
295
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
296
296
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
+5
-5
drivers/gpu/drm/msm/msm_fb.c
+5
-5
drivers/gpu/drm/msm/msm_fb.c
···
76
76
/* prepare/pin all the fb's bo's for scanout.
77
77
*/
78
78
int msm_framebuffer_prepare(struct drm_framebuffer *fb,
79
-
struct msm_gem_address_space *aspace,
79
+
struct msm_gem_vm *vm,
80
80
bool needs_dirtyfb)
81
81
{
82
82
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
···
88
88
atomic_inc(&msm_fb->prepare_count);
89
89
90
90
for (i = 0; i < n; i++) {
91
-
ret = msm_gem_get_and_pin_iova(fb->obj[i], aspace, &msm_fb->iova[i]);
91
+
ret = msm_gem_get_and_pin_iova(fb->obj[i], vm, &msm_fb->iova[i]);
92
92
drm_dbg_state(fb->dev, "FB[%u]: iova[%d]: %08llx (%d)\n",
93
93
fb->base.id, i, msm_fb->iova[i], ret);
94
94
if (ret)
···
99
99
}
100
100
101
101
void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
102
-
struct msm_gem_address_space *aspace,
102
+
struct msm_gem_vm *vm,
103
103
bool needed_dirtyfb)
104
104
{
105
105
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
···
109
109
refcount_dec(&msm_fb->dirtyfb);
110
110
111
111
for (i = 0; i < n; i++)
112
-
msm_gem_unpin_iova(fb->obj[i], aspace);
112
+
msm_gem_unpin_iova(fb->obj[i], vm);
113
113
114
114
if (!atomic_dec_return(&msm_fb->prepare_count))
115
115
memset(msm_fb->iova, 0, sizeof(msm_fb->iova));
116
116
}
117
117
118
118
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
119
-
struct msm_gem_address_space *aspace, int plane)
119
+
struct msm_gem_vm *vm, int plane)
120
120
{
121
121
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
122
122
return msm_fb->iova[plane] + fb->offsets[plane];
+1
-1
drivers/gpu/drm/msm/msm_fbdev.c
+1
-1
drivers/gpu/drm/msm/msm_fbdev.c
···
122
122
* in panic (ie. lock-safe, etc) we could avoid pinning the
123
123
* buffer now:
124
124
*/
125
-
ret = msm_gem_get_and_pin_iova(bo, priv->kms->aspace, &paddr);
125
+
ret = msm_gem_get_and_pin_iova(bo, priv->kms->vm, &paddr);
126
126
if (ret) {
127
127
DRM_DEV_ERROR(dev->dev, "failed to get buffer obj iova: %d\n", ret);
128
128
goto fail;
+37
-37
drivers/gpu/drm/msm/msm_gem.c
+37
-37
drivers/gpu/drm/msm/msm_gem.c
···
398
398
}
399
399
400
400
static struct msm_gem_vma *add_vma(struct drm_gem_object *obj,
401
-
struct msm_gem_address_space *aspace)
401
+
struct msm_gem_vm *vm)
402
402
{
403
403
struct msm_gem_object *msm_obj = to_msm_bo(obj);
404
404
struct msm_gem_vma *vma;
405
405
406
406
msm_gem_assert_locked(obj);
407
407
408
-
vma = msm_gem_vma_new(aspace);
408
+
vma = msm_gem_vma_new(vm);
409
409
if (!vma)
410
410
return ERR_PTR(-ENOMEM);
411
411
···
415
415
}
416
416
417
417
static struct msm_gem_vma *lookup_vma(struct drm_gem_object *obj,
418
-
struct msm_gem_address_space *aspace)
418
+
struct msm_gem_vm *vm)
419
419
{
420
420
struct msm_gem_object *msm_obj = to_msm_bo(obj);
421
421
struct msm_gem_vma *vma;
···
423
423
msm_gem_assert_locked(obj);
424
424
425
425
list_for_each_entry(vma, &msm_obj->vmas, list) {
426
-
if (vma->aspace == aspace)
426
+
if (vma->vm == vm)
427
427
return vma;
428
428
}
429
429
···
454
454
msm_gem_assert_locked(obj);
455
455
456
456
list_for_each_entry(vma, &msm_obj->vmas, list) {
457
-
if (vma->aspace) {
457
+
if (vma->vm) {
458
458
msm_gem_vma_purge(vma);
459
459
if (close)
460
460
msm_gem_vma_close(vma);
···
477
477
}
478
478
479
479
static struct msm_gem_vma *get_vma_locked(struct drm_gem_object *obj,
480
-
struct msm_gem_address_space *aspace,
480
+
struct msm_gem_vm *vm,
481
481
u64 range_start, u64 range_end)
482
482
{
483
483
struct msm_gem_vma *vma;
484
484
485
485
msm_gem_assert_locked(obj);
486
486
487
-
vma = lookup_vma(obj, aspace);
487
+
vma = lookup_vma(obj, vm);
488
488
489
489
if (!vma) {
490
490
int ret;
491
491
492
-
vma = add_vma(obj, aspace);
492
+
vma = add_vma(obj, vm);
493
493
if (IS_ERR(vma))
494
494
return vma;
495
495
···
561
561
}
562
562
563
563
struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
564
-
struct msm_gem_address_space *aspace)
564
+
struct msm_gem_vm *vm)
565
565
{
566
-
return get_vma_locked(obj, aspace, 0, U64_MAX);
566
+
return get_vma_locked(obj, vm, 0, U64_MAX);
567
567
}
568
568
569
569
static int get_and_pin_iova_range_locked(struct drm_gem_object *obj,
570
-
struct msm_gem_address_space *aspace, uint64_t *iova,
570
+
struct msm_gem_vm *vm, uint64_t *iova,
571
571
u64 range_start, u64 range_end)
572
572
{
573
573
struct msm_gem_vma *vma;
···
575
575
576
576
msm_gem_assert_locked(obj);
577
577
578
-
vma = get_vma_locked(obj, aspace, range_start, range_end);
578
+
vma = get_vma_locked(obj, vm, range_start, range_end);
579
579
if (IS_ERR(vma))
580
580
return PTR_ERR(vma);
581
581
···
593
593
* limits iova to specified range (in pages)
594
594
*/
595
595
int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
596
-
struct msm_gem_address_space *aspace, uint64_t *iova,
596
+
struct msm_gem_vm *vm, uint64_t *iova,
597
597
u64 range_start, u64 range_end)
598
598
{
599
599
int ret;
600
600
601
601
msm_gem_lock(obj);
602
-
ret = get_and_pin_iova_range_locked(obj, aspace, iova, range_start, range_end);
602
+
ret = get_and_pin_iova_range_locked(obj, vm, iova, range_start, range_end);
603
603
msm_gem_unlock(obj);
604
604
605
605
return ret;
···
607
607
608
608
/* get iova and pin it. Should have a matching put */
609
609
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
610
-
struct msm_gem_address_space *aspace, uint64_t *iova)
610
+
struct msm_gem_vm *vm, uint64_t *iova)
611
611
{
612
-
return msm_gem_get_and_pin_iova_range(obj, aspace, iova, 0, U64_MAX);
612
+
return msm_gem_get_and_pin_iova_range(obj, vm, iova, 0, U64_MAX);
613
613
}
614
614
615
615
/*
···
617
617
* valid for the life of the object
618
618
*/
619
619
int msm_gem_get_iova(struct drm_gem_object *obj,
620
-
struct msm_gem_address_space *aspace, uint64_t *iova)
620
+
struct msm_gem_vm *vm, uint64_t *iova)
621
621
{
622
622
struct msm_gem_vma *vma;
623
623
int ret = 0;
624
624
625
625
msm_gem_lock(obj);
626
-
vma = get_vma_locked(obj, aspace, 0, U64_MAX);
626
+
vma = get_vma_locked(obj, vm, 0, U64_MAX);
627
627
if (IS_ERR(vma)) {
628
628
ret = PTR_ERR(vma);
629
629
} else {
···
635
635
}
636
636
637
637
static int clear_iova(struct drm_gem_object *obj,
638
-
struct msm_gem_address_space *aspace)
638
+
struct msm_gem_vm *vm)
639
639
{
640
-
struct msm_gem_vma *vma = lookup_vma(obj, aspace);
640
+
struct msm_gem_vma *vma = lookup_vma(obj, vm);
641
641
642
642
if (!vma)
643
643
return 0;
···
657
657
* Setting an iova of zero will clear the vma.
658
658
*/
659
659
int msm_gem_set_iova(struct drm_gem_object *obj,
660
-
struct msm_gem_address_space *aspace, uint64_t iova)
660
+
struct msm_gem_vm *vm, uint64_t iova)
661
661
{
662
662
int ret = 0;
663
663
664
664
msm_gem_lock(obj);
665
665
if (!iova) {
666
-
ret = clear_iova(obj, aspace);
666
+
ret = clear_iova(obj, vm);
667
667
} else {
668
668
struct msm_gem_vma *vma;
669
-
vma = get_vma_locked(obj, aspace, iova, iova + obj->size);
669
+
vma = get_vma_locked(obj, vm, iova, iova + obj->size);
670
670
if (IS_ERR(vma)) {
671
671
ret = PTR_ERR(vma);
672
672
} else if (GEM_WARN_ON(vma->iova != iova)) {
673
-
clear_iova(obj, aspace);
673
+
clear_iova(obj, vm);
674
674
ret = -EBUSY;
675
675
}
676
676
}
···
685
685
* to get rid of it
686
686
*/
687
687
void msm_gem_unpin_iova(struct drm_gem_object *obj,
688
-
struct msm_gem_address_space *aspace)
688
+
struct msm_gem_vm *vm)
689
689
{
690
690
struct msm_gem_vma *vma;
691
691
692
692
msm_gem_lock(obj);
693
-
vma = lookup_vma(obj, aspace);
693
+
vma = lookup_vma(obj, vm);
694
694
if (!GEM_WARN_ON(!vma)) {
695
695
msm_gem_unpin_locked(obj);
696
696
}
···
1008
1008
1009
1009
list_for_each_entry(vma, &msm_obj->vmas, list) {
1010
1010
const char *name, *comm;
1011
-
if (vma->aspace) {
1012
-
struct msm_gem_address_space *aspace = vma->aspace;
1011
+
if (vma->vm) {
1012
+
struct msm_gem_vm *vm = vma->vm;
1013
1013
struct task_struct *task =
1014
-
get_pid_task(aspace->pid, PIDTYPE_PID);
1014
+
get_pid_task(vm->pid, PIDTYPE_PID);
1015
1015
if (task) {
1016
1016
comm = kstrdup(task->comm, GFP_KERNEL);
1017
1017
put_task_struct(task);
1018
1018
} else {
1019
1019
comm = NULL;
1020
1020
}
1021
-
name = aspace->name;
1021
+
name = vm->name;
1022
1022
} else {
1023
1023
name = comm = NULL;
1024
1024
}
1025
-
seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s]",
1025
+
seq_printf(m, " [%s%s%s: vm=%p, %08llx,%s]",
1026
1026
name, comm ? ":" : "", comm ? comm : "",
1027
-
vma->aspace, vma->iova,
1027
+
vma->vm, vma->iova,
1028
1028
vma->mapped ? "mapped" : "unmapped");
1029
1029
kfree(comm);
1030
1030
}
···
1349
1349
}
1350
1350
1351
1351
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
1352
-
uint32_t flags, struct msm_gem_address_space *aspace,
1352
+
uint32_t flags, struct msm_gem_vm *vm,
1353
1353
struct drm_gem_object **bo, uint64_t *iova)
1354
1354
{
1355
1355
void *vaddr;
···
1360
1360
return ERR_CAST(obj);
1361
1361
1362
1362
if (iova) {
1363
-
ret = msm_gem_get_and_pin_iova(obj, aspace, iova);
1363
+
ret = msm_gem_get_and_pin_iova(obj, vm, iova);
1364
1364
if (ret)
1365
1365
goto err;
1366
1366
}
1367
1367
1368
1368
vaddr = msm_gem_get_vaddr(obj);
1369
1369
if (IS_ERR(vaddr)) {
1370
-
msm_gem_unpin_iova(obj, aspace);
1370
+
msm_gem_unpin_iova(obj, vm);
1371
1371
ret = PTR_ERR(vaddr);
1372
1372
goto err;
1373
1373
}
···
1384
1384
}
1385
1385
1386
1386
void msm_gem_kernel_put(struct drm_gem_object *bo,
1387
-
struct msm_gem_address_space *aspace)
1387
+
struct msm_gem_vm *vm)
1388
1388
{
1389
1389
if (IS_ERR_OR_NULL(bo))
1390
1390
return;
1391
1391
1392
1392
msm_gem_put_vaddr(bo);
1393
-
msm_gem_unpin_iova(bo, aspace);
1393
+
msm_gem_unpin_iova(bo, vm);
1394
1394
drm_gem_object_put(bo);
1395
1395
}
1396
1396
+17
-17
drivers/gpu/drm/msm/msm_gem.h
+17
-17
drivers/gpu/drm/msm/msm_gem.h
···
22
22
#define MSM_BO_STOLEN 0x10000000 /* try to use stolen/splash memory */
23
23
#define MSM_BO_MAP_PRIV 0x20000000 /* use IOMMU_PRIV when mapping */
24
24
25
-
struct msm_gem_address_space {
25
+
struct msm_gem_vm {
26
26
const char *name;
27
27
/* NOTE: mm managed at the page level, size is in # of pages
28
28
* and position mm_node->start is in # of pages:
···
47
47
uint64_t va_size;
48
48
};
49
49
50
-
struct msm_gem_address_space *
51
-
msm_gem_address_space_get(struct msm_gem_address_space *aspace);
50
+
struct msm_gem_vm *
51
+
msm_gem_vm_get(struct msm_gem_vm *vm);
52
52
53
-
void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
53
+
void msm_gem_vm_put(struct msm_gem_vm *vm);
54
54
55
-
struct msm_gem_address_space *
56
-
msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
55
+
struct msm_gem_vm *
56
+
msm_gem_vm_create(struct msm_mmu *mmu, const char *name,
57
57
u64 va_start, u64 size);
58
58
59
59
struct msm_fence_context;
···
61
61
struct msm_gem_vma {
62
62
struct drm_mm_node node;
63
63
uint64_t iova;
64
-
struct msm_gem_address_space *aspace;
64
+
struct msm_gem_vm *vm;
65
65
struct list_head list; /* node in msm_gem_object::vmas */
66
66
bool mapped;
67
67
};
68
68
69
-
struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_address_space *aspace);
69
+
struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_vm *vm);
70
70
int msm_gem_vma_init(struct msm_gem_vma *vma, int size,
71
71
u64 range_start, u64 range_end);
72
72
void msm_gem_vma_purge(struct msm_gem_vma *vma);
···
127
127
void msm_gem_unpin_locked(struct drm_gem_object *obj);
128
128
void msm_gem_unpin_active(struct drm_gem_object *obj);
129
129
struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj,
130
-
struct msm_gem_address_space *aspace);
130
+
struct msm_gem_vm *vm);
131
131
int msm_gem_get_iova(struct drm_gem_object *obj,
132
-
struct msm_gem_address_space *aspace, uint64_t *iova);
132
+
struct msm_gem_vm *vm, uint64_t *iova);
133
133
int msm_gem_set_iova(struct drm_gem_object *obj,
134
-
struct msm_gem_address_space *aspace, uint64_t iova);
134
+
struct msm_gem_vm *vm, uint64_t iova);
135
135
int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
136
-
struct msm_gem_address_space *aspace, uint64_t *iova,
136
+
struct msm_gem_vm *vm, uint64_t *iova,
137
137
u64 range_start, u64 range_end);
138
138
int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
139
-
struct msm_gem_address_space *aspace, uint64_t *iova);
139
+
struct msm_gem_vm *vm, uint64_t *iova);
140
140
void msm_gem_unpin_iova(struct drm_gem_object *obj,
141
-
struct msm_gem_address_space *aspace);
141
+
struct msm_gem_vm *vm);
142
142
void msm_gem_pin_obj_locked(struct drm_gem_object *obj);
143
143
struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj);
144
144
void msm_gem_unpin_pages_locked(struct drm_gem_object *obj);
···
160
160
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
161
161
uint32_t size, uint32_t flags);
162
162
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
163
-
uint32_t flags, struct msm_gem_address_space *aspace,
163
+
uint32_t flags, struct msm_gem_vm *vm,
164
164
struct drm_gem_object **bo, uint64_t *iova);
165
165
void msm_gem_kernel_put(struct drm_gem_object *bo,
166
-
struct msm_gem_address_space *aspace);
166
+
struct msm_gem_vm *vm);
167
167
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
168
168
struct dma_buf *dmabuf, struct sg_table *sgt);
169
169
__printf(2, 3)
···
257
257
struct kref ref;
258
258
struct drm_device *dev;
259
259
struct msm_gpu *gpu;
260
-
struct msm_gem_address_space *aspace;
260
+
struct msm_gem_vm *vm;
261
261
struct list_head node; /* node in ring submit list */
262
262
struct drm_exec exec;
263
263
uint32_t seqno; /* Sequence number of the submit on the ring */
+3
-3
drivers/gpu/drm/msm/msm_gem_submit.c
+3
-3
drivers/gpu/drm/msm/msm_gem_submit.c
···
64
64
65
65
kref_init(&submit->ref);
66
66
submit->dev = dev;
67
-
submit->aspace = queue->ctx->aspace;
67
+
submit->vm = queue->ctx->vm;
68
68
submit->gpu = gpu;
69
69
submit->cmd = (void *)&submit->bos[nr_bos];
70
70
submit->queue = queue;
···
312
312
struct msm_gem_vma *vma;
313
313
314
314
/* if locking succeeded, pin bo: */
315
-
vma = msm_gem_get_vma_locked(obj, submit->aspace);
315
+
vma = msm_gem_get_vma_locked(obj, submit->vm);
316
316
if (IS_ERR(vma)) {
317
317
ret = PTR_ERR(vma);
318
318
break;
···
670
670
if (args->pad)
671
671
return -EINVAL;
672
672
673
-
if (unlikely(!ctx->aspace) && !capable(CAP_SYS_RAWIO)) {
673
+
if (unlikely(!ctx->vm) && !capable(CAP_SYS_RAWIO)) {
674
674
DRM_ERROR_RATELIMITED("IOMMU support or CAP_SYS_RAWIO required!\n");
675
675
return -EPERM;
676
676
}
+45
-46
drivers/gpu/drm/msm/msm_gem_vma.c
+45
-46
drivers/gpu/drm/msm/msm_gem_vma.c
···
10
10
#include "msm_mmu.h"
11
11
12
12
static void
13
-
msm_gem_address_space_destroy(struct kref *kref)
13
+
msm_gem_vm_destroy(struct kref *kref)
14
14
{
15
-
struct msm_gem_address_space *aspace = container_of(kref,
16
-
struct msm_gem_address_space, kref);
15
+
struct msm_gem_vm *vm = container_of(kref, struct msm_gem_vm, kref);
17
16
18
-
drm_mm_takedown(&aspace->mm);
19
-
if (aspace->mmu)
20
-
aspace->mmu->funcs->destroy(aspace->mmu);
21
-
put_pid(aspace->pid);
22
-
kfree(aspace);
17
+
drm_mm_takedown(&vm->mm);
18
+
if (vm->mmu)
19
+
vm->mmu->funcs->destroy(vm->mmu);
20
+
put_pid(vm->pid);
21
+
kfree(vm);
23
22
}
24
23
25
24
26
-
void msm_gem_address_space_put(struct msm_gem_address_space *aspace)
25
+
void msm_gem_vm_put(struct msm_gem_vm *vm)
27
26
{
28
-
if (aspace)
29
-
kref_put(&aspace->kref, msm_gem_address_space_destroy);
27
+
if (vm)
28
+
kref_put(&vm->kref, msm_gem_vm_destroy);
30
29
}
31
30
32
-
struct msm_gem_address_space *
33
-
msm_gem_address_space_get(struct msm_gem_address_space *aspace)
31
+
struct msm_gem_vm *
32
+
msm_gem_vm_get(struct msm_gem_vm *vm)
34
33
{
35
-
if (!IS_ERR_OR_NULL(aspace))
36
-
kref_get(&aspace->kref);
34
+
if (!IS_ERR_OR_NULL(vm))
35
+
kref_get(&vm->kref);
37
36
38
-
return aspace;
37
+
return vm;
39
38
}
40
39
41
40
/* Actually unmap memory for the vma */
42
41
void msm_gem_vma_purge(struct msm_gem_vma *vma)
43
42
{
44
-
struct msm_gem_address_space *aspace = vma->aspace;
43
+
struct msm_gem_vm *vm = vma->vm;
45
44
unsigned size = vma->node.size;
46
45
47
46
/* Don't do anything if the memory isn't mapped */
48
47
if (!vma->mapped)
49
48
return;
50
49
51
-
aspace->mmu->funcs->unmap(aspace->mmu, vma->iova, size);
50
+
vm->mmu->funcs->unmap(vm->mmu, vma->iova, size);
52
51
53
52
vma->mapped = false;
54
53
}
···
57
58
msm_gem_vma_map(struct msm_gem_vma *vma, int prot,
58
59
struct sg_table *sgt, int size)
59
60
{
60
-
struct msm_gem_address_space *aspace = vma->aspace;
61
+
struct msm_gem_vm *vm = vma->vm;
61
62
int ret;
62
63
63
64
if (GEM_WARN_ON(!vma->iova))
···
68
69
69
70
vma->mapped = true;
70
71
71
-
if (!aspace)
72
+
if (!vm)
72
73
return 0;
73
74
74
75
/*
···
80
81
* Revisit this if we can come up with a scheme to pre-alloc pages
81
82
* for the pgtable in map/unmap ops.
82
83
*/
83
-
ret = aspace->mmu->funcs->map(aspace->mmu, vma->iova, sgt, size, prot);
84
+
ret = vm->mmu->funcs->map(vm->mmu, vma->iova, sgt, size, prot);
84
85
85
86
if (ret) {
86
87
vma->mapped = false;
···
92
93
/* Close an iova. Warn if it is still in use */
93
94
void msm_gem_vma_close(struct msm_gem_vma *vma)
94
95
{
95
-
struct msm_gem_address_space *aspace = vma->aspace;
96
+
struct msm_gem_vm *vm = vma->vm;
96
97
97
98
GEM_WARN_ON(vma->mapped);
98
99
99
-
spin_lock(&aspace->lock);
100
+
spin_lock(&vm->lock);
100
101
if (vma->iova)
101
102
drm_mm_remove_node(&vma->node);
102
-
spin_unlock(&aspace->lock);
103
+
spin_unlock(&vm->lock);
103
104
104
105
vma->iova = 0;
105
106
106
-
msm_gem_address_space_put(aspace);
107
+
msm_gem_vm_put(vm);
107
108
}
108
109
109
-
struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_address_space *aspace)
110
+
struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_vm *vm)
110
111
{
111
112
struct msm_gem_vma *vma;
112
113
···
114
115
if (!vma)
115
116
return NULL;
116
117
117
-
vma->aspace = aspace;
118
+
vma->vm = vm;
118
119
119
120
return vma;
120
121
}
···
123
124
int msm_gem_vma_init(struct msm_gem_vma *vma, int size,
124
125
u64 range_start, u64 range_end)
125
126
{
126
-
struct msm_gem_address_space *aspace = vma->aspace;
127
+
struct msm_gem_vm *vm = vma->vm;
127
128
int ret;
128
129
129
-
if (GEM_WARN_ON(!aspace))
130
+
if (GEM_WARN_ON(!vm))
130
131
return -EINVAL;
131
132
132
133
if (GEM_WARN_ON(vma->iova))
133
134
return -EBUSY;
134
135
135
-
spin_lock(&aspace->lock);
136
-
ret = drm_mm_insert_node_in_range(&aspace->mm, &vma->node,
136
+
spin_lock(&vm->lock);
137
+
ret = drm_mm_insert_node_in_range(&vm->mm, &vma->node,
137
138
size, PAGE_SIZE, 0,
138
139
range_start, range_end, 0);
139
-
spin_unlock(&aspace->lock);
140
+
spin_unlock(&vm->lock);
140
141
141
142
if (ret)
142
143
return ret;
···
144
145
vma->iova = vma->node.start;
145
146
vma->mapped = false;
146
147
147
-
kref_get(&aspace->kref);
148
+
kref_get(&vm->kref);
148
149
149
150
return 0;
150
151
}
151
152
152
-
struct msm_gem_address_space *
153
-
msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
153
+
struct msm_gem_vm *
154
+
msm_gem_vm_create(struct msm_mmu *mmu, const char *name,
154
155
u64 va_start, u64 size)
155
156
{
156
-
struct msm_gem_address_space *aspace;
157
+
struct msm_gem_vm *vm;
157
158
158
159
if (IS_ERR(mmu))
159
160
return ERR_CAST(mmu);
160
161
161
-
aspace = kzalloc(sizeof(*aspace), GFP_KERNEL);
162
-
if (!aspace)
162
+
vm = kzalloc(sizeof(*vm), GFP_KERNEL);
163
+
if (!vm)
163
164
return ERR_PTR(-ENOMEM);
164
165
165
-
spin_lock_init(&aspace->lock);
166
-
aspace->name = name;
167
-
aspace->mmu = mmu;
168
-
aspace->va_start = va_start;
169
-
aspace->va_size = size;
166
+
spin_lock_init(&vm->lock);
167
+
vm->name = name;
168
+
vm->mmu = mmu;
169
+
vm->va_start = va_start;
170
+
vm->va_size = size;
170
171
171
-
drm_mm_init(&aspace->mm, va_start, size);
172
+
drm_mm_init(&vm->mm, va_start, size);
172
173
173
-
kref_init(&aspace->kref);
174
+
kref_init(&vm->kref);
174
175
175
-
return aspace;
176
+
return vm;
176
177
}
+23
-23
drivers/gpu/drm/msm/msm_gpu.c
+23
-23
drivers/gpu/drm/msm/msm_gpu.c
···
285
285
286
286
if (state->fault_info.ttbr0) {
287
287
struct msm_gpu_fault_info *info = &state->fault_info;
288
-
struct msm_mmu *mmu = submit->aspace->mmu;
288
+
struct msm_mmu *mmu = submit->vm->mmu;
289
289
290
290
msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0,
291
291
&info->asid);
···
389
389
390
390
/* Increment the fault counts */
391
391
submit->queue->faults++;
392
-
if (submit->aspace)
393
-
submit->aspace->faults++;
392
+
if (submit->vm)
393
+
submit->vm->faults++;
394
394
395
395
get_comm_cmdline(submit, &comm, &cmd);
396
396
···
828
828
}
829
829
830
830
/* Return a new address space for a msm_drm_private instance */
831
-
struct msm_gem_address_space *
832
-
msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task)
831
+
struct msm_gem_vm *
832
+
msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task)
833
833
{
834
-
struct msm_gem_address_space *aspace = NULL;
834
+
struct msm_gem_vm *vm = NULL;
835
835
if (!gpu)
836
836
return NULL;
837
837
···
839
839
* If the target doesn't support private address spaces then return
840
840
* the global one
841
841
*/
842
-
if (gpu->funcs->create_private_address_space) {
843
-
aspace = gpu->funcs->create_private_address_space(gpu);
844
-
if (!IS_ERR(aspace))
845
-
aspace->pid = get_pid(task_pid(task));
842
+
if (gpu->funcs->create_private_vm) {
843
+
vm = gpu->funcs->create_private_vm(gpu);
844
+
if (!IS_ERR(vm))
845
+
vm->pid = get_pid(task_pid(task));
846
846
}
847
847
848
-
if (IS_ERR_OR_NULL(aspace))
849
-
aspace = msm_gem_address_space_get(gpu->aspace);
848
+
if (IS_ERR_OR_NULL(vm))
849
+
vm = msm_gem_vm_get(gpu->vm);
850
850
851
-
return aspace;
851
+
return vm;
852
852
}
853
853
854
854
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
···
943
943
msm_devfreq_init(gpu);
944
944
945
945
946
-
gpu->aspace = gpu->funcs->create_address_space(gpu, pdev);
946
+
gpu->vm = gpu->funcs->create_vm(gpu, pdev);
947
947
948
-
if (gpu->aspace == NULL)
948
+
if (gpu->vm == NULL)
949
949
DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
950
-
else if (IS_ERR(gpu->aspace)) {
951
-
ret = PTR_ERR(gpu->aspace);
950
+
else if (IS_ERR(gpu->vm)) {
951
+
ret = PTR_ERR(gpu->vm);
952
952
goto fail;
953
953
}
954
954
955
955
memptrs = msm_gem_kernel_new(drm,
956
956
sizeof(struct msm_rbmemptrs) * nr_rings,
957
-
check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo,
957
+
check_apriv(gpu, MSM_BO_WC), gpu->vm, &gpu->memptrs_bo,
958
958
&memptrs_iova);
959
959
960
960
if (IS_ERR(memptrs)) {
···
998
998
gpu->rb[i] = NULL;
999
999
}
1000
1000
1001
-
msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
1001
+
msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
1002
1002
1003
1003
platform_set_drvdata(pdev, NULL);
1004
1004
return ret;
···
1015
1015
gpu->rb[i] = NULL;
1016
1016
}
1017
1017
1018
-
msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
1018
+
msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
1019
1019
1020
-
if (!IS_ERR_OR_NULL(gpu->aspace)) {
1021
-
gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
1022
-
msm_gem_address_space_put(gpu->aspace);
1020
+
if (!IS_ERR_OR_NULL(gpu->vm)) {
1021
+
gpu->vm->mmu->funcs->detach(gpu->vm->mmu);
1022
+
msm_gem_vm_put(gpu->vm);
1023
1023
}
1024
1024
1025
1025
if (gpu->worker) {
+7
-9
drivers/gpu/drm/msm/msm_gpu.h
+7
-9
drivers/gpu/drm/msm/msm_gpu.h
···
78
78
/* note: gpu_set_freq() can assume that we have been pm_resumed */
79
79
void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
80
80
bool suspended);
81
-
struct msm_gem_address_space *(*create_address_space)
82
-
(struct msm_gpu *gpu, struct platform_device *pdev);
83
-
struct msm_gem_address_space *(*create_private_address_space)
84
-
(struct msm_gpu *gpu);
81
+
struct msm_gem_vm *(*create_vm)(struct msm_gpu *gpu, struct platform_device *pdev);
82
+
struct msm_gem_vm *(*create_private_vm)(struct msm_gpu *gpu);
85
83
uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
86
84
87
85
/**
···
234
236
void __iomem *mmio;
235
237
int irq;
236
238
237
-
struct msm_gem_address_space *aspace;
239
+
struct msm_gem_vm *vm;
238
240
239
241
/* Power Control: */
240
242
struct regulator *gpu_reg, *gpu_cx;
···
356
358
*/
357
359
int queueid;
358
360
359
-
/** @aspace: the per-process GPU address-space */
360
-
struct msm_gem_address_space *aspace;
361
+
/** @vm: the per-process GPU address-space */
362
+
struct msm_gem_vm *vm;
361
363
362
364
/** @kref: the reference count */
363
365
struct kref ref;
···
667
669
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
668
670
const char *name, struct msm_gpu_config *config);
669
671
670
-
struct msm_gem_address_space *
671
-
msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
672
+
struct msm_gem_vm *
673
+
msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task);
672
674
673
675
void msm_gpu_cleanup(struct msm_gpu *gpu);
674
676
+8
-8
drivers/gpu/drm/msm/msm_kms.c
+8
-8
drivers/gpu/drm/msm/msm_kms.c
···
176
176
return -ENOSYS;
177
177
}
178
178
179
-
struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
179
+
struct msm_gem_vm *msm_kms_init_vm(struct drm_device *dev)
180
180
{
181
-
struct msm_gem_address_space *aspace;
181
+
struct msm_gem_vm *vm;
182
182
struct msm_mmu *mmu;
183
183
struct device *mdp_dev = dev->dev;
184
184
struct device *mdss_dev = mdp_dev->parent;
···
204
204
return NULL;
205
205
}
206
206
207
-
aspace = msm_gem_address_space_create(mmu, "mdp_kms",
207
+
vm = msm_gem_vm_create(mmu, "mdp_kms",
208
208
0x1000, 0x100000000 - 0x1000);
209
-
if (IS_ERR(aspace)) {
210
-
dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
209
+
if (IS_ERR(vm)) {
210
+
dev_err(mdp_dev, "vm create, error %pe\n", vm);
211
211
mmu->funcs->destroy(mmu);
212
-
return aspace;
212
+
return vm;
213
213
}
214
214
215
-
msm_mmu_set_fault_handler(aspace->mmu, kms, msm_kms_fault_handler);
215
+
msm_mmu_set_fault_handler(vm->mmu, kms, msm_kms_fault_handler);
216
216
217
-
return aspace;
217
+
return vm;
218
218
}
219
219
220
220
void msm_drm_kms_uninit(struct device *dev)
+1
-1
drivers/gpu/drm/msm/msm_kms.h
+1
-1
drivers/gpu/drm/msm/msm_kms.h
+2
-2
drivers/gpu/drm/msm/msm_ringbuffer.c
+2
-2
drivers/gpu/drm/msm/msm_ringbuffer.c
···
84
84
85
85
ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
86
86
check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
87
-
gpu->aspace, &ring->bo, &ring->iova);
87
+
gpu->vm, &ring->bo, &ring->iova);
88
88
89
89
if (IS_ERR(ring->start)) {
90
90
ret = PTR_ERR(ring->start);
···
131
131
132
132
msm_fence_context_free(ring->fctx);
133
133
134
-
msm_gem_kernel_put(ring->bo, ring->gpu->aspace);
134
+
msm_gem_kernel_put(ring->bo, ring->gpu->vm);
135
135
136
136
kfree(ring);
137
137
}