Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
The way hw_onecell_data is declared:
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
};
makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.
Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
in order to finally get rid on the NR_CLKS define.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Neil Armstrong
and committed by
Jerome Brunet
05d3b7c6
5e4e4804
+424
-428
+1
drivers/clk/meson/Kconfig
+1
drivers/clk/meson/Kconfig
+423
-426
drivers/clk/meson/axg-audio.c
+423
-426
drivers/clk/meson/axg-audio.c
···
15
15
#include <linux/reset-controller.h>
16
16
#include <linux/slab.h>
17
17
18
+
#include "meson-clkc-utils.h"
18
19
#include "axg-audio.h"
19
20
#include "clk-regmap.h"
20
21
#include "clk-phase.h"
···
812
811
* Array of all clocks provided by this provider
813
812
* The input clocks of the controller will be populated at runtime
814
813
*/
815
-
static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
816
-
.hws = {
817
-
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
818
-
[AUD_CLKID_PDM] = &pdm.hw,
819
-
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
820
-
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
821
-
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
822
-
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
823
-
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
824
-
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
825
-
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
826
-
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
827
-
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
828
-
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
829
-
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
830
-
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
831
-
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
832
-
[AUD_CLKID_LOOPBACK] = &loopback.hw,
833
-
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
834
-
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
835
-
[AUD_CLKID_RESAMPLE] = &resample.hw,
836
-
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
837
-
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
838
-
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
839
-
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
840
-
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
841
-
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
842
-
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
843
-
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
844
-
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
845
-
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
846
-
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
847
-
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
848
-
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
849
-
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
850
-
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
851
-
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
852
-
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
853
-
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
854
-
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
855
-
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
856
-
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
857
-
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
858
-
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
859
-
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
860
-
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
861
-
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
862
-
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
863
-
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
864
-
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
865
-
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
866
-
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
867
-
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
868
-
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
869
-
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
870
-
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
871
-
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
872
-
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
873
-
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
874
-
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
875
-
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
876
-
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
877
-
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
878
-
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
879
-
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
880
-
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
881
-
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
882
-
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
883
-
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
884
-
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
885
-
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
886
-
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
887
-
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
888
-
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
889
-
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
890
-
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
891
-
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
892
-
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
893
-
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
894
-
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
895
-
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
896
-
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
897
-
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
898
-
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
899
-
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
900
-
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
901
-
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
902
-
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
903
-
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
904
-
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
905
-
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
906
-
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
907
-
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
908
-
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
909
-
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
910
-
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
911
-
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
912
-
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
913
-
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
914
-
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
915
-
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
916
-
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
917
-
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
918
-
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
919
-
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
920
-
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
921
-
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
922
-
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
923
-
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
924
-
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
925
-
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
926
-
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
927
-
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
928
-
[AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
929
-
[AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
930
-
[AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
931
-
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
932
-
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
933
-
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
934
-
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
935
-
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
936
-
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
937
-
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
938
-
[AUD_CLKID_TOP] = &axg_aud_top,
939
-
[NR_CLKS] = NULL,
940
-
},
941
-
.num = NR_CLKS,
814
+
static struct clk_hw *axg_audio_hw_clks[] = {
815
+
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
816
+
[AUD_CLKID_PDM] = &pdm.hw,
817
+
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
818
+
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
819
+
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
820
+
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
821
+
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
822
+
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
823
+
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
824
+
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
825
+
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
826
+
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
827
+
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
828
+
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
829
+
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
830
+
[AUD_CLKID_LOOPBACK] = &loopback.hw,
831
+
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
832
+
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
833
+
[AUD_CLKID_RESAMPLE] = &resample.hw,
834
+
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
835
+
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
836
+
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
837
+
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
838
+
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
839
+
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
840
+
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
841
+
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
842
+
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
843
+
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
844
+
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
845
+
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
846
+
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
847
+
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
848
+
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
849
+
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
850
+
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
851
+
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
852
+
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
853
+
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
854
+
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
855
+
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
856
+
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
857
+
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
858
+
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
859
+
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
860
+
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
861
+
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
862
+
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
863
+
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
864
+
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
865
+
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
866
+
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
867
+
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
868
+
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
869
+
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
870
+
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
871
+
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
872
+
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
873
+
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
874
+
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
875
+
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
876
+
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
877
+
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
878
+
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
879
+
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
880
+
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
881
+
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
882
+
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
883
+
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
884
+
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
885
+
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
886
+
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
887
+
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
888
+
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
889
+
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
890
+
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
891
+
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
892
+
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
893
+
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
894
+
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
895
+
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
896
+
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
897
+
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
898
+
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
899
+
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
900
+
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
901
+
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
902
+
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
903
+
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
904
+
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
905
+
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
906
+
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
907
+
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
908
+
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
909
+
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
910
+
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
911
+
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
912
+
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
913
+
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
914
+
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
915
+
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
916
+
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
917
+
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
918
+
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
919
+
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
920
+
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
921
+
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
922
+
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
923
+
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
924
+
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
925
+
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
926
+
[AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
927
+
[AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
928
+
[AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
929
+
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
930
+
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
931
+
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
932
+
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
933
+
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
934
+
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
935
+
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
936
+
[AUD_CLKID_TOP] = &axg_aud_top,
942
937
};
943
938
944
939
/*
945
940
* Array of all G12A clocks provided by this provider
946
941
* The input clocks of the controller will be populated at runtime
947
942
*/
948
-
static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
949
-
.hws = {
950
-
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
951
-
[AUD_CLKID_PDM] = &pdm.hw,
952
-
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
953
-
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
954
-
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
955
-
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
956
-
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
957
-
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
958
-
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
959
-
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
960
-
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
961
-
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
962
-
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
963
-
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
964
-
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
965
-
[AUD_CLKID_LOOPBACK] = &loopback.hw,
966
-
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
967
-
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
968
-
[AUD_CLKID_RESAMPLE] = &resample.hw,
969
-
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
970
-
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
971
-
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
972
-
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
973
-
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
974
-
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
975
-
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
976
-
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
977
-
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
978
-
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
979
-
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
980
-
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
981
-
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
982
-
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
983
-
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
984
-
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
985
-
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
986
-
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
987
-
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
988
-
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
989
-
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
990
-
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
991
-
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
992
-
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
993
-
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
994
-
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
995
-
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
996
-
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
997
-
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
998
-
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
999
-
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1000
-
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1001
-
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1002
-
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1003
-
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1004
-
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1005
-
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1006
-
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1007
-
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1008
-
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1009
-
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1010
-
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1011
-
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1012
-
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1013
-
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1014
-
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1015
-
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1016
-
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1017
-
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1018
-
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1019
-
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1020
-
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1021
-
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1022
-
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1023
-
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1024
-
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1025
-
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1026
-
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1027
-
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1028
-
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1029
-
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1030
-
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1031
-
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1032
-
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1033
-
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1034
-
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1035
-
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1036
-
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1037
-
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1038
-
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1039
-
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1040
-
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1041
-
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1042
-
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1043
-
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1044
-
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1045
-
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1046
-
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1047
-
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1048
-
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1049
-
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1050
-
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1051
-
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1052
-
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1053
-
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1054
-
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1055
-
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1056
-
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1057
-
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1058
-
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1059
-
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1060
-
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1061
-
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1062
-
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1063
-
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1064
-
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1065
-
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1066
-
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1067
-
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1068
-
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1069
-
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1070
-
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1071
-
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1072
-
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1073
-
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1074
-
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1075
-
[AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
1076
-
[AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
1077
-
[AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
1078
-
[AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
1079
-
[AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
1080
-
[AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
1081
-
[AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
1082
-
[AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
1083
-
[AUD_CLKID_TOP] = &axg_aud_top,
1084
-
[NR_CLKS] = NULL,
1085
-
},
1086
-
.num = NR_CLKS,
943
+
static struct clk_hw *g12a_audio_hw_clks[] = {
944
+
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
945
+
[AUD_CLKID_PDM] = &pdm.hw,
946
+
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
947
+
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
948
+
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
949
+
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
950
+
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
951
+
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
952
+
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
953
+
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
954
+
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
955
+
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
956
+
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
957
+
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
958
+
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
959
+
[AUD_CLKID_LOOPBACK] = &loopback.hw,
960
+
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
961
+
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
962
+
[AUD_CLKID_RESAMPLE] = &resample.hw,
963
+
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
964
+
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
965
+
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
966
+
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
967
+
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
968
+
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
969
+
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
970
+
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
971
+
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
972
+
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
973
+
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
974
+
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
975
+
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
976
+
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
977
+
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
978
+
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
979
+
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
980
+
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
981
+
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
982
+
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
983
+
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
984
+
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
985
+
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
986
+
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
987
+
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
988
+
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
989
+
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
990
+
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
991
+
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
992
+
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
993
+
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
994
+
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
995
+
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
996
+
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
997
+
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
998
+
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
999
+
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1000
+
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1001
+
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1002
+
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1003
+
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1004
+
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1005
+
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1006
+
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1007
+
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1008
+
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1009
+
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1010
+
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1011
+
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1012
+
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1013
+
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1014
+
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1015
+
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1016
+
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1017
+
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1018
+
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1019
+
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1020
+
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1021
+
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1022
+
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1023
+
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1024
+
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1025
+
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1026
+
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1027
+
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1028
+
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1029
+
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1030
+
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1031
+
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1032
+
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1033
+
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1034
+
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1035
+
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1036
+
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1037
+
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1038
+
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1039
+
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1040
+
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1041
+
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1042
+
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1043
+
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1044
+
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1045
+
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1046
+
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1047
+
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1048
+
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1049
+
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1050
+
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1051
+
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1052
+
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1053
+
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1054
+
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1055
+
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1056
+
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1057
+
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1058
+
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1059
+
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1060
+
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1061
+
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1062
+
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1063
+
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1064
+
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1065
+
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1066
+
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1067
+
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1068
+
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1069
+
[AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
1070
+
[AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
1071
+
[AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
1072
+
[AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
1073
+
[AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
1074
+
[AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
1075
+
[AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
1076
+
[AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
1077
+
[AUD_CLKID_TOP] = &axg_aud_top,
1087
1078
};
1088
1079
1089
1080
/*
1090
1081
* Array of all SM1 clocks provided by this provider
1091
1082
* The input clocks of the controller will be populated at runtime
1092
1083
*/
1093
-
static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
1094
-
.hws = {
1095
-
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
1096
-
[AUD_CLKID_PDM] = &pdm.hw,
1097
-
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
1098
-
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
1099
-
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
1100
-
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
1101
-
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
1102
-
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
1103
-
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
1104
-
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
1105
-
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
1106
-
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
1107
-
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
1108
-
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
1109
-
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
1110
-
[AUD_CLKID_LOOPBACK] = &loopback.hw,
1111
-
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
1112
-
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
1113
-
[AUD_CLKID_RESAMPLE] = &resample.hw,
1114
-
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
1115
-
[AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
1116
-
[AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
1117
-
[AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
1118
-
[AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
1119
-
[AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
1120
-
[AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
1121
-
[AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
1122
-
[AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
1123
-
[AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
1124
-
[AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
1125
-
[AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
1126
-
[AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
1127
-
[AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
1128
-
[AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
1129
-
[AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
1130
-
[AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
1131
-
[AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
1132
-
[AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
1133
-
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1134
-
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1135
-
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1136
-
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1137
-
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1138
-
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1139
-
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1140
-
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1141
-
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1142
-
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1143
-
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1144
-
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1145
-
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1146
-
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1147
-
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1148
-
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1149
-
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1150
-
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1151
-
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1152
-
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1153
-
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1154
-
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1155
-
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1156
-
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1157
-
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1158
-
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1159
-
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1160
-
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1161
-
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1162
-
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1163
-
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1164
-
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1165
-
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1166
-
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1167
-
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1168
-
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1169
-
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1170
-
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1171
-
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1172
-
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1173
-
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1174
-
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1175
-
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1176
-
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1177
-
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1178
-
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1179
-
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1180
-
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1181
-
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1182
-
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1183
-
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1184
-
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1185
-
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1186
-
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1187
-
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1188
-
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1189
-
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1190
-
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1191
-
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1192
-
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1193
-
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1194
-
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1195
-
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1196
-
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1197
-
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1198
-
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1199
-
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1200
-
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1201
-
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1202
-
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1203
-
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1204
-
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1205
-
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1206
-
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1207
-
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1208
-
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1209
-
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1210
-
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1211
-
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1212
-
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1213
-
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1214
-
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1215
-
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1216
-
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1217
-
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1218
-
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1219
-
[AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
1220
-
[AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
1221
-
[AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
1222
-
[AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
1223
-
[AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
1224
-
[AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
1225
-
[AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
1226
-
[AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
1227
-
[AUD_CLKID_TOP] = &sm1_aud_top.hw,
1228
-
[AUD_CLKID_TORAM] = &toram.hw,
1229
-
[AUD_CLKID_EQDRC] = &eqdrc.hw,
1230
-
[AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
1231
-
[AUD_CLKID_TOVAD] = &tovad.hw,
1232
-
[AUD_CLKID_LOCKER] = &locker.hw,
1233
-
[AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
1234
-
[AUD_CLKID_FRDDR_D] = &frddr_d.hw,
1235
-
[AUD_CLKID_TODDR_D] = &toddr_d.hw,
1236
-
[AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
1237
-
[AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
1238
-
[AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
1239
-
[AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
1240
-
[AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
1241
-
[AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
1242
-
[NR_CLKS] = NULL,
1243
-
},
1244
-
.num = NR_CLKS,
1084
+
static struct clk_hw *sm1_audio_hw_clks[] = {
1085
+
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
1086
+
[AUD_CLKID_PDM] = &pdm.hw,
1087
+
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
1088
+
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
1089
+
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
1090
+
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
1091
+
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
1092
+
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
1093
+
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
1094
+
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
1095
+
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
1096
+
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
1097
+
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
1098
+
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
1099
+
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
1100
+
[AUD_CLKID_LOOPBACK] = &loopback.hw,
1101
+
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
1102
+
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
1103
+
[AUD_CLKID_RESAMPLE] = &resample.hw,
1104
+
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
1105
+
[AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
1106
+
[AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
1107
+
[AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
1108
+
[AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
1109
+
[AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
1110
+
[AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
1111
+
[AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
1112
+
[AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
1113
+
[AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
1114
+
[AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
1115
+
[AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
1116
+
[AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
1117
+
[AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
1118
+
[AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
1119
+
[AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
1120
+
[AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
1121
+
[AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
1122
+
[AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
1123
+
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1124
+
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1125
+
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1126
+
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1127
+
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1128
+
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1129
+
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1130
+
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1131
+
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1132
+
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1133
+
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1134
+
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1135
+
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1136
+
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1137
+
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1138
+
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1139
+
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1140
+
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1141
+
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1142
+
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1143
+
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1144
+
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1145
+
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1146
+
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1147
+
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1148
+
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1149
+
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1150
+
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1151
+
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1152
+
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1153
+
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1154
+
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1155
+
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1156
+
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1157
+
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1158
+
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1159
+
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1160
+
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1161
+
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1162
+
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1163
+
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1164
+
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1165
+
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1166
+
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1167
+
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1168
+
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1169
+
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1170
+
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1171
+
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1172
+
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1173
+
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1174
+
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1175
+
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1176
+
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1177
+
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1178
+
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1179
+
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1180
+
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1181
+
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1182
+
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1183
+
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1184
+
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1185
+
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1186
+
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1187
+
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1188
+
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1189
+
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1190
+
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1191
+
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1192
+
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1193
+
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1194
+
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1195
+
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1196
+
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1197
+
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1198
+
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1199
+
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1200
+
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1201
+
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1202
+
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1203
+
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1204
+
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1205
+
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1206
+
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1207
+
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1208
+
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1209
+
[AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
1210
+
[AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
1211
+
[AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
1212
+
[AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
1213
+
[AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
1214
+
[AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
1215
+
[AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
1216
+
[AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
1217
+
[AUD_CLKID_TOP] = &sm1_aud_top.hw,
1218
+
[AUD_CLKID_TORAM] = &toram.hw,
1219
+
[AUD_CLKID_EQDRC] = &eqdrc.hw,
1220
+
[AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
1221
+
[AUD_CLKID_TOVAD] = &tovad.hw,
1222
+
[AUD_CLKID_LOCKER] = &locker.hw,
1223
+
[AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
1224
+
[AUD_CLKID_FRDDR_D] = &frddr_d.hw,
1225
+
[AUD_CLKID_TODDR_D] = &toddr_d.hw,
1226
+
[AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
1227
+
[AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
1228
+
[AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
1229
+
[AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
1230
+
[AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
1231
+
[AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
1245
1232
};
1246
1233
1247
1234
···
1734
1745
struct audioclk_data {
1735
1746
struct clk_regmap *const *regmap_clks;
1736
1747
unsigned int regmap_clk_num;
1737
-
struct clk_hw_onecell_data *hw_onecell_data;
1748
+
struct meson_clk_hw_data hw_clks;
1738
1749
unsigned int reset_offset;
1739
1750
unsigned int reset_num;
1740
1751
};
···
1780
1791
data->regmap_clks[i]->map = map;
1781
1792
1782
1793
/* Take care to skip the registered input clocks */
1783
-
for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
1794
+
for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
1784
1795
const char *name;
1785
1796
1786
-
hw = data->hw_onecell_data->hws[i];
1797
+
hw = data->hw_clks.hws[i];
1787
1798
/* array might be sparse */
1788
1799
if (!hw)
1789
1800
continue;
···
1797
1808
}
1798
1809
}
1799
1810
1800
-
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1801
-
data->hw_onecell_data);
1811
+
ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
1802
1812
if (ret)
1803
1813
return ret;
1804
1814
···
1822
1834
static const struct audioclk_data axg_audioclk_data = {
1823
1835
.regmap_clks = axg_clk_regmaps,
1824
1836
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1825
-
.hw_onecell_data = &axg_audio_hw_onecell_data,
1837
+
.hw_clks = {
1838
+
.hws = axg_audio_hw_clks,
1839
+
.num = ARRAY_SIZE(axg_audio_hw_clks),
1840
+
},
1826
1841
};
1827
1842
1828
1843
static const struct audioclk_data g12a_audioclk_data = {
1829
1844
.regmap_clks = g12a_clk_regmaps,
1830
1845
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
1831
-
.hw_onecell_data = &g12a_audio_hw_onecell_data,
1846
+
.hw_clks = {
1847
+
.hws = g12a_audio_hw_clks,
1848
+
.num = ARRAY_SIZE(g12a_audio_hw_clks),
1849
+
},
1832
1850
.reset_offset = AUDIO_SW_RESET,
1833
1851
.reset_num = 26,
1834
1852
};
···
1842
1848
static const struct audioclk_data sm1_audioclk_data = {
1843
1849
.regmap_clks = sm1_clk_regmaps,
1844
1850
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1845
-
.hw_onecell_data = &sm1_audio_hw_onecell_data,
1851
+
.hw_clks = {
1852
+
.hws = sm1_audio_hw_clks,
1853
+
.num = ARRAY_SIZE(sm1_audio_hw_clks),
1854
+
},
1846
1855
.reset_offset = AUDIO_SM1_SW_RESET0,
1847
1856
.reset_num = 39,
1848
1857
};