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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
reset: add polarfire soc reset support
Add support for the resets on Microchip's PolarFire SoC (MPFS).
Reset control is a single register, wedged in between registers for
clock control. To fit with existed DT etc, the reset controller is
created using the aux device framework & set up in the clock driver.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
authored by
Conor Dooley
and committed by
Claudiu Beznea
05f9e363
b56bae2d
+165
-1
+7
drivers/reset/Kconfig
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drivers/reset/Kconfig
···
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help
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This enables the reset driver for ImgTec Pistachio SoCs.
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config RESET_POLARFIRE_SOC
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bool "Microchip PolarFire SoC (MPFS) Reset Driver"
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depends on AUXILIARY_BUS && MCHP_CLK_MPFS
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default MCHP_CLK_MPFS
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help
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This driver supports peripheral reset for the Microchip PolarFire SoC
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config RESET_QCOM_AOSS
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tristate "Qcom AOSS Reset Driver"
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depends on ARCH_QCOM || COMPILE_TEST
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drivers/reset/Makefile
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drivers/reset/Makefile
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obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
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obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o
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obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
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obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
···
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obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
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obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
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obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o
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-
+157
drivers/reset/reset-mpfs.c
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drivers/reset/reset-mpfs.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PolarFire SoC (MPFS) Peripheral Clock Reset Controller
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*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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* Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
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*
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*/
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#include <linux/auxiliary_bus.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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#include <soc/microchip/mpfs.h>
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/*
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* The ENVM reset is the lowest bit in the register & I am using the CLK_FOO
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* defines in the dt to make things easier to configure - so this is accounting
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* for the offset of 3 there.
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*/
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#define MPFS_PERIPH_OFFSET CLK_ENVM
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#define MPFS_NUM_RESETS 30u
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#define MPFS_SLEEP_MIN_US 100
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#define MPFS_SLEEP_MAX_US 200
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/* block concurrent access to the soft reset register */
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static DEFINE_SPINLOCK(mpfs_reset_lock);
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/*
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* Peripheral clock resets
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*/
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static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&mpfs_reset_lock, flags);
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reg = mpfs_reset_read(rcdev->dev);
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reg |= BIT(id);
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mpfs_reset_write(rcdev->dev, reg);
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spin_unlock_irqrestore(&mpfs_reset_lock, flags);
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return 0;
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}
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static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&mpfs_reset_lock, flags);
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reg = mpfs_reset_read(rcdev->dev);
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reg &= ~BIT(id);
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mpfs_reset_write(rcdev->dev, reg);
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spin_unlock_irqrestore(&mpfs_reset_lock, flags);
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return 0;
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}
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static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
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{
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u32 reg = mpfs_reset_read(rcdev->dev);
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/*
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* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
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* is never hit.
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*/
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return (reg & BIT(id));
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}
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static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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mpfs_assert(rcdev, id);
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usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US);
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mpfs_deassert(rcdev, id);
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return 0;
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}
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static const struct reset_control_ops mpfs_reset_ops = {
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.reset = mpfs_reset,
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.assert = mpfs_assert,
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.deassert = mpfs_deassert,
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.status = mpfs_status,
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};
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static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *reset_spec)
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{
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unsigned int index = reset_spec->args[0];
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/*
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* CLK_RESERVED does not map to a clock, but it does map to a reset,
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* so it has to be accounted for here. It is the reset for the fabric,
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* so if this reset gets called - do not reset it.
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*/
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if (index == CLK_RESERVED) {
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dev_err(rcdev->dev, "Resetting the fabric is not supported\n");
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return -EINVAL;
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}
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if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) {
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dev_err(rcdev->dev, "Invalid reset index %u\n", index);
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return -EINVAL;
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}
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return index - MPFS_PERIPH_OFFSET;
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}
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static int mpfs_reset_probe(struct auxiliary_device *adev,
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const struct auxiliary_device_id *id)
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{
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struct device *dev = &adev->dev;
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struct reset_controller_dev *rcdev;
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rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL);
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if (!rcdev)
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return -ENOMEM;
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rcdev->dev = dev;
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rcdev->dev->parent = dev->parent;
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rcdev->ops = &mpfs_reset_ops;
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rcdev->of_node = dev->parent->of_node;
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rcdev->of_reset_n_cells = 1;
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rcdev->of_xlate = mpfs_reset_xlate;
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rcdev->nr_resets = MPFS_NUM_RESETS;
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return devm_reset_controller_register(dev, rcdev);
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}
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static const struct auxiliary_device_id mpfs_reset_ids[] = {
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{
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.name = "clk_mpfs.reset-mpfs",
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},
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{ }
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};
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MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
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static struct auxiliary_driver mpfs_reset_driver = {
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.probe = mpfs_reset_probe,
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.id_table = mpfs_reset_ids,
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};
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module_auxiliary_driver(mpfs_reset_driver);
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MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
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MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
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MODULE_LICENSE("GPL");
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MODULE_IMPORT_NS(MCHP_CLK_MPFS);