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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'pinctrl-v5.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Sorry to bomb in fixes this late. Maybe I can comfort you by saying it
is only driver fixes, and mostly IRQ handling which is something GPIO
and pin control drivers never get right. You think it works and then
it doesn't.
Summary:
- Fix IRQ setup in the MCP23s08.
- Fix pin setup on pins > 31 in the Ocelot driver.
- Fix IRQs in the Mediatek driver"
* tag 'pinctrl-v5.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: mediatek: Update cur_mask in mask/mask ops
pinctrl: mediatek: Ignore interrupts that are wake only during resume
pinctrl: ocelot: fix pinmuxing for pins after 31
pinctrl: ocelot: fix gpio direction for pins after 31
pinctrl: mcp23s08: Fix add_data and irqchip_add_nested call order
+33
-27
+19
-15
drivers/pinctrl/mediatek/mtk-eint.c
+19
-15
drivers/pinctrl/mediatek/mtk-eint.c
···
113
113
void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
114
114
eint->regs->mask_set);
115
115
116
+
eint->cur_mask[d->hwirq >> 5] &= ~mask;
117
+
116
118
writel(mask, reg);
117
119
}
118
120
···
124
122
u32 mask = BIT(d->hwirq & 0x1f);
125
123
void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
126
124
eint->regs->mask_clr);
125
+
126
+
eint->cur_mask[d->hwirq >> 5] |= mask;
127
127
128
128
writel(mask, reg);
129
129
···
221
217
}
222
218
}
223
219
224
-
static void mtk_eint_chip_read_mask(const struct mtk_eint *eint,
225
-
void __iomem *base, u32 *buf)
226
-
{
227
-
int port;
228
-
void __iomem *reg;
229
-
230
-
for (port = 0; port < eint->hw->ports; port++) {
231
-
reg = base + eint->regs->mask + (port << 2);
232
-
buf[port] = ~readl_relaxed(reg);
233
-
/* Mask is 0 when irq is enabled, and 1 when disabled. */
234
-
}
235
-
}
236
-
237
220
static int mtk_eint_irq_request_resources(struct irq_data *d)
238
221
{
239
222
struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
···
309
318
struct irq_chip *chip = irq_desc_get_chip(desc);
310
319
struct mtk_eint *eint = irq_desc_get_handler_data(desc);
311
320
unsigned int status, eint_num;
312
-
int offset, index, virq;
321
+
int offset, mask_offset, index, virq;
313
322
void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
314
323
int dual_edge, start_level, curr_level;
315
324
···
319
328
status = readl(reg);
320
329
while (status) {
321
330
offset = __ffs(status);
331
+
mask_offset = eint_num >> 5;
322
332
index = eint_num + offset;
323
333
virq = irq_find_mapping(eint->domain, index);
324
334
status &= ~BIT(offset);
335
+
336
+
/*
337
+
* If we get an interrupt on pin that was only required
338
+
* for wake (but no real interrupt requested), mask the
339
+
* interrupt (as would mtk_eint_resume do anyway later
340
+
* in the resume sequence).
341
+
*/
342
+
if (eint->wake_mask[mask_offset] & BIT(offset) &&
343
+
!(eint->cur_mask[mask_offset] & BIT(offset))) {
344
+
writel_relaxed(BIT(offset), reg -
345
+
eint->regs->stat +
346
+
eint->regs->mask_set);
347
+
}
325
348
326
349
dual_edge = eint->dual_edge[index];
327
350
if (dual_edge) {
···
375
370
376
371
int mtk_eint_do_suspend(struct mtk_eint *eint)
377
372
{
378
-
mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask);
379
373
mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
380
374
381
375
return 0;
+4
-4
drivers/pinctrl/pinctrl-mcp23s08.c
+4
-4
drivers/pinctrl/pinctrl-mcp23s08.c
···
771
771
if (ret < 0)
772
772
goto fail;
773
773
774
+
ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
775
+
if (ret < 0)
776
+
goto fail;
777
+
774
778
mcp->irq_controller =
775
779
device_property_read_bool(dev, "interrupt-controller");
776
780
if (mcp->irq && mcp->irq_controller) {
···
815
811
if (ret)
816
812
goto fail;
817
813
}
818
-
819
-
ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
820
-
if (ret < 0)
821
-
goto fail;
822
814
823
815
if (one_regmap_config) {
824
816
mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
+10
-8
drivers/pinctrl/pinctrl-ocelot.c
+10
-8
drivers/pinctrl/pinctrl-ocelot.c
···
396
396
return -1;
397
397
}
398
398
399
-
#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
399
+
#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
400
400
401
401
static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
402
402
unsigned int selector, unsigned int group)
···
412
412
413
413
/*
414
414
* f is encoded on two bits.
415
-
* bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
416
-
* ALT1
415
+
* bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
416
+
* ALT[1]
417
417
* This is racy because both registers can't be updated at the same time
418
418
* but it doesn't matter much for now.
419
419
*/
420
-
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, pin->pin),
420
+
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
421
421
BIT(p), f << p);
422
-
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, pin->pin),
422
+
regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
423
423
BIT(p), f << (p - 1));
424
424
425
425
return 0;
426
426
}
427
+
428
+
#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
427
429
428
430
static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
429
431
struct pinctrl_gpio_range *range,
···
434
432
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
435
433
unsigned int p = pin % 32;
436
434
437
-
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, p), BIT(p),
435
+
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
438
436
input ? 0 : BIT(p));
439
437
440
438
return 0;
···
447
445
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
448
446
unsigned int p = offset % 32;
449
447
450
-
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT0, info, offset),
448
+
regmap_update_bits(info->map, REG_ALT(0, info, offset),
451
449
BIT(p), 0);
452
-
regmap_update_bits(info->map, REG(OCELOT_GPIO_ALT1, info, offset),
450
+
regmap_update_bits(info->map, REG_ALT(1, info, offset),
453
451
BIT(p), 0);
454
452
455
453
return 0;