Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Share dependency vote table with GMU
A8x GMU firmwares expect a separate vote table which describes the
relationship between the Gx rail and MxA rail (and possibly Cx rail).
Create this new vote table and implement the new HFI message which
allows passing vote tables to send this data to GMU.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689016/
Message-ID: <20251118-kaana-gpu-support-v4-13-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
authored by
Akhil P Oommen
and committed by
Rob Clark
06cfbca0
ca04ce7a
+125
+54
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+54
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
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return 0;
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}
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1619
+
static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes,
1620
+
unsigned long *freqs, int freqs_count)
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+
{
1622
+
const u16 *mx;
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+
size_t count;
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+
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mx = cmd_db_read_aux_data("mx.lvl", &count);
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if (IS_ERR(mx))
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return PTR_ERR(mx);
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/*
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* The data comes back as an array of unsigned shorts so adjust the
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* count accordingly
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*/
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count >>= 1;
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if (!count)
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return -EINVAL;
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+
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/* Fix the vote for zero frequency */
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votes[0] = 0xffffffff;
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+
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/* Construct a vote for rest of the corners */
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for (int i = 1; i < freqs_count; i++) {
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unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
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u8 j, index = 0;
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+
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/* Get the primary index that matches the arc level */
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for (j = 0; j < count; j++) {
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if (mx[j] >= level) {
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index = j;
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break;
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+
}
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}
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+
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if (j == count) {
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DRM_DEV_ERROR(dev,
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"Mx Level %u not found in the RPMh list\n",
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level);
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DRM_DEV_ERROR(dev, "Available levels:\n");
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for (j = 0; j < count; j++)
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DRM_DEV_ERROR(dev, " %u\n", mx[j]);
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+
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return -EINVAL;
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}
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+
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/* Construct the vote */
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votes[i] = (0x3fff << 14) | (index << 8) | (0xff);
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}
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+
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return 0;
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+
}
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+
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/*
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* The GMU votes with the RPMh for itself and on behalf of the GPU but we need
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* to construct the list of votes on the CPU and send it over. Query the RPMh
···
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/* Build the CX votes */
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ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
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gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl");
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+
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ret |= a6xx_gmu_rpmh_dep_votes_init(gmu->dev, gmu->dep_arc_votes,
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+
gmu->gpu_freqs, gmu->nr_gpu_freqs);
1702
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/* Build the interconnect votes */
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if (info->bcms && gmu->nr_gpu_bws > 1)
+1
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+1
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+53
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+53
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
···
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HFI_MSG_ID(HFI_H2F_MSG_START),
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HFI_MSG_ID(HFI_H2F_FEATURE_CTRL),
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HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START),
26
+
HFI_MSG_ID(HFI_H2F_MSG_TABLE),
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HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE),
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HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER),
28
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};
···
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NULL, 0);
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}
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+
static int a8xx_hfi_send_perf_table(struct a6xx_gmu *gmu)
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{
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unsigned int num_gx_votes = 3, num_cx_votes = 2;
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struct a6xx_hfi_table_entry *entry;
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struct a6xx_hfi_table *tbl;
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int ret, i;
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u32 size;
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+
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size = sizeof(*tbl) + (2 * sizeof(tbl->entry[0])) +
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(gmu->nr_gpu_freqs * num_gx_votes * sizeof(gmu->gx_arc_votes[0])) +
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+
(gmu->nr_gmu_freqs * num_cx_votes * sizeof(gmu->cx_arc_votes[0]));
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tbl = kzalloc(size, GFP_KERNEL);
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tbl->type = HFI_TABLE_GPU_PERF;
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+
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/* First fill GX votes */
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entry = &tbl->entry[0];
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entry->count = gmu->nr_gpu_freqs;
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entry->stride = num_gx_votes;
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+
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for (i = 0; i < gmu->nr_gpu_freqs; i++) {
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unsigned int base = i * entry->stride;
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+
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entry->data[base+0] = gmu->gx_arc_votes[i];
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entry->data[base+1] = gmu->dep_arc_votes[i];
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entry->data[base+2] = gmu->gpu_freqs[i] / 1000;
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}
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+
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/* Then fill CX votes */
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entry = (struct a6xx_hfi_table_entry *)
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&tbl->entry[0].data[gmu->nr_gpu_freqs * num_gx_votes];
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+
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+
entry->count = gmu->nr_gmu_freqs;
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entry->stride = num_cx_votes;
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+
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for (i = 0; i < gmu->nr_gmu_freqs; i++) {
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unsigned int base = i * entry->stride;
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+
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+
entry->data[base] = gmu->cx_arc_votes[i];
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entry->data[base+1] = gmu->gmu_freqs[i] / 1000;
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}
313
+
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ret = a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_TABLE, tbl, size, NULL, 0);
315
+
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+
kfree(tbl);
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return ret;
318
+
}
319
+
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static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu)
275
321
{
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+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
323
+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
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struct a6xx_hfi_msg_perf_table msg = { 0 };
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int i;
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+
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+
if (adreno_is_a8xx(adreno_gpu))
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return a8xx_hfi_send_perf_table(gmu);
278
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msg.num_gpu_levels = gmu->nr_gpu_freqs;
280
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msg.num_gmu_levels = gmu->nr_gmu_freqs;
+17
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
+17
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
···
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u32 handle;
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};
187
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+
#define HFI_H2F_MSG_TABLE 15
189
+
190
+
struct a6xx_hfi_table_entry {
191
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u32 count;
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u32 stride;
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u32 data[];
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};
195
+
196
+
struct a6xx_hfi_table {
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u32 header;
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u32 version;
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u32 type;
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#define HFI_TABLE_BW_VOTE 0
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+
#define HFI_TABLE_GPU_PERF 1
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struct a6xx_hfi_table_entry entry[];
203
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};
204
+
188
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#define HFI_H2F_MSG_GX_BW_PERF_VOTE 30
189
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struct a6xx_hfi_gx_bw_perf_vote_cmd {