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drm/msm/a6xx: Improve MX rail fallback in RPMH vote init

Current logic assumes that the voltage corners in both MxG and MxA are
always same. This is not true for recent targets. So, rework the rpmh init
sequence to probe and calculate the votes with the respective rails, ie,
GX rails should use MxG as secondary rail and Cx rail should use MxA as
the secondary rail.

Fixes: d6225e0cd096 ("drm/msm/adreno: Add support for X185 GPU")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689014/
Message-ID: <20251118-kaana-gpu-support-v4-12-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark ca04ce7a 50e8a557

+15 -11
+15 -11
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
··· 1544 1544 } 1545 1545 1546 1546 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1547 - unsigned long *freqs, int freqs_count, const char *id) 1547 + unsigned long *freqs, int freqs_count, 1548 + const char *pri_id, const char *sec_id) 1548 1549 { 1549 1550 int i, j; 1550 1551 const u16 *pri, *sec; 1551 1552 size_t pri_count, sec_count; 1552 1553 1553 - pri = cmd_db_read_aux_data(id, &pri_count); 1554 + pri = cmd_db_read_aux_data(pri_id, &pri_count); 1554 1555 if (IS_ERR(pri)) 1555 1556 return PTR_ERR(pri); 1556 1557 /* ··· 1562 1561 if (!pri_count) 1563 1562 return -EINVAL; 1564 1563 1565 - /* 1566 - * Some targets have a separate gfx mxc rail. So try to read that first and then fall back 1567 - * to regular mx rail if it is missing 1568 - */ 1569 - sec = cmd_db_read_aux_data("gmxc.lvl", &sec_count); 1570 - if (IS_ERR(sec) && sec != ERR_PTR(-EPROBE_DEFER)) 1571 - sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1564 + sec = cmd_db_read_aux_data(sec_id, &sec_count); 1572 1565 if (IS_ERR(sec)) 1573 1566 return PTR_ERR(sec); 1574 1567 ··· 1630 1635 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1631 1636 const struct a6xx_info *info = adreno_gpu->info->a6xx; 1632 1637 struct msm_gpu *gpu = &adreno_gpu->base; 1638 + const char *sec_id; 1639 + const u16 *gmxc; 1633 1640 int ret; 1641 + 1642 + gmxc = cmd_db_read_aux_data("gmxc.lvl", NULL); 1643 + if (gmxc == ERR_PTR(-EPROBE_DEFER)) 1644 + return -EPROBE_DEFER; 1645 + 1646 + /* If GMxC is present, prefer that as secondary rail for GX votes */ 1647 + sec_id = IS_ERR_OR_NULL(gmxc) ? "mx.lvl" : "gmxc.lvl"; 1634 1648 1635 1649 /* Build the GX votes */ 1636 1650 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1637 - gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1651 + gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl", sec_id); 1638 1652 1639 1653 /* Build the CX votes */ 1640 1654 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1641 - gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1655 + gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl", "mx.lvl"); 1642 1656 1643 1657 /* Build the interconnect votes */ 1644 1658 if (info->bcms && gmu->nr_gpu_bws > 1)