tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/dp: Implement .set_idle_link_train() for everyone

All platforms are capable of explicitly transmitting the idle
pattern. Implement it for everyone (so far it as implemented
only for HSW+).

The immediate benefit is that we gain the possibility of
implementing the POST_LT_ADJ_REQ sequence for all platforms.

Another potential future use would be a pseudo port sync mode on
pre-BDW where we attempt to sync up multiple ports/pipes by trying
to turn on the transcoders at the same time, and switching the
links to normal pixel transmission at the same time.

I'm not 100% sure the hardware is guaranteed to transmit the
required number of idle patterns (5) when switching away from
training pattern (either via explicit idle pattern, or straight
to the normal pixel output). Would be nice to confirm that at
some point, but for now let's assume it happens correctly in
both cases.

v2: Elaborate a bit more on the min required idle patterns

Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250710201718.25310-7-ville.syrjala@linux.intel.com

Ville Syrjälä 071dcf12 4cd073be

+31 -2
+31 -2
drivers/gpu/drm/i915/display/g4x_dp.c
··· 601 601 } 602 602 603 603 static void 604 + cpt_set_idle_link_train(struct intel_dp *intel_dp, 605 + const struct intel_crtc_state *crtc_state) 606 + { 607 + struct intel_display *display = to_intel_display(intel_dp); 608 + 609 + intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 610 + intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 611 + 612 + intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 613 + intel_de_posting_read(display, intel_dp->output_reg); 614 + } 615 + 616 + static void 604 617 g4x_set_link_train(struct intel_dp *intel_dp, 605 618 const struct intel_crtc_state *crtc_state, 606 619 u8 dp_train_pat) ··· 636 623 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 637 624 return; 638 625 } 626 + 627 + intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 628 + intel_de_posting_read(display, intel_dp->output_reg); 629 + } 630 + 631 + static void 632 + g4x_set_idle_link_train(struct intel_dp *intel_dp, 633 + const struct intel_crtc_state *crtc_state) 634 + { 635 + struct intel_display *display = to_intel_display(intel_dp); 636 + 637 + intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 638 + intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE; 639 639 640 640 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 641 641 intel_de_posting_read(display, intel_dp->output_reg); ··· 1357 1331 intel_encoder->audio_disable = g4x_dp_audio_disable; 1358 1332 1359 1333 if ((display->platform.ivybridge && port == PORT_A) || 1360 - (HAS_PCH_CPT(display) && port != PORT_A)) 1334 + (HAS_PCH_CPT(display) && port != PORT_A)) { 1361 1335 dig_port->dp.set_link_train = cpt_set_link_train; 1362 - else 1336 + dig_port->dp.set_idle_link_train = cpt_set_idle_link_train; 1337 + } else { 1363 1338 dig_port->dp.set_link_train = g4x_set_link_train; 1339 + dig_port->dp.set_idle_link_train = g4x_set_idle_link_train; 1340 + } 1364 1341 1365 1342 if (display->platform.cherryview) 1366 1343 intel_encoder->set_signal_levels = chv_set_signal_levels;