tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915: Remove i915_reg.h from intel_display.c

Move CHICKEN_PIPESL_1 register definition to display header.
This allows intel_display.c free of i915_reg.h include.

v3: Fix commit header (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-10-uma.shankar@intel.com

Uma Shankar 07437917 f0702380

+23 -23
-1
drivers/gpu/drm/i915/display/intel_display.c
··· 50 50 #include "g4x_hdmi.h" 51 51 #include "hsw_ips.h" 52 52 #include "i915_config.h" 53 - #include "i915_reg.h" 54 53 #include "i9xx_plane.h" 55 54 #include "i9xx_plane_regs.h" 56 55 #include "i9xx_wm.h"
+23
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 1543 1543 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 1544 1544 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 1545 1545 1546 + #define _CHICKEN_PIPESL_1_A 0x420b0 1547 + #define _CHICKEN_PIPESL_1_B 0x420b4 1548 + #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 1549 + #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 1550 + #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 1551 + #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 1552 + #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 1553 + #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 1554 + #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 1555 + #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 1556 + #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 1557 + #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 1558 + #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 1559 + #define HSW_FBCQ_DIS REG_BIT(22) 1560 + #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ 1561 + #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ 1562 + #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 1563 + #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 1564 + #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 1565 + #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 1566 + #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 1567 + #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ 1568 + 1546 1569 #define _CHICKEN_TRANS_A 0x420c0 1547 1570 #define _CHICKEN_TRANS_B 0x420c4 1548 1571 #define _CHICKEN_TRANS_C 0x420c8
-22
drivers/gpu/drm/i915/i915_reg.h
··· 878 878 #define CHICKEN_PAR2_1 _MMIO(0x42090) 879 879 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 880 880 881 - #define _CHICKEN_PIPESL_1_A 0x420b0 882 - #define _CHICKEN_PIPESL_1_B 0x420b4 883 - #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 884 - #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 885 - #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 886 - #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 887 - #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 888 - #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 889 - #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 890 - #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 891 - #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 892 - #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 893 - #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 894 - #define HSW_FBCQ_DIS REG_BIT(22) 895 - #define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */ 896 - #define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */ 897 - #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 898 - #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 899 - #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 900 - #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 901 - #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 902 - #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */ 903 881 904 882 #define DISP_ARB_CTL _MMIO(0x45000) 905 883 #define DISP_FBC_MEMORY_WAKE REG_BIT(31)