Merge tag 'i3c/for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux

+72

Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Analog Devices I3C Controller 8 + 9 + description: 10 + FPGA-based I3C controller designed to interface with I3C and I2C peripherals, 11 + implementing a subset of the I3C-basic specification. The IP core is tested 12 + on arm, microblaze, and arm64 architectures. 13 + 14 + https://analogdevicesinc.github.io/hdl/library/i3c_controller 15 + 16 + maintainers: 17 + - Jorge Marques <jorge.marques@analog.com> 18 + 19 + properties: 20 + compatible: 21 + const: adi,i3c-master-v1 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + clocks: 27 + minItems: 1 28 + items: 29 + - description: The AXI interconnect clock, drives the register map. 30 + - description: 31 + The secondary clock, drives the internal logic asynchronously to the 32 + register map. The presence of this entry states that the IP Core was 33 + synthesized with a second clock input, and the absence of this entry 34 + indicates a topology where a single clock input drives all the 35 + internal logic. 36 + 37 + clock-names: 38 + minItems: 1 39 + items: 40 + - const: axi 41 + - const: i3c 42 + 43 + interrupts: 44 + maxItems: 1 45 + 46 + required: 47 + - compatible 48 + - reg 49 + - clocks 50 + - clock-names 51 + - interrupts 52 + 53 + allOf: 54 + - $ref: i3c.yaml# 55 + 56 + unevaluatedProperties: false 57 + 58 + examples: 59 + - | 60 + #include <dt-bindings/interrupt-controller/irq.h> 61 + 62 + i3c@44a00000 { 63 + compatible = "adi,i3c-master-v1"; 64 + reg = <0x44a00000 0x1000>; 65 + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 66 + clocks = <&clkc 15>, <&clkc 15>; 67 + clock-names = "axi", "i3c"; 68 + #address-cells = <3>; 69 + #size-cells = <0>; 70 + 71 + /* I3C and I2C devices */ 72 + };

+11 -5

Documentation/devicetree/bindings/i3c/renesas,i3c.yaml

··· 4 4 $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface 7 + title: Renesas I3C Bus Interface 8 8 9 9 maintainers: 10 10 - Wolfram Sang <wsa+renesas@sang-engineering.com> ··· 12 12 13 13 properties: 14 14 compatible: 15 - items: 16 - - enum: 17 - - renesas,r9a08g045-i3c # RZ/G3S 18 - - renesas,r9a09g047-i3c # RZ/G3E 15 + oneOf: 16 + - items: 17 + - enum: 18 + - renesas,r9a08g045-i3c # RZ/G3S 19 + - renesas,r9a09g047-i3c # RZ/G3E 20 + - items: 21 + - enum: 22 + - renesas,r9a09g056-i3c # RZ/V2N 23 + - renesas,r9a09g057-i3c # RZ/V2H(P) 24 + - const: renesas,r9a09g047-i3c 19 25 20 26 reg: 21 27 maxItems: 1

+6

MAINTAINERS

··· 11674 11674 F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml 11675 11675 F: drivers/i3c/master/ast2600-i3c-master.c 11676 11676 11677 + I3C DRIVER FOR ANALOG DEVICES I3C CONTROLLER IP 11678 + M: Jorge Marques <jorge.marques@analog.com> 11679 + S: Maintained 11680 + F: Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml 11681 + F: drivers/i3c/master/adi-i3c-master.c 11682 + 11677 11683 I3C DRIVER FOR CADENCE I3C MASTER IP 11678 11684 M: Przemysław Gaj <pgaj@cadence.com> 11679 11685 S: Maintained

+10 -2

drivers/i3c/internals.h

··· 38 38 u32 tmp = 0; 39 39 40 40 memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3); 41 - writel(tmp, addr); 41 + /* 42 + * writesl() instead of writel() to keep FIFO 43 + * byteorder on big-endian targets 44 + */ 45 + writesl(addr, &tmp, 1); 42 46 } 43 47 } 44 48 ··· 59 55 if (nbytes & 3) { 60 56 u32 tmp; 61 57 62 - tmp = readl(addr); 58 + /* 59 + * readsl() instead of readl() to keep FIFO 60 + * byteorder on big-endian targets 61 + */ 62 + readsl(addr, &tmp, 1); 63 63 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3); 64 64 } 65 65 }

+75 -3

drivers/i3c/master.c

··· 8 8 #include <linux/atomic.h> 9 9 #include <linux/bug.h> 10 10 #include <linux/device.h> 11 + #include <linux/dma-mapping.h> 11 12 #include <linux/err.h> 12 13 #include <linux/export.h> 13 14 #include <linux/kernel.h> ··· 1729 1728 EXPORT_SYMBOL_GPL(i3c_master_do_daa); 1730 1729 1731 1730 /** 1731 + * i3c_master_dma_map_single() - Map buffer for single DMA transfer 1732 + * @dev: device object of a device doing DMA 1733 + * @buf: destination/source buffer for DMA 1734 + * @len: length of transfer 1735 + * @force_bounce: true, force to use a bounce buffer, 1736 + * false, function will auto check is a bounce buffer required 1737 + * @dir: DMA direction 1738 + * 1739 + * Map buffer for a DMA transfer and allocate a bounce buffer if required. 1740 + * 1741 + * Return: I3C DMA transfer descriptor or NULL in case of error. 1742 + */ 1743 + struct i3c_dma *i3c_master_dma_map_single(struct device *dev, void *buf, 1744 + size_t len, bool force_bounce, enum dma_data_direction dir) 1745 + { 1746 + struct i3c_dma *dma_xfer __free(kfree) = NULL; 1747 + void *bounce __free(kfree) = NULL; 1748 + void *dma_buf = buf; 1749 + 1750 + dma_xfer = kzalloc(sizeof(*dma_xfer), GFP_KERNEL); 1751 + if (!dma_xfer) 1752 + return NULL; 1753 + 1754 + dma_xfer->dev = dev; 1755 + dma_xfer->buf = buf; 1756 + dma_xfer->dir = dir; 1757 + dma_xfer->len = len; 1758 + dma_xfer->map_len = len; 1759 + 1760 + if (is_vmalloc_addr(buf)) 1761 + force_bounce = true; 1762 + 1763 + if (force_bounce) { 1764 + dma_xfer->map_len = ALIGN(len, cache_line_size()); 1765 + if (dir == DMA_FROM_DEVICE) 1766 + bounce = kzalloc(dma_xfer->map_len, GFP_KERNEL); 1767 + else 1768 + bounce = kmemdup(buf, dma_xfer->map_len, GFP_KERNEL); 1769 + if (!bounce) 1770 + return NULL; 1771 + dma_buf = bounce; 1772 + } 1773 + 1774 + dma_xfer->addr = dma_map_single(dev, dma_buf, dma_xfer->map_len, dir); 1775 + if (dma_mapping_error(dev, dma_xfer->addr)) 1776 + return NULL; 1777 + 1778 + dma_xfer->bounce_buf = no_free_ptr(bounce); 1779 + return no_free_ptr(dma_xfer); 1780 + } 1781 + EXPORT_SYMBOL_GPL(i3c_master_dma_map_single); 1782 + 1783 + /** 1784 + * i3c_master_dma_unmap_single() - Unmap buffer after DMA 1785 + * @dma_xfer: DMA transfer and mapping descriptor 1786 + * 1787 + * Unmap buffer and cleanup DMA transfer descriptor. 1788 + */ 1789 + void i3c_master_dma_unmap_single(struct i3c_dma *dma_xfer) 1790 + { 1791 + dma_unmap_single(dma_xfer->dev, dma_xfer->addr, 1792 + dma_xfer->map_len, dma_xfer->dir); 1793 + if (dma_xfer->bounce_buf) { 1794 + if (dma_xfer->dir == DMA_FROM_DEVICE) 1795 + memcpy(dma_xfer->buf, dma_xfer->bounce_buf, 1796 + dma_xfer->len); 1797 + kfree(dma_xfer->bounce_buf); 1798 + } 1799 + kfree(dma_xfer); 1800 + } 1801 + EXPORT_SYMBOL_GPL(i3c_master_dma_unmap_single); 1802 + 1803 + /** 1732 1804 * i3c_master_set_info() - set master device information 1733 1805 * @master: master used to send frames on the bus 1734 1806 * @info: I3C device information ··· 2564 2490 adap->owner = master->dev.parent->driver->owner; 2565 2491 adap->algo = &i3c_master_i2c_algo; 2566 2492 strscpy(adap->name, dev_name(master->dev.parent), sizeof(adap->name)); 2567 - 2568 - /* FIXME: Should we allow i3c masters to override these values? */ 2569 - adap->timeout = 1000; 2493 + adap->timeout = HZ; 2570 2494 adap->retries = 3; 2571 2495 2572 2496 id = of_alias_get_id(master->dev.of_node, "i2c");

+11

drivers/i3c/master/Kconfig

··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 + config ADI_I3C_MASTER 3 + tristate "Analog Devices I3C master driver" 4 + depends on HAS_IOMEM 5 + help 6 + Support for Analog Devices I3C Controller IP, an AXI-interfaced IP 7 + core that supports I3C and I2C devices, multiple speed-grades and I3C 8 + IBIs. 9 + 10 + This driver can also be built as a module. If so, the module will be 11 + called adi-i3c-master. 12 + 2 13 config CDNS_I3C_MASTER 3 14 tristate "Cadence I3C master driver" 4 15 depends on HAS_IOMEM

+1

drivers/i3c/master/Makefile

··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 + obj-$(CONFIG_ADI_I3C_MASTER) += adi-i3c-master.o 2 3 obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o 3 4 obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o 4 5 obj-$(CONFIG_AST2600_I3C_MASTER) += ast2600-i3c-master.o

+1019

drivers/i3c/master/adi-i3c-master.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * I3C Controller driver 4 + * Copyright 2025 Analog Devices Inc. 5 + * Author: Jorge Marques <jorge.marques@analog.com> 6 + */ 7 + 8 + #include <linux/bitops.h> 9 + #include <linux/bitfield.h> 10 + #include <linux/clk.h> 11 + #include <linux/err.h> 12 + #include <linux/errno.h> 13 + #include <linux/adi-axi-common.h> 14 + #include <linux/i3c/master.h> 15 + #include <linux/interrupt.h> 16 + #include <linux/io.h> 17 + #include <linux/module.h> 18 + #include <linux/of.h> 19 + #include <linux/platform_device.h> 20 + 21 + #include "../internals.h" 22 + 23 + #define ADI_MAX_DEVS 16 24 + #define ADI_HAS_MDB_FROM_BCR(x) (FIELD_GET(BIT(2), (x))) 25 + 26 + #define REG_ENABLE 0x040 27 + 28 + #define REG_PID_L 0x054 29 + #define REG_PID_H 0x058 30 + #define REG_DCR_BCR_DA 0x05c 31 + #define REG_DCR_BCR_DA_GET_DA(x) FIELD_GET(GENMASK(22, 16), (x)) 32 + #define REG_DCR_BCR_DA_GET_BCR(x) FIELD_GET(GENMASK(15, 8), (x)) 33 + #define REG_DCR_BCR_DA_GET_DCR(x) FIELD_GET(GENMASK(7, 0), (x)) 34 + 35 + #define REG_IRQ_MASK 0x080 36 + #define REG_IRQ_PENDING 0x084 37 + #define REG_IRQ_PENDING_DAA BIT(7) 38 + #define REG_IRQ_PENDING_IBI BIT(6) 39 + #define REG_IRQ_PENDING_CMDR BIT(5) 40 + 41 + #define REG_CMD_FIFO 0x0d4 42 + #define REG_CMD_FIFO_0_IS_CCC BIT(22) 43 + #define REG_CMD_FIFO_0_BCAST BIT(21) 44 + #define REG_CMD_FIFO_0_SR BIT(20) 45 + #define REG_CMD_FIFO_0_LEN(l) FIELD_PREP(GENMASK(19, 8), (l)) 46 + #define REG_CMD_FIFO_0_DEV_ADDR(a) FIELD_PREP(GENMASK(7, 1), (a)) 47 + #define REG_CMD_FIFO_0_RNW BIT(0) 48 + #define REG_CMD_FIFO_1_CCC(id) FIELD_PREP(GENMASK(7, 0), (id)) 49 + 50 + #define REG_CMD_FIFO_ROOM 0x0c0 51 + #define REG_CMDR_FIFO 0x0d8 52 + #define REG_CMDR_FIFO_UDA_ERROR 8 53 + #define REG_CMDR_FIFO_NACK_RESP 6 54 + #define REG_CMDR_FIFO_CE2_ERROR 4 55 + #define REG_CMDR_FIFO_CE0_ERROR 1 56 + #define REG_CMDR_FIFO_NO_ERROR 0 57 + #define REG_CMDR_FIFO_ERROR(x) FIELD_GET(GENMASK(23, 20), (x)) 58 + #define REG_CMDR_FIFO_XFER_BYTES(x) FIELD_GET(GENMASK(19, 8), (x)) 59 + 60 + #define REG_SDO_FIFO 0x0dc 61 + #define REG_SDO_FIFO_ROOM 0x0c8 62 + #define REG_SDI_FIFO 0x0e0 63 + #define REG_IBI_FIFO 0x0e4 64 + #define REG_FIFO_STATUS 0x0e8 65 + #define REG_FIFO_STATUS_CMDR_EMPTY BIT(0) 66 + #define REG_FIFO_STATUS_IBI_EMPTY BIT(1) 67 + 68 + #define REG_OPS 0x100 69 + #define REG_OPS_PP_SG_MASK GENMASK(6, 5) 70 + #define REG_OPS_SET_SG(x) FIELD_PREP(REG_OPS_PP_SG_MASK, (x)) 71 + 72 + #define REG_IBI_CONFIG 0x140 73 + #define REG_IBI_CONFIG_ENABLE BIT(0) 74 + #define REG_IBI_CONFIG_LISTEN BIT(1) 75 + 76 + #define REG_DEV_CHAR 0x180 77 + #define REG_DEV_CHAR_IS_I2C BIT(0) 78 + #define REG_DEV_CHAR_IS_ATTACHED BIT(1) 79 + #define REG_DEV_CHAR_BCR_IBI(x) FIELD_PREP(GENMASK(3, 2), (x)) 80 + #define REG_DEV_CHAR_WEN BIT(8) 81 + #define REG_DEV_CHAR_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 82 + 83 + enum speed_grade {PP_SG_UNSET, PP_SG_1MHZ, PP_SG_3MHZ, PP_SG_6MHZ, PP_SG_12MHZ}; 84 + 85 + struct adi_i3c_cmd { 86 + u32 cmd0; 87 + u32 cmd1; 88 + u32 tx_len; 89 + const void *tx_buf; 90 + u32 rx_len; 91 + void *rx_buf; 92 + u32 error; 93 + }; 94 + 95 + struct adi_i3c_xfer { 96 + struct list_head node; 97 + struct completion comp; 98 + int ret; 99 + unsigned int ncmds; 100 + unsigned int ncmds_comp; 101 + struct adi_i3c_cmd cmds[] __counted_by(ncmds); 102 + }; 103 + 104 + struct adi_i3c_master { 105 + struct i3c_master_controller base; 106 + u32 free_rr_slots; 107 + struct { 108 + unsigned int num_slots; 109 + struct i3c_dev_desc **slots; 110 + spinlock_t lock; /* Protect IBI slot access */ 111 + } ibi; 112 + struct { 113 + struct list_head list; 114 + struct adi_i3c_xfer *cur; 115 + spinlock_t lock; /* Protect transfer */ 116 + } xferqueue; 117 + void __iomem *regs; 118 + struct clk *clk; 119 + unsigned long i3c_scl_lim; 120 + struct { 121 + u8 addrs[ADI_MAX_DEVS]; 122 + u8 index; 123 + } daa; 124 + }; 125 + 126 + static inline struct adi_i3c_master *to_adi_i3c_master(struct i3c_master_controller *master) 127 + { 128 + return container_of(master, struct adi_i3c_master, base); 129 + } 130 + 131 + static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master, 132 + const u8 *buf, unsigned int nbytes) 133 + { 134 + unsigned int n, m; 135 + 136 + n = readl(master->regs + REG_SDO_FIFO_ROOM); 137 + m = min(n, nbytes); 138 + i3c_writel_fifo(master->regs + REG_SDO_FIFO, buf, m); 139 + } 140 + 141 + static void adi_i3c_master_rd_from_rx_fifo(struct adi_i3c_master *master, 142 + u8 *buf, unsigned int nbytes) 143 + { 144 + i3c_readl_fifo(master->regs + REG_SDI_FIFO, buf, nbytes); 145 + } 146 + 147 + static bool adi_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 148 + const struct i3c_ccc_cmd *cmd) 149 + { 150 + if (cmd->ndests > 1) 151 + return false; 152 + 153 + switch (cmd->id) { 154 + case I3C_CCC_ENEC(true): 155 + case I3C_CCC_ENEC(false): 156 + case I3C_CCC_DISEC(true): 157 + case I3C_CCC_DISEC(false): 158 + case I3C_CCC_RSTDAA(true): 159 + case I3C_CCC_RSTDAA(false): 160 + case I3C_CCC_ENTDAA: 161 + case I3C_CCC_SETDASA: 162 + case I3C_CCC_SETNEWDA: 163 + case I3C_CCC_GETMWL: 164 + case I3C_CCC_GETMRL: 165 + case I3C_CCC_GETPID: 166 + case I3C_CCC_GETBCR: 167 + case I3C_CCC_GETDCR: 168 + case I3C_CCC_GETSTATUS: 169 + case I3C_CCC_GETHDRCAP: 170 + return true; 171 + default: 172 + break; 173 + } 174 + 175 + return false; 176 + } 177 + 178 + static int adi_i3c_master_disable(struct adi_i3c_master *master) 179 + { 180 + writel(0, master->regs + REG_IBI_CONFIG); 181 + 182 + return 0; 183 + } 184 + 185 + static struct adi_i3c_xfer *adi_i3c_master_alloc_xfer(struct adi_i3c_master *master, 186 + unsigned int ncmds) 187 + { 188 + struct adi_i3c_xfer *xfer; 189 + 190 + xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 191 + if (!xfer) 192 + return NULL; 193 + 194 + INIT_LIST_HEAD(&xfer->node); 195 + xfer->ncmds = ncmds; 196 + xfer->ret = -ETIMEDOUT; 197 + 198 + return xfer; 199 + } 200 + 201 + static void adi_i3c_master_start_xfer_locked(struct adi_i3c_master *master) 202 + { 203 + struct adi_i3c_xfer *xfer = master->xferqueue.cur; 204 + unsigned int i, n, m; 205 + 206 + if (!xfer) 207 + return; 208 + 209 + for (i = 0; i < xfer->ncmds; i++) { 210 + struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 211 + 212 + if (!(cmd->cmd0 & REG_CMD_FIFO_0_RNW)) 213 + adi_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 214 + } 215 + 216 + n = readl(master->regs + REG_CMD_FIFO_ROOM); 217 + for (i = 0; i < xfer->ncmds; i++) { 218 + struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 219 + 220 + m = cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC ? 2 : 1; 221 + if (m > n) 222 + break; 223 + writel(cmd->cmd0, master->regs + REG_CMD_FIFO); 224 + if (cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC) 225 + writel(cmd->cmd1, master->regs + REG_CMD_FIFO); 226 + n -= m; 227 + } 228 + } 229 + 230 + static void adi_i3c_master_end_xfer_locked(struct adi_i3c_master *master, 231 + u32 pending) 232 + { 233 + struct adi_i3c_xfer *xfer = master->xferqueue.cur; 234 + int i, ret = 0; 235 + 236 + if (!xfer) 237 + return; 238 + 239 + while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_CMDR_EMPTY)) { 240 + struct adi_i3c_cmd *cmd; 241 + u32 cmdr, rx_len; 242 + 243 + cmdr = readl(master->regs + REG_CMDR_FIFO); 244 + 245 + cmd = &xfer->cmds[xfer->ncmds_comp++]; 246 + if (cmd->cmd0 & REG_CMD_FIFO_0_RNW) { 247 + rx_len = min_t(u32, REG_CMDR_FIFO_XFER_BYTES(cmdr), cmd->rx_len); 248 + adi_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len); 249 + } 250 + cmd->error = REG_CMDR_FIFO_ERROR(cmdr); 251 + } 252 + 253 + for (i = 0; i < xfer->ncmds_comp; i++) { 254 + switch (xfer->cmds[i].error) { 255 + case REG_CMDR_FIFO_NO_ERROR: 256 + break; 257 + 258 + case REG_CMDR_FIFO_CE0_ERROR: 259 + case REG_CMDR_FIFO_CE2_ERROR: 260 + case REG_CMDR_FIFO_NACK_RESP: 261 + case REG_CMDR_FIFO_UDA_ERROR: 262 + ret = -EIO; 263 + break; 264 + 265 + default: 266 + ret = -EINVAL; 267 + break; 268 + } 269 + } 270 + 271 + xfer->ret = ret; 272 + 273 + if (xfer->ncmds_comp != xfer->ncmds) 274 + return; 275 + 276 + complete(&xfer->comp); 277 + 278 + xfer = list_first_entry_or_null(&master->xferqueue.list, 279 + struct adi_i3c_xfer, node); 280 + if (xfer) 281 + list_del_init(&xfer->node); 282 + 283 + master->xferqueue.cur = xfer; 284 + adi_i3c_master_start_xfer_locked(master); 285 + } 286 + 287 + static void adi_i3c_master_queue_xfer(struct adi_i3c_master *master, 288 + struct adi_i3c_xfer *xfer) 289 + { 290 + init_completion(&xfer->comp); 291 + guard(spinlock_irqsave)(&master->xferqueue.lock); 292 + if (master->xferqueue.cur) { 293 + list_add_tail(&xfer->node, &master->xferqueue.list); 294 + } else { 295 + master->xferqueue.cur = xfer; 296 + adi_i3c_master_start_xfer_locked(master); 297 + } 298 + } 299 + 300 + static void adi_i3c_master_unqueue_xfer(struct adi_i3c_master *master, 301 + struct adi_i3c_xfer *xfer) 302 + { 303 + guard(spinlock_irqsave)(&master->xferqueue.lock); 304 + if (master->xferqueue.cur == xfer) 305 + master->xferqueue.cur = NULL; 306 + else 307 + list_del_init(&xfer->node); 308 + 309 + writel(0x01, master->regs + REG_ENABLE); 310 + writel(0x00, master->regs + REG_ENABLE); 311 + writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 312 + } 313 + 314 + static enum i3c_error_code adi_i3c_cmd_get_err(struct adi_i3c_cmd *cmd) 315 + { 316 + switch (cmd->error) { 317 + case REG_CMDR_FIFO_CE0_ERROR: 318 + return I3C_ERROR_M0; 319 + 320 + case REG_CMDR_FIFO_CE2_ERROR: 321 + case REG_CMDR_FIFO_NACK_RESP: 322 + return I3C_ERROR_M2; 323 + 324 + default: 325 + break; 326 + } 327 + 328 + return I3C_ERROR_UNKNOWN; 329 + } 330 + 331 + static int adi_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 332 + struct i3c_ccc_cmd *cmd) 333 + { 334 + struct adi_i3c_master *master = to_adi_i3c_master(m); 335 + struct adi_i3c_xfer *xfer __free(kfree) = NULL; 336 + struct adi_i3c_cmd *ccmd; 337 + 338 + xfer = adi_i3c_master_alloc_xfer(master, 1); 339 + if (!xfer) 340 + return -ENOMEM; 341 + 342 + ccmd = xfer->cmds; 343 + ccmd->cmd1 = REG_CMD_FIFO_1_CCC(cmd->id); 344 + ccmd->cmd0 = REG_CMD_FIFO_0_IS_CCC | 345 + REG_CMD_FIFO_0_LEN(cmd->dests[0].payload.len); 346 + 347 + if (cmd->id & I3C_CCC_DIRECT) 348 + ccmd->cmd0 |= REG_CMD_FIFO_0_DEV_ADDR(cmd->dests[0].addr); 349 + 350 + if (cmd->rnw) { 351 + ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 352 + ccmd->rx_buf = cmd->dests[0].payload.data; 353 + ccmd->rx_len = cmd->dests[0].payload.len; 354 + } else { 355 + ccmd->tx_buf = cmd->dests[0].payload.data; 356 + ccmd->tx_len = cmd->dests[0].payload.len; 357 + } 358 + 359 + adi_i3c_master_queue_xfer(master, xfer); 360 + if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 361 + adi_i3c_master_unqueue_xfer(master, xfer); 362 + 363 + cmd->err = adi_i3c_cmd_get_err(&xfer->cmds[0]); 364 + 365 + return 0; 366 + } 367 + 368 + static int adi_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 369 + struct i3c_priv_xfer *xfers, 370 + int nxfers) 371 + { 372 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 373 + struct adi_i3c_master *master = to_adi_i3c_master(m); 374 + struct adi_i3c_xfer *xfer __free(kfree) = NULL; 375 + int i, ret; 376 + 377 + if (!nxfers) 378 + return 0; 379 + 380 + xfer = adi_i3c_master_alloc_xfer(master, nxfers); 381 + if (!xfer) 382 + return -ENOMEM; 383 + 384 + for (i = 0; i < nxfers; i++) { 385 + struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 386 + 387 + ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(dev->info.dyn_addr); 388 + 389 + if (xfers[i].rnw) { 390 + ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 391 + ccmd->rx_buf = xfers[i].data.in; 392 + ccmd->rx_len = xfers[i].len; 393 + } else { 394 + ccmd->tx_buf = xfers[i].data.out; 395 + ccmd->tx_len = xfers[i].len; 396 + } 397 + 398 + ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 399 + 400 + if (i < nxfers - 1) 401 + ccmd->cmd0 |= REG_CMD_FIFO_0_SR; 402 + 403 + if (!i) 404 + ccmd->cmd0 |= REG_CMD_FIFO_0_BCAST; 405 + } 406 + 407 + adi_i3c_master_queue_xfer(master, xfer); 408 + if (!wait_for_completion_timeout(&xfer->comp, 409 + msecs_to_jiffies(1000))) 410 + adi_i3c_master_unqueue_xfer(master, xfer); 411 + 412 + ret = xfer->ret; 413 + 414 + for (i = 0; i < nxfers; i++) 415 + xfers[i].err = adi_i3c_cmd_get_err(&xfer->cmds[i]); 416 + 417 + return ret; 418 + } 419 + 420 + struct adi_i3c_i2c_dev_data { 421 + struct i3c_generic_ibi_pool *ibi_pool; 422 + u16 id; 423 + s16 ibi; 424 + }; 425 + 426 + static int adi_i3c_master_get_rr_slot(struct adi_i3c_master *master, 427 + u8 dyn_addr) 428 + { 429 + if (!master->free_rr_slots) 430 + return -ENOSPC; 431 + 432 + return ffs(master->free_rr_slots) - 1; 433 + } 434 + 435 + static int adi_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 dyn_addr) 436 + { 437 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 438 + struct adi_i3c_master *master = to_adi_i3c_master(m); 439 + u8 addr; 440 + 441 + addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 442 + 443 + writel(REG_DEV_CHAR_ADDR(dyn_addr), master->regs + REG_DEV_CHAR); 444 + writel((readl(master->regs + REG_DEV_CHAR) & 445 + ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 446 + master->regs + REG_DEV_CHAR); 447 + 448 + writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 449 + writel(readl(master->regs + REG_DEV_CHAR) | 450 + REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 451 + master->regs + REG_DEV_CHAR); 452 + 453 + return 0; 454 + } 455 + 456 + static int adi_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 457 + { 458 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 459 + struct adi_i3c_master *master = to_adi_i3c_master(m); 460 + struct adi_i3c_i2c_dev_data *data; 461 + int slot; 462 + u8 addr; 463 + 464 + data = kzalloc(sizeof(*data), GFP_KERNEL); 465 + if (!data) 466 + return -ENOMEM; 467 + 468 + slot = adi_i3c_master_get_rr_slot(master, dev->info.dyn_addr); 469 + if (slot < 0) { 470 + kfree(data); 471 + return slot; 472 + } 473 + 474 + data->id = slot; 475 + i3c_dev_set_master_data(dev, data); 476 + master->free_rr_slots &= ~BIT(slot); 477 + 478 + addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 479 + 480 + writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 481 + writel(readl(master->regs + REG_DEV_CHAR) | 482 + REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 483 + master->regs + REG_DEV_CHAR); 484 + 485 + return 0; 486 + } 487 + 488 + static void adi_i3c_master_sync_dev_char(struct i3c_master_controller *m) 489 + { 490 + struct adi_i3c_master *master = to_adi_i3c_master(m); 491 + struct i3c_dev_desc *i3cdev; 492 + u32 bcr_ibi; 493 + u8 addr; 494 + 495 + i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 496 + addr = i3cdev->info.dyn_addr ? 497 + i3cdev->info.dyn_addr : i3cdev->info.static_addr; 498 + writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 499 + bcr_ibi = FIELD_GET(I3C_BCR_IBI_PAYLOAD | I3C_BCR_IBI_REQ_CAP, (i3cdev->info.bcr)); 500 + writel(readl(master->regs + REG_DEV_CHAR) | 501 + REG_DEV_CHAR_BCR_IBI(bcr_ibi) | REG_DEV_CHAR_WEN, 502 + master->regs + REG_DEV_CHAR); 503 + } 504 + } 505 + 506 + static void adi_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 507 + { 508 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 509 + struct adi_i3c_master *master = to_adi_i3c_master(m); 510 + struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 511 + u8 addr; 512 + 513 + addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 514 + 515 + writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 516 + writel((readl(master->regs + REG_DEV_CHAR) & 517 + ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 518 + master->regs + REG_DEV_CHAR); 519 + 520 + i3c_dev_set_master_data(dev, NULL); 521 + master->free_rr_slots |= BIT(data->id); 522 + kfree(data); 523 + } 524 + 525 + static int adi_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 526 + { 527 + struct i3c_master_controller *m = i2c_dev_get_master(dev); 528 + struct adi_i3c_master *master = to_adi_i3c_master(m); 529 + struct adi_i3c_i2c_dev_data *data; 530 + int slot; 531 + 532 + slot = adi_i3c_master_get_rr_slot(master, 0); 533 + if (slot < 0) 534 + return slot; 535 + 536 + data = kzalloc(sizeof(*data), GFP_KERNEL); 537 + if (!data) 538 + return -ENOMEM; 539 + 540 + data->id = slot; 541 + master->free_rr_slots &= ~BIT(slot); 542 + i2c_dev_set_master_data(dev, data); 543 + 544 + writel(REG_DEV_CHAR_ADDR(dev->addr) | 545 + REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 546 + master->regs + REG_DEV_CHAR); 547 + 548 + return 0; 549 + } 550 + 551 + static void adi_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 552 + { 553 + struct i3c_master_controller *m = i2c_dev_get_master(dev); 554 + struct adi_i3c_master *master = to_adi_i3c_master(m); 555 + struct adi_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 556 + 557 + writel(REG_DEV_CHAR_ADDR(dev->addr) | 558 + REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_WEN, 559 + master->regs + REG_DEV_CHAR); 560 + 561 + i2c_dev_set_master_data(dev, NULL); 562 + master->free_rr_slots |= BIT(data->id); 563 + kfree(data); 564 + } 565 + 566 + static void adi_i3c_master_bus_cleanup(struct i3c_master_controller *m) 567 + { 568 + struct adi_i3c_master *master = to_adi_i3c_master(m); 569 + 570 + adi_i3c_master_disable(master); 571 + } 572 + 573 + static void adi_i3c_master_upd_i3c_scl_lim(struct adi_i3c_master *master) 574 + { 575 + struct i3c_master_controller *m = &master->base; 576 + struct i3c_bus *bus = i3c_master_get_bus(m); 577 + u8 i3c_scl_lim = 0; 578 + struct i3c_dev_desc *dev; 579 + u8 pp_sg; 580 + 581 + i3c_bus_for_each_i3cdev(bus, dev) { 582 + u8 max_fscl; 583 + 584 + max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds), 585 + I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds)); 586 + 587 + switch (max_fscl) { 588 + case I3C_SDR1_FSCL_8MHZ: 589 + max_fscl = PP_SG_6MHZ; 590 + break; 591 + case I3C_SDR2_FSCL_6MHZ: 592 + max_fscl = PP_SG_3MHZ; 593 + break; 594 + case I3C_SDR3_FSCL_4MHZ: 595 + max_fscl = PP_SG_3MHZ; 596 + break; 597 + case I3C_SDR4_FSCL_2MHZ: 598 + max_fscl = PP_SG_1MHZ; 599 + break; 600 + case I3C_SDR0_FSCL_MAX: 601 + default: 602 + max_fscl = PP_SG_12MHZ; 603 + break; 604 + } 605 + 606 + if (max_fscl && 607 + (i3c_scl_lim > max_fscl || !i3c_scl_lim)) 608 + i3c_scl_lim = max_fscl; 609 + } 610 + 611 + if (!i3c_scl_lim) 612 + return; 613 + 614 + master->i3c_scl_lim = i3c_scl_lim - 1; 615 + 616 + pp_sg = readl(master->regs + REG_OPS) & ~REG_OPS_PP_SG_MASK; 617 + pp_sg |= REG_OPS_SET_SG(master->i3c_scl_lim); 618 + 619 + writel(pp_sg, master->regs + REG_OPS); 620 + } 621 + 622 + static void adi_i3c_master_get_features(struct adi_i3c_master *master, 623 + unsigned int slot, 624 + struct i3c_device_info *info) 625 + { 626 + u32 buf; 627 + 628 + /* Dynamic address and PID are for identification only */ 629 + memset(info, 0, sizeof(*info)); 630 + buf = readl(master->regs + REG_DCR_BCR_DA); 631 + info->dyn_addr = REG_DCR_BCR_DA_GET_DA(buf); 632 + info->dcr = REG_DCR_BCR_DA_GET_DCR(buf); 633 + info->bcr = REG_DCR_BCR_DA_GET_BCR(buf); 634 + info->pid = readl(master->regs + REG_PID_L); 635 + info->pid |= (u64)readl(master->regs + REG_PID_H) << 32; 636 + } 637 + 638 + static int adi_i3c_master_do_daa(struct i3c_master_controller *m) 639 + { 640 + struct adi_i3c_master *master = to_adi_i3c_master(m); 641 + int ret, addr = 0; 642 + u32 irq_mask; 643 + 644 + for (u8 i = 0; i < ADI_MAX_DEVS; i++) { 645 + addr = i3c_master_get_free_addr(m, addr); 646 + if (addr < 0) 647 + return addr; 648 + master->daa.addrs[i] = addr; 649 + } 650 + 651 + irq_mask = readl(master->regs + REG_IRQ_MASK); 652 + writel(irq_mask | REG_IRQ_PENDING_DAA, 653 + master->regs + REG_IRQ_MASK); 654 + 655 + master->daa.index = 0; 656 + ret = i3c_master_entdaa_locked(&master->base); 657 + 658 + writel(irq_mask, master->regs + REG_IRQ_MASK); 659 + 660 + /* DAA always finishes with CE2_ERROR or NACK_RESP */ 661 + if (ret && ret != I3C_ERROR_M2) 662 + return ret; 663 + 664 + /* Add I3C devices discovered */ 665 + for (u8 i = 0; i < master->daa.index; i++) 666 + i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]); 667 + /* Sync retrieved devs info with the IP */ 668 + adi_i3c_master_sync_dev_char(m); 669 + 670 + i3c_master_defslvs_locked(&master->base); 671 + 672 + adi_i3c_master_upd_i3c_scl_lim(master); 673 + 674 + return 0; 675 + } 676 + 677 + static int adi_i3c_master_bus_init(struct i3c_master_controller *m) 678 + { 679 + struct adi_i3c_master *master = to_adi_i3c_master(m); 680 + struct i3c_device_info info = { }; 681 + int ret; 682 + 683 + ret = i3c_master_get_free_addr(m, 0); 684 + if (ret < 0) 685 + return ret; 686 + 687 + adi_i3c_master_get_features(master, 0, &info); 688 + ret = i3c_master_set_info(&master->base, &info); 689 + if (ret) 690 + return ret; 691 + 692 + writel(REG_IBI_CONFIG_LISTEN, 693 + master->regs + REG_IBI_CONFIG); 694 + 695 + return 0; 696 + } 697 + 698 + static void adi_i3c_master_handle_ibi(struct adi_i3c_master *master, 699 + u32 raw) 700 + { 701 + struct adi_i3c_i2c_dev_data *data; 702 + struct i3c_ibi_slot *slot; 703 + struct i3c_dev_desc *dev; 704 + u8 da, id, mdb, len; 705 + u8 *buf; 706 + 707 + da = FIELD_GET(GENMASK(23, 17), raw); 708 + mdb = FIELD_GET(GENMASK(15, 8), raw); 709 + for (id = 0; id < master->ibi.num_slots; id++) { 710 + if (master->ibi.slots[id] && 711 + master->ibi.slots[id]->info.dyn_addr == da) 712 + break; 713 + } 714 + 715 + if (id == master->ibi.num_slots) 716 + return; 717 + 718 + dev = master->ibi.slots[id]; 719 + len = ADI_HAS_MDB_FROM_BCR(dev->info.bcr); 720 + data = i3c_dev_get_master_data(dev); 721 + 722 + guard(spinlock)(&master->ibi.lock); 723 + slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 724 + if (!slot) 725 + return; 726 + 727 + slot->len = len; 728 + buf = slot->data; 729 + buf[0] = mdb; 730 + i3c_master_queue_ibi(dev, slot); 731 + } 732 + 733 + static void adi_i3c_master_demux_ibis(struct adi_i3c_master *master) 734 + { 735 + while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_IBI_EMPTY)) { 736 + u32 raw = readl(master->regs + REG_IBI_FIFO); 737 + 738 + adi_i3c_master_handle_ibi(master, raw); 739 + } 740 + } 741 + 742 + static void adi_i3c_master_handle_da_req(struct adi_i3c_master *master) 743 + { 744 + u8 payload0[8]; 745 + u32 addr; 746 + 747 + adi_i3c_master_rd_from_rx_fifo(master, payload0, 6); 748 + addr = master->daa.addrs[master->daa.index++]; 749 + addr = (addr << 1) | (parity8(addr) ? 0 : 1); 750 + 751 + writel(addr, master->regs + REG_SDO_FIFO); 752 + } 753 + 754 + static irqreturn_t adi_i3c_master_irq(int irq, void *data) 755 + { 756 + struct adi_i3c_master *master = data; 757 + u32 pending; 758 + 759 + pending = readl(master->regs + REG_IRQ_PENDING); 760 + writel(pending, master->regs + REG_IRQ_PENDING); 761 + if (pending & REG_IRQ_PENDING_CMDR) { 762 + scoped_guard(spinlock_irqsave, &master->xferqueue.lock) { 763 + adi_i3c_master_end_xfer_locked(master, pending); 764 + } 765 + } 766 + if (pending & REG_IRQ_PENDING_IBI) 767 + adi_i3c_master_demux_ibis(master); 768 + if (pending & REG_IRQ_PENDING_DAA) 769 + adi_i3c_master_handle_da_req(master); 770 + 771 + return IRQ_HANDLED; 772 + } 773 + 774 + static int adi_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 775 + struct i2c_msg *xfers, 776 + int nxfers) 777 + { 778 + struct i3c_master_controller *m = i2c_dev_get_master(dev); 779 + struct adi_i3c_master *master = to_adi_i3c_master(m); 780 + struct adi_i3c_xfer *xfer __free(kfree) = NULL; 781 + int i; 782 + 783 + if (!nxfers) 784 + return 0; 785 + for (i = 0; i < nxfers; i++) { 786 + if (xfers[i].flags & I2C_M_TEN) 787 + return -EOPNOTSUPP; 788 + } 789 + xfer = adi_i3c_master_alloc_xfer(master, nxfers); 790 + if (!xfer) 791 + return -ENOMEM; 792 + 793 + for (i = 0; i < nxfers; i++) { 794 + struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 795 + 796 + ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(xfers[i].addr); 797 + 798 + if (xfers[i].flags & I2C_M_RD) { 799 + ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 800 + ccmd->rx_buf = xfers[i].buf; 801 + ccmd->rx_len = xfers[i].len; 802 + } else { 803 + ccmd->tx_buf = xfers[i].buf; 804 + ccmd->tx_len = xfers[i].len; 805 + } 806 + 807 + ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 808 + } 809 + 810 + adi_i3c_master_queue_xfer(master, xfer); 811 + if (!wait_for_completion_timeout(&xfer->comp, 812 + m->i2c.timeout)) 813 + adi_i3c_master_unqueue_xfer(master, xfer); 814 + 815 + return xfer->ret; 816 + } 817 + 818 + static int adi_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 819 + { 820 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 821 + struct adi_i3c_master *master = to_adi_i3c_master(m); 822 + struct i3c_dev_desc *i3cdev; 823 + u32 enabled = 0; 824 + int ret; 825 + 826 + ret = i3c_master_disec_locked(m, dev->info.dyn_addr, 827 + I3C_CCC_EVENT_SIR); 828 + 829 + i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 830 + if (dev != i3cdev && i3cdev->ibi) 831 + enabled |= i3cdev->ibi->enabled; 832 + } 833 + if (!enabled) { 834 + writel(REG_IBI_CONFIG_LISTEN, 835 + master->regs + REG_IBI_CONFIG); 836 + writel(readl(master->regs + REG_IRQ_MASK) & ~REG_IRQ_PENDING_IBI, 837 + master->regs + REG_IRQ_MASK); 838 + } 839 + 840 + return ret; 841 + } 842 + 843 + static int adi_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 844 + { 845 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 846 + struct adi_i3c_master *master = to_adi_i3c_master(m); 847 + 848 + writel(REG_IBI_CONFIG_LISTEN | REG_IBI_CONFIG_ENABLE, 849 + master->regs + REG_IBI_CONFIG); 850 + 851 + writel(readl(master->regs + REG_IRQ_MASK) | REG_IRQ_PENDING_IBI, 852 + master->regs + REG_IRQ_MASK); 853 + 854 + return i3c_master_enec_locked(m, dev->info.dyn_addr, 855 + I3C_CCC_EVENT_SIR); 856 + } 857 + 858 + static int adi_i3c_master_request_ibi(struct i3c_dev_desc *dev, 859 + const struct i3c_ibi_setup *req) 860 + { 861 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 862 + struct adi_i3c_master *master = to_adi_i3c_master(m); 863 + struct adi_i3c_i2c_dev_data *data; 864 + unsigned int i; 865 + 866 + data = i3c_dev_get_master_data(dev); 867 + data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 868 + if (IS_ERR(data->ibi_pool)) 869 + return PTR_ERR(data->ibi_pool); 870 + 871 + scoped_guard(spinlock_irqsave, &master->ibi.lock) { 872 + for (i = 0; i < master->ibi.num_slots; i++) { 873 + if (!master->ibi.slots[i]) { 874 + data->ibi = i; 875 + master->ibi.slots[i] = dev; 876 + break; 877 + } 878 + } 879 + } 880 + 881 + if (i < master->ibi.num_slots) 882 + return 0; 883 + 884 + i3c_generic_ibi_free_pool(data->ibi_pool); 885 + data->ibi_pool = NULL; 886 + 887 + return -ENOSPC; 888 + } 889 + 890 + static void adi_i3c_master_free_ibi(struct i3c_dev_desc *dev) 891 + { 892 + struct i3c_master_controller *m = i3c_dev_get_master(dev); 893 + struct adi_i3c_master *master = to_adi_i3c_master(m); 894 + struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 895 + 896 + scoped_guard(spinlock_irqsave, &master->ibi.lock) { 897 + master->ibi.slots[data->ibi] = NULL; 898 + } 899 + 900 + i3c_generic_ibi_free_pool(data->ibi_pool); 901 + } 902 + 903 + static void adi_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 904 + struct i3c_ibi_slot *slot) 905 + { 906 + struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 907 + 908 + i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 909 + } 910 + 911 + static const struct i3c_master_controller_ops adi_i3c_master_ops = { 912 + .bus_init = adi_i3c_master_bus_init, 913 + .bus_cleanup = adi_i3c_master_bus_cleanup, 914 + .attach_i3c_dev = adi_i3c_master_attach_i3c_dev, 915 + .reattach_i3c_dev = adi_i3c_master_reattach_i3c_dev, 916 + .detach_i3c_dev = adi_i3c_master_detach_i3c_dev, 917 + .attach_i2c_dev = adi_i3c_master_attach_i2c_dev, 918 + .detach_i2c_dev = adi_i3c_master_detach_i2c_dev, 919 + .do_daa = adi_i3c_master_do_daa, 920 + .supports_ccc_cmd = adi_i3c_master_supports_ccc_cmd, 921 + .send_ccc_cmd = adi_i3c_master_send_ccc_cmd, 922 + .priv_xfers = adi_i3c_master_priv_xfers, 923 + .i2c_xfers = adi_i3c_master_i2c_xfers, 924 + .request_ibi = adi_i3c_master_request_ibi, 925 + .enable_ibi = adi_i3c_master_enable_ibi, 926 + .disable_ibi = adi_i3c_master_disable_ibi, 927 + .free_ibi = adi_i3c_master_free_ibi, 928 + .recycle_ibi_slot = adi_i3c_master_recycle_ibi_slot, 929 + }; 930 + 931 + static const struct of_device_id adi_i3c_master_of_match[] = { 932 + { .compatible = "adi,i3c-master-v1" }, 933 + {} 934 + }; 935 + 936 + static int adi_i3c_master_probe(struct platform_device *pdev) 937 + { 938 + struct adi_i3c_master *master; 939 + struct clk_bulk_data *clk; 940 + unsigned int version; 941 + int ret, irq; 942 + 943 + master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 944 + if (!master) 945 + return -ENOMEM; 946 + 947 + master->regs = devm_platform_ioremap_resource(pdev, 0); 948 + if (IS_ERR(master->regs)) 949 + return PTR_ERR(master->regs); 950 + 951 + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clk); 952 + if (ret < 0) 953 + return dev_err_probe(&pdev->dev, ret, 954 + "Failed to get clocks\n"); 955 + 956 + irq = platform_get_irq(pdev, 0); 957 + if (irq < 0) 958 + return irq; 959 + 960 + version = readl(master->regs + ADI_AXI_REG_VERSION); 961 + if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) 962 + dev_err_probe(&pdev->dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n", 963 + ADI_AXI_PCORE_VER_MAJOR(version), 964 + ADI_AXI_PCORE_VER_MINOR(version), 965 + ADI_AXI_PCORE_VER_PATCH(version)); 966 + 967 + writel(0x00, master->regs + REG_ENABLE); 968 + writel(0x00, master->regs + REG_IRQ_MASK); 969 + 970 + ret = devm_request_irq(&pdev->dev, irq, adi_i3c_master_irq, 0, 971 + dev_name(&pdev->dev), master); 972 + if (ret) 973 + return ret; 974 + 975 + platform_set_drvdata(pdev, master); 976 + 977 + master->free_rr_slots = GENMASK(ADI_MAX_DEVS, 1); 978 + 979 + writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 980 + 981 + spin_lock_init(&master->ibi.lock); 982 + master->ibi.num_slots = 15; 983 + master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 984 + sizeof(*master->ibi.slots), 985 + GFP_KERNEL); 986 + if (!master->ibi.slots) 987 + return -ENOMEM; 988 + 989 + spin_lock_init(&master->xferqueue.lock); 990 + INIT_LIST_HEAD(&master->xferqueue.list); 991 + 992 + return i3c_master_register(&master->base, &pdev->dev, 993 + &adi_i3c_master_ops, false); 994 + } 995 + 996 + static void adi_i3c_master_remove(struct platform_device *pdev) 997 + { 998 + struct adi_i3c_master *master = platform_get_drvdata(pdev); 999 + 1000 + writel(0xff, master->regs + REG_IRQ_PENDING); 1001 + writel(0x00, master->regs + REG_IRQ_MASK); 1002 + writel(0x01, master->regs + REG_ENABLE); 1003 + 1004 + i3c_master_unregister(&master->base); 1005 + } 1006 + 1007 + static struct platform_driver adi_i3c_master = { 1008 + .probe = adi_i3c_master_probe, 1009 + .remove = adi_i3c_master_remove, 1010 + .driver = { 1011 + .name = "adi-i3c-master", 1012 + .of_match_table = adi_i3c_master_of_match, 1013 + }, 1014 + }; 1015 + module_platform_driver(adi_i3c_master); 1016 + 1017 + MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1018 + MODULE_DESCRIPTION("Analog Devices I3C master driver"); 1019 + MODULE_LICENSE("GPL");

+23

drivers/i3c/master/dw-i3c-master.c

··· 1737 1737 SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_resume, NULL) 1738 1738 }; 1739 1739 1740 + static void dw_i3c_shutdown(struct platform_device *pdev) 1741 + { 1742 + struct dw_i3c_master *master = platform_get_drvdata(pdev); 1743 + int ret; 1744 + 1745 + ret = pm_runtime_resume_and_get(master->dev); 1746 + if (ret < 0) { 1747 + dev_err(master->dev, 1748 + "<%s> cannot resume i3c bus master, err: %d\n", 1749 + __func__, ret); 1750 + return; 1751 + } 1752 + 1753 + cancel_work_sync(&master->hj_work); 1754 + 1755 + /* Disable interrupts */ 1756 + writel((u32)~INTR_ALL, master->regs + INTR_STATUS_EN); 1757 + writel((u32)~INTR_ALL, master->regs + INTR_SIGNAL_EN); 1758 + 1759 + pm_runtime_put_autosuspend(master->dev); 1760 + } 1761 + 1740 1762 static const struct of_device_id dw_i3c_master_of_match[] = { 1741 1763 { .compatible = "snps,dw-i3c-master-1.00a", }, 1742 1764 {}, ··· 1774 1752 static struct platform_driver dw_i3c_driver = { 1775 1753 .probe = dw_i3c_probe, 1776 1754 .remove = dw_i3c_remove, 1755 + .shutdown = dw_i3c_shutdown, 1777 1756 .driver = { 1778 1757 .name = "dw-i3c-master", 1779 1758 .of_match_table = dw_i3c_master_of_match,

+6 -3

drivers/i3c/master/mipi-i3c-hci/cmd_v1.c

··· 317 317 break; 318 318 next_addr = ret; 319 319 320 - DBG("next_addr = 0x%02x, DAA using DAT %d", next_addr, dat_idx); 320 + dev_dbg(&hci->master.dev, 321 + "next_addr = 0x%02x, DAA using DAT %d", 322 + next_addr, dat_idx); 321 323 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dat_idx, next_addr); 322 324 mipi_i3c_hci_dct_index_reset(hci); 323 325 ··· 351 349 } 352 350 353 351 i3c_hci_dct_get_val(hci, 0, &pid, &dcr, &bcr); 354 - DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x", 355 - next_addr, pid, dcr, bcr); 352 + dev_dbg(&hci->master.dev, 353 + "assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x", 354 + next_addr, pid, dcr, bcr); 356 355 357 356 mipi_i3c_hci_dat_v1.free_entry(hci, dat_idx); 358 357 dat_idx = -1;

+4 -3

drivers/i3c/master/mipi-i3c-hci/cmd_v2.c

··· 261 261 if (ret < 0) 262 262 break; 263 263 next_addr = ret; 264 - DBG("next_addr = 0x%02x", next_addr); 264 + dev_dbg(&hci->master.dev, "next_addr = 0x%02x", next_addr); 265 265 xfer[0].cmd_tid = hci_get_tid(); 266 266 xfer[0].cmd_desc[0] = 267 267 CMD_0_ATTR_A | ··· 293 293 pid = (pid << 32) | device_id[0]; 294 294 bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]); 295 295 dcr = FIELD_GET(W1_MASK(63, 56), device_id[1]); 296 - DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x", 297 - next_addr, pid, dcr, bcr); 296 + dev_dbg(&hci->master.dev, 297 + "assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x", 298 + next_addr, pid, dcr, bcr); 298 299 /* 299 300 * TODO: Extend the subsystem layer to allow for registering 300 301 * new device and provide BCR/DCR/PID at the same time.

+10 -64

drivers/i3c/master/mipi-i3c-hci/core.c

··· 121 121 struct i3c_device_info info; 122 122 int ret; 123 123 124 - DBG(""); 125 - 126 124 if (hci->cmd == &mipi_i3c_hci_cmd_v1) { 127 125 ret = mipi_i3c_hci_dat_v1.init(hci); 128 126 if (ret) ··· 147 149 amd_set_resp_buf_thld(hci); 148 150 149 151 reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 150 - DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL)); 152 + dev_dbg(&hci->master.dev, "HC_CONTROL = %#x", reg_read(HC_CONTROL)); 151 153 152 154 return 0; 153 155 } ··· 156 158 { 157 159 struct i3c_hci *hci = to_i3c_hci(m); 158 160 struct platform_device *pdev = to_platform_device(m->dev.parent); 159 - 160 - DBG(""); 161 161 162 162 reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 163 163 synchronize_irq(platform_get_irq(pdev, 0)); ··· 192 196 DECLARE_COMPLETION_ONSTACK(done); 193 197 int i, last, ret = 0; 194 198 195 - DBG("cmd=%#x rnw=%d ndests=%d data[0].len=%d", 196 - ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len); 199 + dev_dbg(&hci->master.dev, "cmd=%#x rnw=%d ndests=%d data[0].len=%d", 200 + ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len); 197 201 198 202 xfer = hci_alloc_xfer(nxfers); 199 203 if (!xfer) ··· 251 255 } 252 256 253 257 if (ccc->rnw) 254 - DBG("got: %*ph", 255 - ccc->dests[0].payload.len, ccc->dests[0].payload.data); 258 + dev_dbg(&hci->master.dev, "got: %*ph", 259 + ccc->dests[0].payload.len, ccc->dests[0].payload.data); 256 260 257 261 out: 258 262 hci_free_xfer(xfer, nxfers); ··· 263 267 { 264 268 struct i3c_hci *hci = to_i3c_hci(m); 265 269 266 - DBG(""); 267 - 268 270 return hci->cmd->perform_daa(hci); 269 - } 270 - 271 - static int i3c_hci_alloc_safe_xfer_buf(struct i3c_hci *hci, 272 - struct hci_xfer *xfer) 273 - { 274 - if (hci->io != &mipi_i3c_hci_dma || 275 - xfer->data == NULL || !is_vmalloc_addr(xfer->data)) 276 - return 0; 277 - 278 - if (xfer->rnw) 279 - xfer->bounce_buf = kzalloc(xfer->data_len, GFP_KERNEL); 280 - else 281 - xfer->bounce_buf = kmemdup(xfer->data, 282 - xfer->data_len, GFP_KERNEL); 283 - 284 - return xfer->bounce_buf == NULL ? -ENOMEM : 0; 285 - } 286 - 287 - static void i3c_hci_free_safe_xfer_buf(struct i3c_hci *hci, 288 - struct hci_xfer *xfer) 289 - { 290 - if (hci->io != &mipi_i3c_hci_dma || xfer->bounce_buf == NULL) 291 - return; 292 - 293 - if (xfer->rnw) 294 - memcpy(xfer->data, xfer->bounce_buf, xfer->data_len); 295 - 296 - kfree(xfer->bounce_buf); 297 271 } 298 272 299 273 static int i3c_hci_priv_xfers(struct i3c_dev_desc *dev, ··· 277 311 unsigned int size_limit; 278 312 int i, last, ret = 0; 279 313 280 - DBG("nxfers = %d", nxfers); 314 + dev_dbg(&hci->master.dev, "nxfers = %d", nxfers); 281 315 282 316 xfer = hci_alloc_xfer(nxfers); 283 317 if (!xfer) ··· 299 333 } 300 334 hci->cmd->prep_i3c_xfer(hci, dev, &xfer[i]); 301 335 xfer[i].cmd_desc[0] |= CMD_0_ROC; 302 - ret = i3c_hci_alloc_safe_xfer_buf(hci, &xfer[i]); 303 - if (ret) 304 - goto out; 305 336 } 306 337 last = i - 1; 307 338 xfer[last].cmd_desc[0] |= CMD_0_TOC; ··· 322 359 } 323 360 324 361 out: 325 - for (i = 0; i < nxfers; i++) 326 - i3c_hci_free_safe_xfer_buf(hci, &xfer[i]); 327 - 328 362 hci_free_xfer(xfer, nxfers); 329 363 return ret; 330 364 } ··· 335 375 DECLARE_COMPLETION_ONSTACK(done); 336 376 int i, last, ret = 0; 337 377 338 - DBG("nxfers = %d", nxfers); 378 + dev_dbg(&hci->master.dev, "nxfers = %d", nxfers); 339 379 340 380 xfer = hci_alloc_xfer(nxfers); 341 381 if (!xfer) 342 382 return -ENOMEM; 343 383 344 384 for (i = 0; i < nxfers; i++) { 345 - xfer[i].data = i2c_get_dma_safe_msg_buf(&i2c_xfers[i], 1); 385 + xfer[i].data = i2c_xfers[i].buf; 346 386 xfer[i].data_len = i2c_xfers[i].len; 347 387 xfer[i].rnw = i2c_xfers[i].flags & I2C_M_RD; 348 388 hci->cmd->prep_i2c_xfer(hci, dev, &xfer[i]); ··· 368 408 } 369 409 370 410 out: 371 - for (i = 0; i < nxfers; i++) 372 - i2c_put_dma_safe_msg_buf(xfer[i].data, &i2c_xfers[i], 373 - ret ? false : true); 374 - 375 411 hci_free_xfer(xfer, nxfers); 376 412 return ret; 377 413 } ··· 378 422 struct i3c_hci *hci = to_i3c_hci(m); 379 423 struct i3c_hci_dev_data *dev_data; 380 424 int ret; 381 - 382 - DBG(""); 383 425 384 426 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); 385 427 if (!dev_data) ··· 402 448 struct i3c_hci *hci = to_i3c_hci(m); 403 449 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 404 450 405 - DBG(""); 406 - 407 451 if (hci->cmd == &mipi_i3c_hci_cmd_v1) 408 452 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dev_data->dat_idx, 409 453 dev->info.dyn_addr); ··· 413 461 struct i3c_master_controller *m = i3c_dev_get_master(dev); 414 462 struct i3c_hci *hci = to_i3c_hci(m); 415 463 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev); 416 - 417 - DBG(""); 418 464 419 465 i3c_dev_set_master_data(dev, NULL); 420 466 if (hci->cmd == &mipi_i3c_hci_cmd_v1) ··· 426 476 struct i3c_hci *hci = to_i3c_hci(m); 427 477 struct i3c_hci_dev_data *dev_data; 428 478 int ret; 429 - 430 - DBG(""); 431 479 432 480 if (hci->cmd != &mipi_i3c_hci_cmd_v1) 433 481 return 0; ··· 449 501 struct i3c_master_controller *m = i2c_dev_get_master(dev); 450 502 struct i3c_hci *hci = to_i3c_hci(m); 451 503 struct i3c_hci_dev_data *dev_data = i2c_dev_get_master_data(dev); 452 - 453 - DBG(""); 454 504 455 505 if (dev_data) { 456 506 i2c_dev_set_master_data(dev, NULL); ··· 537 591 538 592 val = reg_read(INTR_STATUS); 539 593 reg_write(INTR_STATUS, val); 540 - DBG("INTR_STATUS = %#x", val); 594 + dev_dbg(&hci->master.dev, "INTR_STATUS %#x", val); 541 595 542 596 if (val) 543 597 result = IRQ_HANDLED; ··· 587 641 } 588 642 589 643 hci->caps = reg_read(HC_CAPABILITIES); 590 - DBG("caps = %#x", hci->caps); 644 + dev_dbg(&hci->master.dev, "caps = %#x", hci->caps); 591 645 592 646 size_in_dwords = hci->version_major < 1 || 593 647 (hci->version_major == 1 && hci->version_minor < 1);

+55 -41

drivers/i3c/master/mipi-i3c-hci/dma.c

··· 14 14 #include <linux/errno.h> 15 15 #include <linux/i3c/master.h> 16 16 #include <linux/io.h> 17 + #include <linux/pci.h> 17 18 18 19 #include "hci.h" 19 20 #include "cmd.h" ··· 77 76 #define INTR_TRANSFER_COMPLETION BIT(11) 78 77 #define INTR_RING_OP BIT(10) 79 78 #define INTR_TRANSFER_ERR BIT(9) 80 - #define INTR_WARN_INS_STOP_MODE BIT(7) 81 79 #define INTR_IBI_RING_FULL BIT(6) 82 80 #define INTR_TRANSFER_ABORT BIT(5) 83 81 ··· 138 138 }; 139 139 140 140 struct hci_rings_data { 141 + struct device *sysdev; 141 142 unsigned int total; 142 143 struct hci_rh_data headers[] __counted_by(total); 143 144 }; ··· 166 165 rh_reg_write(IBI_SETUP, 0); 167 166 168 167 if (rh->xfer) 169 - dma_free_coherent(&hci->master.dev, 168 + dma_free_coherent(rings->sysdev, 170 169 rh->xfer_struct_sz * rh->xfer_entries, 171 170 rh->xfer, rh->xfer_dma); 172 171 if (rh->resp) 173 - dma_free_coherent(&hci->master.dev, 172 + dma_free_coherent(rings->sysdev, 174 173 rh->resp_struct_sz * rh->xfer_entries, 175 174 rh->resp, rh->resp_dma); 176 175 kfree(rh->src_xfers); 177 176 if (rh->ibi_status) 178 - dma_free_coherent(&hci->master.dev, 177 + dma_free_coherent(rings->sysdev, 179 178 rh->ibi_status_sz * rh->ibi_status_entries, 180 179 rh->ibi_status, rh->ibi_status_dma); 181 180 if (rh->ibi_data_dma) 182 - dma_unmap_single(&hci->master.dev, rh->ibi_data_dma, 181 + dma_unmap_single(rings->sysdev, rh->ibi_data_dma, 183 182 rh->ibi_chunk_sz * rh->ibi_chunks_total, 184 183 DMA_FROM_DEVICE); 185 184 kfree(rh->ibi_data); ··· 195 194 { 196 195 struct hci_rings_data *rings; 197 196 struct hci_rh_data *rh; 197 + struct device *sysdev; 198 198 u32 regval; 199 199 unsigned int i, nr_rings, xfers_sz, resps_sz; 200 200 unsigned int ibi_status_ring_sz, ibi_data_ring_sz; 201 201 int ret; 202 + 203 + /* 204 + * Set pointer to a physical device that does DMA and has IOMMU setup 205 + * done for it in case of enabled IOMMU and use it with the DMA API. 206 + * Here such device is either 207 + * "mipi-i3c-hci" platform device (OF/ACPI enumeration) parent or 208 + * grandparent (PCI enumeration). 209 + */ 210 + sysdev = hci->master.dev.parent; 211 + if (sysdev->parent && dev_is_pci(sysdev->parent)) 212 + sysdev = sysdev->parent; 202 213 203 214 regval = rhs_reg_read(CONTROL); 204 215 nr_rings = FIELD_GET(MAX_HEADER_COUNT_CAP, regval); ··· 226 213 return -ENOMEM; 227 214 hci->io_data = rings; 228 215 rings->total = nr_rings; 216 + rings->sysdev = sysdev; 229 217 230 218 regval = FIELD_PREP(MAX_HEADER_COUNT, rings->total); 231 219 rhs_reg_write(CONTROL, regval); ··· 248 234 regval = rh_reg_read(CR_SETUP); 249 235 rh->xfer_struct_sz = FIELD_GET(CR_XFER_STRUCT_SIZE, regval); 250 236 rh->resp_struct_sz = FIELD_GET(CR_RESP_STRUCT_SIZE, regval); 251 - DBG("xfer_struct_sz = %d, resp_struct_sz = %d", 252 - rh->xfer_struct_sz, rh->resp_struct_sz); 237 + dev_dbg(&hci->master.dev, 238 + "xfer_struct_sz = %d, resp_struct_sz = %d", 239 + rh->xfer_struct_sz, rh->resp_struct_sz); 253 240 xfers_sz = rh->xfer_struct_sz * rh->xfer_entries; 254 241 resps_sz = rh->resp_struct_sz * rh->xfer_entries; 255 242 256 - rh->xfer = dma_alloc_coherent(&hci->master.dev, xfers_sz, 243 + rh->xfer = dma_alloc_coherent(rings->sysdev, xfers_sz, 257 244 &rh->xfer_dma, GFP_KERNEL); 258 - rh->resp = dma_alloc_coherent(&hci->master.dev, resps_sz, 245 + rh->resp = dma_alloc_coherent(rings->sysdev, resps_sz, 259 246 &rh->resp_dma, GFP_KERNEL); 260 247 rh->src_xfers = 261 248 kmalloc_array(rh->xfer_entries, sizeof(*rh->src_xfers), ··· 278 263 INTR_TRANSFER_COMPLETION | 279 264 INTR_RING_OP | 280 265 INTR_TRANSFER_ERR | 281 - INTR_WARN_INS_STOP_MODE | 282 266 INTR_IBI_RING_FULL | 283 267 INTR_TRANSFER_ABORT); 284 268 ··· 309 295 ibi_data_ring_sz = rh->ibi_chunk_sz * rh->ibi_chunks_total; 310 296 311 297 rh->ibi_status = 312 - dma_alloc_coherent(&hci->master.dev, ibi_status_ring_sz, 298 + dma_alloc_coherent(rings->sysdev, ibi_status_ring_sz, 313 299 &rh->ibi_status_dma, GFP_KERNEL); 314 300 rh->ibi_data = kmalloc(ibi_data_ring_sz, GFP_KERNEL); 315 301 ret = -ENOMEM; 316 302 if (!rh->ibi_status || !rh->ibi_data) 317 303 goto err_out; 318 304 rh->ibi_data_dma = 319 - dma_map_single(&hci->master.dev, rh->ibi_data, 305 + dma_map_single(rings->sysdev, rh->ibi_data, 320 306 ibi_data_ring_sz, DMA_FROM_DEVICE); 321 - if (dma_mapping_error(&hci->master.dev, rh->ibi_data_dma)) { 307 + if (dma_mapping_error(rings->sysdev, rh->ibi_data_dma)) { 322 308 rh->ibi_data_dma = 0; 323 309 ret = -ENOMEM; 324 310 goto err_out; ··· 363 349 xfer = xfer_list + i; 364 350 if (!xfer->data) 365 351 continue; 366 - dma_unmap_single(&hci->master.dev, 367 - xfer->data_dma, xfer->data_len, 368 - xfer->rnw ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 352 + i3c_master_dma_unmap_single(xfer->dma); 369 353 } 370 354 } 371 355 ··· 374 362 struct hci_rh_data *rh; 375 363 unsigned int i, ring, enqueue_ptr; 376 364 u32 op1_val, op2_val; 377 - void *buf; 378 365 379 366 /* For now we only use ring 0 */ 380 367 ring = 0; ··· 384 373 for (i = 0; i < n; i++) { 385 374 struct hci_xfer *xfer = xfer_list + i; 386 375 u32 *ring_data = rh->xfer + rh->xfer_struct_sz * enqueue_ptr; 376 + enum dma_data_direction dir = xfer->rnw ? DMA_FROM_DEVICE : 377 + DMA_TO_DEVICE; 378 + bool need_bounce; 387 379 388 380 /* store cmd descriptor */ 389 381 *ring_data++ = xfer->cmd_desc[0]; ··· 405 391 406 392 /* 2nd and 3rd words of Data Buffer Descriptor Structure */ 407 393 if (xfer->data) { 408 - buf = xfer->bounce_buf ? xfer->bounce_buf : xfer->data; 409 - xfer->data_dma = 410 - dma_map_single(&hci->master.dev, 411 - buf, 412 - xfer->data_len, 413 - xfer->rnw ? 414 - DMA_FROM_DEVICE : 415 - DMA_TO_DEVICE); 416 - if (dma_mapping_error(&hci->master.dev, 417 - xfer->data_dma)) { 394 + need_bounce = device_iommu_mapped(rings->sysdev) && 395 + xfer->rnw && 396 + xfer->data_len != ALIGN(xfer->data_len, 4); 397 + xfer->dma = i3c_master_dma_map_single(rings->sysdev, 398 + xfer->data, 399 + xfer->data_len, 400 + need_bounce, 401 + dir); 402 + if (!xfer->dma) { 418 403 hci_dma_unmap_xfer(hci, xfer_list, i); 419 404 return -ENOMEM; 420 405 } 421 - *ring_data++ = lower_32_bits(xfer->data_dma); 422 - *ring_data++ = upper_32_bits(xfer->data_dma); 406 + *ring_data++ = lower_32_bits(xfer->dma->addr); 407 + *ring_data++ = upper_32_bits(xfer->dma->addr); 423 408 } else { 424 409 *ring_data++ = 0; 425 410 *ring_data++ = 0; ··· 524 511 ring_resp = rh->resp + rh->resp_struct_sz * done_ptr; 525 512 resp = *ring_resp; 526 513 tid = RESP_TID(resp); 527 - DBG("resp = 0x%08x", resp); 514 + dev_dbg(&hci->master.dev, "resp = 0x%08x", resp); 528 515 529 516 xfer = rh->src_xfers[done_ptr]; 530 517 if (!xfer) { 531 - DBG("orphaned ring entry"); 518 + dev_dbg(&hci->master.dev, "orphaned ring entry"); 532 519 } else { 533 520 hci_dma_unmap_xfer(hci, xfer, 1); 534 521 xfer->ring_entry = -1; ··· 599 586 600 587 static void hci_dma_process_ibi(struct i3c_hci *hci, struct hci_rh_data *rh) 601 588 { 589 + struct hci_rings_data *rings = hci->io_data; 602 590 struct i3c_dev_desc *dev; 603 591 struct i3c_hci_dev_data *dev_data; 604 592 struct hci_dma_dev_ibi_data *dev_ibi; ··· 631 617 632 618 ring_ibi_status = rh->ibi_status + rh->ibi_status_sz * ptr; 633 619 ibi_status = *ring_ibi_status; 634 - DBG("status = %#x", ibi_status); 620 + dev_dbg(&hci->master.dev, "status = %#x", ibi_status); 635 621 636 622 if (ibi_status_error) { 637 623 /* we no longer care */ ··· 659 645 660 646 if (last_ptr == -1) { 661 647 /* this IBI sequence is not yet complete */ 662 - DBG("no LAST_STATUS available (e=%d d=%d)", enq_ptr, deq_ptr); 648 + dev_dbg(&hci->master.dev, 649 + "no LAST_STATUS available (e=%d d=%d)", 650 + enq_ptr, deq_ptr); 663 651 return; 664 652 } 665 653 deq_ptr = last_ptr + 1; ··· 712 696 * rh->ibi_chunk_sz; 713 697 if (first_part > ibi_size) 714 698 first_part = ibi_size; 715 - dma_sync_single_for_cpu(&hci->master.dev, ring_ibi_data_dma, 699 + dma_sync_single_for_cpu(rings->sysdev, ring_ibi_data_dma, 716 700 first_part, DMA_FROM_DEVICE); 717 701 memcpy(slot->data, ring_ibi_data, first_part); 718 702 ··· 721 705 /* we wrap back to the start and copy remaining data */ 722 706 ring_ibi_data = rh->ibi_data; 723 707 ring_ibi_data_dma = rh->ibi_data_dma; 724 - dma_sync_single_for_cpu(&hci->master.dev, ring_ibi_data_dma, 708 + dma_sync_single_for_cpu(rings->sysdev, ring_ibi_data_dma, 725 709 ibi_size - first_part, DMA_FROM_DEVICE); 726 710 memcpy(slot->data + first_part, ring_ibi_data, 727 711 ibi_size - first_part); ··· 761 745 762 746 rh = &rings->headers[i]; 763 747 status = rh_reg_read(INTR_STATUS); 764 - DBG("rh%d status: %#x", i, status); 748 + dev_dbg(&hci->master.dev, "Ring %d: RH_INTR_STATUS %#x", 749 + i, status); 765 750 if (!status) 766 751 continue; 767 752 rh_reg_write(INTR_STATUS, status); ··· 778 761 u32 ring_status; 779 762 780 763 dev_notice_ratelimited(&hci->master.dev, 781 - "ring %d: Transfer Aborted\n", i); 764 + "Ring %d: Transfer Aborted\n", i); 782 765 mipi_i3c_hci_resume(hci); 783 766 ring_status = rh_reg_read(RING_STATUS); 784 767 if (!(ring_status & RING_STATUS_RUNNING) && ··· 796 779 RING_CTRL_RUN_STOP); 797 780 } 798 781 } 799 - if (status & INTR_WARN_INS_STOP_MODE) 800 - dev_warn_ratelimited(&hci->master.dev, 801 - "ring %d: Inserted Stop on Mode Change\n", i); 802 782 if (status & INTR_IBI_RING_FULL) 803 783 dev_err_ratelimited(&hci->master.dev, 804 - "ring %d: IBI Ring Full Condition\n", i); 784 + "Ring %d: IBI Ring Full Condition\n", i); 805 785 806 786 handled = true; 807 787 }

+7 -4

drivers/i3c/master/mipi-i3c-hci/ext_caps.c

··· 35 35 switch (hci->vendor_mipi_id) { 36 36 case MIPI_VENDOR_NXP: 37 37 hci->quirks |= HCI_QUIRK_RAW_CCC; 38 - DBG("raw CCC quirks set"); 38 + dev_dbg(&hci->master.dev, "raw CCC quirks set"); 39 39 break; 40 40 } 41 41 ··· 77 77 for (index = 0; index < entries; index++) { 78 78 u32 mode_entry = readl(base); 79 79 80 - DBG("mode %d: 0x%08x", index, mode_entry); 80 + dev_dbg(&hci->master.dev, "mode %d: 0x%08x", 81 + index, mode_entry); 81 82 /* TODO: will be needed when I3C core does more than SDR */ 82 83 base += 4; 83 84 } ··· 98 97 dev_info(&hci->master.dev, "available data rates:\n"); 99 98 for (index = 0; index < entries; index++) { 100 99 rate_entry = readl(base); 101 - DBG("entry %d: 0x%08x", index, rate_entry); 100 + dev_dbg(&hci->master.dev, "entry %d: 0x%08x", 101 + index, rate_entry); 102 102 rate = FIELD_GET(XFERRATE_ACTUAL_RATE_KHZ, rate_entry); 103 103 rate_id = FIELD_GET(XFERRATE_RATE_ID, rate_entry); 104 104 mode_id = FIELD_GET(XFERRATE_MODE_ID, rate_entry); ··· 270 268 cap_header = readl(curr_cap); 271 269 cap_id = FIELD_GET(CAP_HEADER_ID, cap_header); 272 270 cap_length = FIELD_GET(CAP_HEADER_LENGTH, cap_header); 273 - DBG("id=0x%02x length=%d", cap_id, cap_length); 271 + dev_dbg(&hci->master.dev, "id=0x%02x length=%d", 272 + cap_id, cap_length); 274 273 if (!cap_length) 275 274 break; 276 275 if (curr_cap + cap_length * 4 >= end) {

+1 -5

drivers/i3c/master/mipi-i3c-hci/hci.h

··· 12 12 13 13 #include <linux/io.h> 14 14 15 - /* Handy logging macro to save on line length */ 16 - #define DBG(x, ...) pr_devel("%s: " x "\n", __func__, ##__VA_ARGS__) 17 - 18 15 /* 32-bit word aware bit and mask macros */ 19 16 #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0) 20 17 #define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32) ··· 91 94 }; 92 95 struct { 93 96 /* DMA specific */ 94 - dma_addr_t data_dma; 95 - void *bounce_buf; 97 + struct i3c_dma *dma; 96 98 int ring_number; 97 99 int ring_entry; 98 100 };

+3

drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c

··· 124 124 } 125 125 126 126 static const struct pci_device_id mipi_i3c_hci_pci_devices[] = { 127 + /* Wildcat Lake-U */ 128 + { PCI_VDEVICE(INTEL, 0x4d7c), (kernel_ulong_t)&intel_info}, 129 + { PCI_VDEVICE(INTEL, 0x4d6f), (kernel_ulong_t)&intel_info}, 127 130 /* Panther Lake-H */ 128 131 { PCI_VDEVICE(INTEL, 0xe37c), (kernel_ulong_t)&intel_info}, 129 132 { PCI_VDEVICE(INTEL, 0xe36f), (kernel_ulong_t)&intel_info},

+43 -32

drivers/i3c/master/mipi-i3c-hci/pio.c

··· 213 213 pio_reg_write(INTR_SIGNAL_ENABLE, 0x0); 214 214 215 215 if (pio) { 216 - DBG("status = %#x/%#x", 217 - pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 216 + dev_dbg(&hci->master.dev, "status = %#x/%#x", 217 + pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 218 218 BUG_ON(pio->curr_xfer); 219 219 BUG_ON(pio->curr_rx); 220 220 BUG_ON(pio->curr_tx); ··· 226 226 227 227 static void hci_pio_write_cmd(struct i3c_hci *hci, struct hci_xfer *xfer) 228 228 { 229 - DBG("cmd_desc[%d] = 0x%08x", 0, xfer->cmd_desc[0]); 230 - DBG("cmd_desc[%d] = 0x%08x", 1, xfer->cmd_desc[1]); 229 + dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x", 230 + 0, xfer->cmd_desc[0]); 231 + dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x", 232 + 1, xfer->cmd_desc[1]); 231 233 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[0]); 232 234 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[1]); 233 235 if (hci->cmd == &mipi_i3c_hci_cmd_v2) { 234 - DBG("cmd_desc[%d] = 0x%08x", 2, xfer->cmd_desc[2]); 235 - DBG("cmd_desc[%d] = 0x%08x", 3, xfer->cmd_desc[3]); 236 + dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x", 237 + 2, xfer->cmd_desc[2]); 238 + dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x", 239 + 3, xfer->cmd_desc[3]); 236 240 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[2]); 237 241 pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[3]); 238 242 } ··· 258 254 nr_words = min(xfer->data_left / 4, pio->rx_thresh_size); 259 255 /* extract data from FIFO */ 260 256 xfer->data_left -= nr_words * 4; 261 - DBG("now %d left %d", nr_words * 4, xfer->data_left); 257 + dev_dbg(&hci->master.dev, "now %d left %d", 258 + nr_words * 4, xfer->data_left); 262 259 while (nr_words--) 263 260 *p++ = pio_reg_read(XFER_DATA_PORT); 264 261 } ··· 274 269 struct hci_xfer *xfer = pio->curr_rx; 275 270 u32 *p; 276 271 277 - DBG("%d remaining", count); 272 + dev_dbg(&hci->master.dev, "%d remaining", count); 278 273 279 274 p = xfer->data; 280 275 p += (xfer->data_len - xfer->data_left) / 4; ··· 283 278 unsigned int nr_words = count / 4; 284 279 /* extract data from FIFO */ 285 280 xfer->data_left -= nr_words * 4; 286 - DBG("now %d left %d", nr_words * 4, xfer->data_left); 281 + dev_dbg(&hci->master.dev, "now %d left %d", 282 + nr_words * 4, xfer->data_left); 287 283 while (nr_words--) 288 284 *p++ = pio_reg_read(XFER_DATA_PORT); 289 285 } ··· 327 321 nr_words = min(xfer->data_left / 4, pio->tx_thresh_size); 328 322 /* push data into the FIFO */ 329 323 xfer->data_left -= nr_words * 4; 330 - DBG("now %d left %d", nr_words * 4, xfer->data_left); 324 + dev_dbg(&hci->master.dev, "now %d left %d", 325 + nr_words * 4, xfer->data_left); 331 326 while (nr_words--) 332 327 pio_reg_write(XFER_DATA_PORT, *p++); 333 328 } ··· 343 336 */ 344 337 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) 345 338 return false; 346 - DBG("trailing %d", xfer->data_left); 339 + dev_dbg(&hci->master.dev, "trailing %d", xfer->data_left); 347 340 pio_reg_write(XFER_DATA_PORT, *p); 348 341 xfer->data_left = 0; 349 342 } ··· 488 481 u32 resp = pio_reg_read(RESPONSE_QUEUE_PORT); 489 482 unsigned int tid = RESP_TID(resp); 490 483 491 - DBG("resp = 0x%08x", resp); 484 + dev_dbg(&hci->master.dev, "resp = 0x%08x", resp); 492 485 if (tid != xfer->cmd_tid) { 493 486 dev_err(&hci->master.dev, 494 487 "response tid=%d when expecting %d\n", ··· 529 522 * still exists. 530 523 */ 531 524 if (pio->curr_rx == xfer) { 532 - DBG("short RX ?"); 525 + dev_dbg(&hci->master.dev, "short RX ?"); 533 526 pio->curr_rx = pio->curr_rx->next_data; 534 527 } else if (pio->curr_tx == xfer) { 535 - DBG("short TX ?"); 528 + dev_dbg(&hci->master.dev, "short TX ?"); 536 529 pio->curr_tx = pio->curr_tx->next_data; 537 530 } else if (xfer->data_left) { 538 - DBG("PIO xfer count = %d after response", 539 - xfer->data_left); 531 + dev_dbg(&hci->master.dev, 532 + "PIO xfer count = %d after response", 533 + xfer->data_left); 540 534 } 541 535 542 536 pio->curr_resp = xfer->next_resp; ··· 599 591 struct hci_xfer *prev_queue_tail; 600 592 int i; 601 593 602 - DBG("n = %d", n); 594 + dev_dbg(&hci->master.dev, "n = %d", n); 603 595 604 596 /* link xfer instances together and initialize data count */ 605 597 for (i = 0; i < n; i++) { ··· 619 611 if (!hci_pio_process_cmd(hci, pio)) 620 612 pio->enabled_irqs |= STAT_CMD_QUEUE_READY; 621 613 pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs); 622 - DBG("status = %#x/%#x", 623 - pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 614 + dev_dbg(&hci->master.dev, "status = %#x/%#x", 615 + pio_reg_read(INTR_STATUS), 616 + pio_reg_read(INTR_SIGNAL_ENABLE)); 624 617 } 625 618 spin_unlock_irq(&pio->lock); 626 619 return 0; ··· 695 686 int ret; 696 687 697 688 spin_lock_irq(&pio->lock); 698 - DBG("n=%d status=%#x/%#x", n, 699 - pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 700 - DBG("main_status = %#x/%#x", 701 - readl(hci->base_regs + 0x20), readl(hci->base_regs + 0x28)); 689 + dev_dbg(&hci->master.dev, "n=%d status=%#x/%#x", n, 690 + pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 691 + dev_dbg(&hci->master.dev, "main_status = %#x/%#x", 692 + readl(hci->base_regs + 0x20), readl(hci->base_regs + 0x28)); 702 693 703 694 ret = hci_pio_dequeue_xfer_common(hci, pio, xfer, n); 704 695 spin_unlock_irq(&pio->lock); ··· 742 733 mipi_i3c_hci_pio_reset(hci); 743 734 mipi_i3c_hci_resume(hci); 744 735 745 - DBG("status=%#x/%#x", 746 - pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 736 + dev_dbg(&hci->master.dev, "status=%#x/%#x", 737 + pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 747 738 } 748 739 749 740 static void hci_pio_set_ibi_thresh(struct i3c_hci *hci, ··· 758 749 if (regval != pio->reg_queue_thresh) { 759 750 pio_reg_write(QUEUE_THLD_CTRL, regval); 760 751 pio->reg_queue_thresh = regval; 761 - DBG("%d", thresh_val); 752 + dev_dbg(&hci->master.dev, "%d", thresh_val); 762 753 } 763 754 } 764 755 ··· 782 773 /* extract the data from the IBI port */ 783 774 nr_words = thresh_val; 784 775 ibi->seg_cnt -= nr_words * 4; 785 - DBG("now %d left %d", nr_words * 4, ibi->seg_cnt); 776 + dev_dbg(&hci->master.dev, "now %d left %d", 777 + nr_words * 4, ibi->seg_cnt); 786 778 while (nr_words--) 787 779 *p++ = pio_reg_read(IBI_PORT); 788 780 } ··· 801 791 hci_pio_set_ibi_thresh(hci, pio, 1); 802 792 if (!(pio_reg_read(INTR_STATUS) & STAT_IBI_STATUS_THLD)) 803 793 return false; 804 - DBG("trailing %d", ibi->seg_cnt); 794 + dev_dbg(&hci->master.dev, "trailing %d", ibi->seg_cnt); 805 795 data = pio_reg_read(IBI_PORT); 806 796 data = (__force u32) cpu_to_le32(data); 807 797 while (ibi->seg_cnt--) { ··· 830 820 */ 831 821 832 822 ibi_status = pio_reg_read(IBI_PORT); 833 - DBG("status = %#x", ibi_status); 823 + dev_dbg(&hci->master.dev, "status = %#x", ibi_status); 834 824 ibi->addr = FIELD_GET(IBI_TARGET_ADDR, ibi_status); 835 825 if (ibi_status & IBI_ERROR) { 836 826 dev_err(&hci->master.dev, "IBI error from %#x\n", ibi->addr); ··· 996 986 997 987 spin_lock(&pio->lock); 998 988 status = pio_reg_read(INTR_STATUS); 999 - DBG("(in) status: %#x/%#x", status, pio->enabled_irqs); 989 + dev_dbg(&hci->master.dev, "PIO_INTR_STATUS %#x/%#x", 990 + status, pio->enabled_irqs); 1000 991 status &= pio->enabled_irqs | STAT_LATENCY_WARNINGS; 1001 992 if (!status) { 1002 993 spin_unlock(&pio->lock); ··· 1034 1023 pio->enabled_irqs &= ~STAT_CMD_QUEUE_READY; 1035 1024 1036 1025 pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs); 1037 - DBG("(out) status: %#x/%#x", 1038 - pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 1026 + dev_dbg(&hci->master.dev, "PIO_INTR_STATUS %#x/%#x", 1027 + pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); 1039 1028 spin_unlock(&pio->lock); 1040 1029 return true; 1041 1030 }

+1 -1

drivers/i3c/master/renesas-i3c.c

··· 679 679 i3c_master_add_i3c_dev_locked(m, i3c->addrs[pos]); 680 680 } 681 681 682 - return ret < 0 ? ret : 0; 682 + return 0; 683 683 } 684 684 685 685 static bool renesas_i3c_supports_ccc_cmd(struct i3c_master_controller *m,

+26 -5

drivers/i3c/master/svc-i3c-master.c

··· 417 417 SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000); 418 418 if (ret) { 419 419 dev_err(master->dev, "Timeout when polling for COMPLETE\n"); 420 + i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 420 421 return ret; 421 422 } 422 423 ··· 518 517 */ 519 518 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); 520 519 521 - /* Acknowledge the incoming interrupt with the AUTOIBI mechanism */ 522 - writel(SVC_I3C_MCTRL_REQUEST_AUTO_IBI | 523 - SVC_I3C_MCTRL_IBIRESP_AUTO, 520 + /* 521 + * Write REQUEST_START_ADDR request to emit broadcast address for arbitration, 522 + * instend of using AUTO_IBI. 523 + * 524 + * Using AutoIBI request may cause controller to remain in AutoIBI state when 525 + * there is a glitch on SDA line (high->low->high). 526 + * 1. SDA high->low, raising an interrupt to execute IBI isr. 527 + * 2. SDA low->high. 528 + * 3. IBI isr writes an AutoIBI request. 529 + * 4. The controller will not start AutoIBI process because SDA is not low. 530 + * 5. IBIWON polling times out. 531 + * 6. Controller reamins in AutoIBI state and doesn't accept EmitStop request. 532 + */ 533 + writel(SVC_I3C_MCTRL_REQUEST_START_ADDR | 534 + SVC_I3C_MCTRL_TYPE_I3C | 535 + SVC_I3C_MCTRL_IBIRESP_MANUAL | 536 + SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE) | 537 + SVC_I3C_MCTRL_ADDR(I3C_BROADCAST_ADDR), 524 538 master->regs + SVC_I3C_MCTRL); 525 539 526 540 /* Wait for IBIWON, should take approximately 100us */ ··· 555 539 switch (ibitype) { 556 540 case SVC_I3C_MSTATUS_IBITYPE_IBI: 557 541 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); 558 - if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI)) 542 + if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI)) { 559 543 svc_i3c_master_nack_ibi(master); 560 - else 544 + } else { 545 + if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) 546 + svc_i3c_master_ack_ibi(master, true); 547 + else 548 + svc_i3c_master_ack_ibi(master, false); 561 549 svc_i3c_master_handle_ibi(master, dev); 550 + } 562 551 break; 563 552 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: 564 553 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN))

+26

include/linux/i3c/master.h

··· 558 558 #define i3c_bus_for_each_i3cdev(bus, dev) \ 559 559 list_for_each_entry(dev, &(bus)->devs.i3c, common.node) 560 560 561 + /** 562 + * struct i3c_dma - DMA transfer and mapping descriptor 563 + * @dev: device object of a device doing DMA 564 + * @buf: destination/source buffer for DMA 565 + * @len: length of transfer 566 + * @map_len: length of DMA mapping 567 + * @addr: mapped DMA address for a Host Controller Driver 568 + * @dir: DMA direction 569 + * @bounce_buf: an allocated bounce buffer if transfer needs it or NULL 570 + */ 571 + struct i3c_dma { 572 + struct device *dev; 573 + void *buf; 574 + size_t len; 575 + size_t map_len; 576 + dma_addr_t addr; 577 + enum dma_data_direction dir; 578 + void *bounce_buf; 579 + }; 580 + 561 581 int i3c_master_do_i2c_xfers(struct i3c_master_controller *master, 562 582 const struct i2c_msg *xfers, 563 583 int nxfers); ··· 595 575 int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, 596 576 u8 addr); 597 577 int i3c_master_do_daa(struct i3c_master_controller *master); 578 + struct i3c_dma *i3c_master_dma_map_single(struct device *dev, void *ptr, 579 + size_t len, bool force_bounce, 580 + enum dma_data_direction dir); 581 + void i3c_master_dma_unmap_single(struct i3c_dma *dma_xfer); 582 + DEFINE_FREE(i3c_master_dma_unmap_single, void *, 583 + if (_T) i3c_master_dma_unmap_single(_T)) 598 584 599 585 int i3c_master_set_info(struct i3c_master_controller *master, 600 586 const struct i3c_device_info *info);

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