Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'i2c-for-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang:
"Mostly DT bindings additions this time because Andi was super busy and
I also could only partly cover it.
- new ids for qcom-cci, mt65xx, exynos5, apple, tegra20, k1, i801
- drop support for already removed S3C2410
- introduce and use fwnode_for_each_child_node_scoped()
- mmt65xx: improve write-then-read transactions
- k1: various fixes around bus errors and resets
- usual share of cleanups, minor improvements, PM fixes...
at24 updates:
- add the compatible for Giantec GT24C256C to the device-tree
bindings"
* tag 'i2c-for-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (33 commits)
i2c: i801: Add support for Intel Wildcat Lake-U
dt-bindings: i2c: i2c-mt65xx: Add MediaTek MT8196/6991 compatibles
i2c: designware: Add disabling clocks when probe fails
i2c: designware: Fix clock issue when PM is disabled
i2c: busses: Fix some spelling errors
i2c: mux: Simplify boolean assignment in i2c_mux_alloc
i2c: designware: use dev_err_probe() when probing platform device
i2c: designware: convert to dev_err_probe() on request IRQ error
i2c: spacemit: ensure SDA is released after bus reset
i2c: spacemit: check SDA instead of SCL after bus reset
i2c: spacemit: disable SDA glitch fix to avoid restart delay
i2c: spacemit: remove stop function to avoid bus error
i2c: spacemit: ensure bus release check runs when wait_bus_idle() fails
i2c: mediatek: fix potential incorrect use of I2C_MASTER_WRRD
i2c: boardinfo: Annotate code used in init phase only
dt-bindings: i2c: i2c-mt65xx: Document MediaTek MT6878 I2C
dt-bindings: i2c: samsung,s3c2410-i2c: Drop S3C2410
i2c: s3c2410: Drop S3C2410 OF support
dt-bindings: i2c: spacemit,k1-i2c: Minor whitespace cleanup in example
dt-bindings: i2c: exynos5: add samsung,exynos8890-hsi2c compatible
...
+218
-115
+1
Documentation/devicetree/bindings/eeprom/at24.yaml
+1
Documentation/devicetree/bindings/eeprom/at24.yaml
+16
-11
Documentation/devicetree/bindings/i2c/apple,i2c.yaml
+16
-11
Documentation/devicetree/bindings/i2c/apple,i2c.yaml
···
20
20
21
21
properties:
22
22
compatible:
23
-
items:
24
-
- enum:
25
-
- apple,s5l8960x-i2c
26
-
- apple,t7000-i2c
27
-
- apple,s8000-i2c
28
-
- apple,t8010-i2c
29
-
- apple,t8015-i2c
30
-
- apple,t8103-i2c
31
-
- apple,t8112-i2c
32
-
- apple,t6000-i2c
33
-
- const: apple,i2c
23
+
oneOf:
24
+
- items:
25
+
- const: apple,t6020-i2c
26
+
- const: apple,t8103-i2c
27
+
- items:
28
+
- enum:
29
+
# Do not add additional SoC to this list.
30
+
- apple,s5l8960x-i2c
31
+
- apple,t7000-i2c
32
+
- apple,s8000-i2c
33
+
- apple,t8010-i2c
34
+
- apple,t8015-i2c
35
+
- apple,t8103-i2c
36
+
- apple,t8112-i2c
37
+
- apple,t6000-i2c
38
+
- const: apple,i2c
34
39
35
40
reg:
36
41
maxItems: 1
+5
Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
+5
Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
···
35
35
- const: samsung,exynos7-hsi2c
36
36
- items:
37
37
- enum:
38
+
- samsung,exynos8890-hsi2c
39
+
- const: samsung,exynos8895-hsi2c
40
+
- items:
41
+
- enum:
38
42
- google,gs101-hsi2c
39
43
- samsung,exynos2200-hsi2c
40
44
- samsung,exynos850-hsi2c
45
+
- samsung,exynos990-hsi2c
41
46
- const: samsung,exynosautov9-hsi2c
42
47
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
43
48
deprecated: true
+6
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
+6
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
···
52
52
- const: mediatek,mt8173-i2c
53
53
- items:
54
54
- enum:
55
+
- mediatek,mt6878-i2c
56
+
- mediatek,mt6991-i2c
57
+
- mediatek,mt8196-i2c
58
+
- const: mediatek,mt8188-i2c
59
+
- items:
60
+
- enum:
55
61
- mediatek,mt6893-i2c
56
62
- mediatek,mt8195-i2c
57
63
- const: mediatek,mt8192-i2c
+6
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+6
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
···
80
80
support for 64 KiB transactions whereas earlier chips supported no
81
81
more than 4 KiB per transactions.
82
82
const: nvidia,tegra194-i2c
83
+
- description: |
84
+
Tegra256 has 8 generic I2C controllers. The controllers are similar to
85
+
the previous generations, but have a different parent clock and hence
86
+
the timing parameters are configured differently.
87
+
const: nvidia,tegra256-i2c
83
88
84
89
reg:
85
90
maxItems: 1
···
191
186
contains:
192
187
enum:
193
188
- nvidia,tegra194-i2c
189
+
- nvidia,tegra256-i2c
194
190
then:
195
191
required:
196
192
- resets
+22
-2
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+22
-2
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
···
25
25
26
26
- items:
27
27
- enum:
28
+
- qcom,qcm2290-cci
29
+
- qcom,sa8775p-cci
28
30
- qcom,sc7280-cci
29
31
- qcom,sc8280xp-cci
30
32
- qcom,sdm670-cci
···
46
44
const: 0
47
45
48
46
clocks:
49
-
minItems: 3
47
+
minItems: 2
50
48
maxItems: 6
51
49
52
50
clock-names:
53
-
minItems: 3
51
+
minItems: 2
54
52
maxItems: 6
55
53
56
54
interrupts:
···
115
113
then:
116
114
properties:
117
115
clocks:
116
+
minItems: 3
118
117
maxItems: 3
119
118
clock-names:
120
119
items:
121
120
- const: camss_top_ahb
122
121
- const: cci_ahb
122
+
- const: cci
123
+
124
+
- if:
125
+
properties:
126
+
compatible:
127
+
contains:
128
+
enum:
129
+
- qcom,qcm2290-cci
130
+
then:
131
+
properties:
132
+
clocks:
133
+
minItems: 2
134
+
maxItems: 2
135
+
clock-names:
136
+
items:
137
+
- const: ahb
123
138
- const: cci
124
139
125
140
- if:
···
242
223
compatible:
243
224
contains:
244
225
enum:
226
+
- qcom,sa8775p-cci
245
227
- qcom,sm8550-cci
246
228
- qcom,sm8650-cci
247
229
- qcom,x1e80100-cci
-2
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
-2
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
···
13
13
compatible:
14
14
oneOf:
15
15
- enum:
16
-
- samsung,s3c2410-i2c
17
16
- samsung,s3c2440-i2c
18
17
# For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
19
18
- samsung,s3c2440-hdmiphy-i2c
···
92
93
compatible:
93
94
contains:
94
95
enum:
95
-
- samsung,s3c2410-i2c
96
96
- samsung,s3c2440-i2c
97
97
- samsung,s3c2440-hdmiphy-i2c
98
98
then:
+1
-1
Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
+1
-1
Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
+1
Documentation/i2c/busses/i2c-i801.rst
+1
Documentation/i2c/busses/i2c-i801.rst
+1
drivers/i2c/busses/Kconfig
+1
drivers/i2c/busses/Kconfig
+4
-5
drivers/i2c/busses/i2c-designware-master.c
+4
-5
drivers/i2c/busses/i2c-designware-master.c
···
1068
1068
if (!(dev->flags & ACCESS_POLLING)) {
1069
1069
ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
1070
1070
irq_flags, dev_name(dev->dev), dev);
1071
-
if (ret) {
1072
-
dev_err(dev->dev, "failure requesting irq %i: %d\n",
1073
-
dev->irq, ret);
1074
-
return ret;
1075
-
}
1071
+
if (ret)
1072
+
return dev_err_probe(dev->dev, ret,
1073
+
"failure requesting irq %i: %d\n",
1074
+
dev->irq, ret);
1076
1075
}
1077
1076
1078
1077
ret = i2c_dw_init_recovery_info(dev);
+10
-5
drivers/i2c/busses/i2c-designware-platdrv.c
+10
-5
drivers/i2c/busses/i2c-designware-platdrv.c
···
238
238
239
239
dev->rst = devm_reset_control_get_optional_exclusive(device, NULL);
240
240
if (IS_ERR(dev->rst))
241
-
return PTR_ERR(dev->rst);
241
+
return dev_err_probe(device, PTR_ERR(dev->rst), "failed to acquire reset\n");
242
242
243
243
reset_control_deassert(dev->rst);
244
244
···
247
247
goto exit_reset;
248
248
249
249
ret = i2c_dw_probe_lock_support(dev);
250
-
if (ret)
250
+
if (ret) {
251
+
ret = dev_err_probe(device, ret, "failed to probe lock support\n");
251
252
goto exit_reset;
253
+
}
252
254
253
255
i2c_dw_configure(dev);
254
256
255
257
/* Optional interface clock */
256
258
dev->pclk = devm_clk_get_optional(device, "pclk");
257
259
if (IS_ERR(dev->pclk)) {
258
-
ret = PTR_ERR(dev->pclk);
260
+
ret = dev_err_probe(device, PTR_ERR(dev->pclk), "failed to acquire pclk\n");
259
261
goto exit_reset;
260
262
}
261
263
262
264
dev->clk = devm_clk_get_optional(device, NULL);
263
265
if (IS_ERR(dev->clk)) {
264
-
ret = PTR_ERR(dev->clk);
266
+
ret = dev_err_probe(device, PTR_ERR(dev->clk), "failed to acquire clock\n");
265
267
goto exit_reset;
266
268
}
267
269
···
316
314
317
315
exit_probe:
318
316
dw_i2c_plat_pm_cleanup(dev);
317
+
i2c_dw_prepare_clk(dev, false);
319
318
exit_reset:
320
319
reset_control_assert(dev->rst);
321
320
return ret;
···
334
331
i2c_dw_disable(dev);
335
332
336
333
pm_runtime_dont_use_autosuspend(device);
337
-
pm_runtime_put_sync(device);
334
+
pm_runtime_put_noidle(device);
338
335
dw_i2c_plat_pm_cleanup(dev);
336
+
337
+
i2c_dw_prepare_clk(dev, false);
339
338
340
339
i2c_dw_remove_lock_support(dev);
341
340
+4
-5
drivers/i2c/busses/i2c-designware-slave.c
+4
-5
drivers/i2c/busses/i2c-designware-slave.c
···
266
266
267
267
ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave,
268
268
IRQF_SHARED, dev_name(dev->dev), dev);
269
-
if (ret) {
270
-
dev_err(dev->dev, "failure requesting IRQ %i: %d\n",
271
-
dev->irq, ret);
272
-
return ret;
273
-
}
269
+
if (ret)
270
+
return dev_err_probe(dev->dev, ret,
271
+
"failure requesting IRQ %i: %d\n",
272
+
dev->irq, ret);
274
273
275
274
ret = i2c_add_numbered_adapter(adap);
276
275
if (ret)
+1
-1
drivers/i2c/busses/i2c-hix5hd2.c
+1
-1
drivers/i2c/busses/i2c-hix5hd2.c
···
339
339
ret = priv->state;
340
340
341
341
/*
342
-
* If this is the last message to be transfered (stop == 1)
342
+
* If this is the last message to be transferred (stop == 1)
343
343
* Then check if the bus can be brought back to idle.
344
344
*/
345
345
if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
+3
drivers/i2c/busses/i2c-i801.c
+3
drivers/i2c/busses/i2c-i801.c
···
83
83
* Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes
84
84
* Panther Lake-H (SOC) 0xe322 32 hard yes yes yes
85
85
* Panther Lake-P (SOC) 0xe422 32 hard yes yes yes
86
+
* Wildcat Lake-U (SOC) 0x4d22 32 hard yes yes yes
86
87
*
87
88
* Features supported by this driver:
88
89
* Software PEC no
···
237
236
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
238
237
#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
239
238
#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
239
+
#define PCI_DEVICE_ID_INTEL_WILDCAT_LAKE_U_SMBUS 0x4d22
240
240
#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
241
241
#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
242
242
#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
···
1058
1056
{ PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1059
1057
{ PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1060
1058
{ PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1059
+
{ PCI_DEVICE_DATA(INTEL, WILDCAT_LAKE_U_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1061
1060
{ 0, }
1062
1061
};
1063
1062
+45
-26
drivers/i2c/busses/i2c-k1.c
+45
-26
drivers/i2c/busses/i2c-k1.c
···
3
3
* Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com>
4
4
*/
5
5
6
+
#include <linux/bitfield.h>
6
7
#include <linux/clk.h>
7
8
#include <linux/i2c.h>
8
9
#include <linux/iopoll.h>
···
15
14
#define SPACEMIT_ICR 0x0 /* Control register */
16
15
#define SPACEMIT_ISR 0x4 /* Status register */
17
16
#define SPACEMIT_IDBR 0xc /* Data buffer register */
17
+
#define SPACEMIT_IRCR 0x18 /* Reset cycle counter */
18
18
#define SPACEMIT_IBMR 0x1c /* Bus monitor register */
19
19
20
20
/* SPACEMIT_ICR register fields */
···
27
25
#define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */
28
26
/* Bit 9 is reserved */
29
27
#define SPACEMIT_CR_UR BIT(10) /* unit reset */
30
-
/* Bits 11-12 are reserved */
28
+
#define SPACEMIT_CR_RSTREQ BIT(11) /* i2c bus reset request */
29
+
/* Bit 12 is reserved */
31
30
#define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */
32
31
#define SPACEMIT_CR_IUE BIT(14) /* unit enable */
33
32
/* Bits 15-17 are reserved */
···
79
76
SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \
80
77
SPACEMIT_SR_ALD)
81
78
79
+
#define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fix */
80
+
/* the cycles of SCL during bus reset */
81
+
#define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0)
82
+
82
83
/* SPACEMIT_IBMR register fields */
83
84
#define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */
84
85
#define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */
···
94
87
#define SPACEMIT_I2C_MAX_FAST_MODE_FREQ 400000 /* Hz */
95
88
96
89
#define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD)
90
+
91
+
#define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9
97
92
98
93
enum spacemit_i2c_state {
99
94
SPACEMIT_STATE_IDLE,
···
169
160
static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c)
170
161
{
171
162
u32 status;
163
+
u8 clk_cnt;
172
164
173
165
/* if bus is locked, reset unit. 0: locked */
174
166
status = readl(i2c->base + SPACEMIT_IBMR);
···
179
169
spacemit_i2c_reset(i2c);
180
170
usleep_range(10, 20);
181
171
182
-
/* check scl status again */
172
+
for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) {
173
+
status = readl(i2c->base + SPACEMIT_IBMR);
174
+
if (status & SPACEMIT_BMR_SDA)
175
+
return;
176
+
177
+
/* There's nothing left to save here, we are about to exit */
178
+
writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1),
179
+
i2c->base + SPACEMIT_IRCR);
180
+
writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR);
181
+
usleep_range(20, 30);
182
+
}
183
+
184
+
/* check sda again here */
183
185
status = readl(i2c->base + SPACEMIT_IBMR);
184
-
if (!(status & SPACEMIT_BMR_SCL))
186
+
if (!(status & SPACEMIT_BMR_SDA))
185
187
dev_warn_ratelimited(i2c->dev, "unit reset failed\n");
186
188
}
187
189
···
259
237
val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE;
260
238
261
239
writel(val, i2c->base + SPACEMIT_ICR);
240
+
241
+
/*
242
+
* The glitch fix in the K1 I2C controller introduces a delay
243
+
* on restart signals, so we disable the fix here.
244
+
*/
245
+
val = readl(i2c->base + SPACEMIT_IRCR);
246
+
val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX;
247
+
writel(val, i2c->base + SPACEMIT_IRCR);
262
248
}
263
249
264
250
static inline void
···
294
264
val = readl(i2c->base + SPACEMIT_ICR);
295
265
val &= ~SPACEMIT_CR_STOP;
296
266
val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE;
297
-
writel(val, i2c->base + SPACEMIT_ICR);
298
-
}
299
-
300
-
static void spacemit_i2c_stop(struct spacemit_i2c_dev *i2c)
301
-
{
302
-
u32 val;
303
-
304
-
val = readl(i2c->base + SPACEMIT_ICR);
305
-
val |= SPACEMIT_CR_STOP | SPACEMIT_CR_ALDIE | SPACEMIT_CR_TB;
306
-
307
-
if (i2c->read)
308
-
val |= SPACEMIT_CR_ACKNAK;
309
-
310
267
writel(val, i2c->base + SPACEMIT_ICR);
311
268
}
312
269
···
429
412
430
413
val = readl(i2c->base + SPACEMIT_ICR);
431
414
val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START);
432
-
writel(val, i2c->base + SPACEMIT_ICR);
433
415
434
416
switch (i2c->state) {
435
417
case SPACEMIT_STATE_START:
···
445
429
}
446
430
447
431
if (i2c->state != SPACEMIT_STATE_IDLE) {
432
+
val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE;
433
+
448
434
if (spacemit_i2c_is_last_msg(i2c)) {
449
435
/* trigger next byte with stop */
450
-
spacemit_i2c_stop(i2c);
451
-
} else {
452
-
/* trigger next byte */
453
-
val |= SPACEMIT_CR_ALDIE | SPACEMIT_CR_TB;
454
-
writel(val, i2c->base + SPACEMIT_ICR);
436
+
val |= SPACEMIT_CR_STOP;
437
+
438
+
if (i2c->read)
439
+
val |= SPACEMIT_CR_ACKNAK;
455
440
}
441
+
writel(val, i2c->base + SPACEMIT_ICR);
456
442
}
457
443
458
444
err_out:
···
494
476
spacemit_i2c_enable(i2c);
495
477
496
478
ret = spacemit_i2c_wait_bus_idle(i2c);
497
-
if (!ret)
479
+
if (!ret) {
498
480
ret = spacemit_i2c_xfer_msg(i2c);
499
-
else if (ret < 0)
500
-
dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret);
501
-
else
481
+
if (ret < 0)
482
+
dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret);
483
+
} else {
502
484
spacemit_i2c_check_bus_release(i2c);
485
+
}
503
486
504
487
spacemit_i2c_disable(i2c);
505
488
+10
-7
drivers/i2c/busses/i2c-mt65xx.c
+10
-7
drivers/i2c/busses/i2c-mt65xx.c
···
1243
1243
{
1244
1244
int ret;
1245
1245
int left_num = num;
1246
+
bool write_then_read_en = false;
1246
1247
struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1247
1248
1248
1249
ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
···
1257
1256
if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1258
1257
msgs[0].addr == msgs[1].addr) {
1259
1258
i2c->auto_restart = 0;
1259
+
write_then_read_en = true;
1260
1260
}
1261
1261
}
1262
1262
···
1282
1280
else
1283
1281
i2c->op = I2C_MASTER_WR;
1284
1282
1285
-
if (!i2c->auto_restart) {
1286
-
if (num > 1) {
1287
-
/* combined two messages into one transaction */
1288
-
i2c->op = I2C_MASTER_WRRD;
1289
-
left_num--;
1290
-
}
1283
+
if (write_then_read_en) {
1284
+
/* combined two messages into one transaction */
1285
+
i2c->op = I2C_MASTER_WRRD;
1286
+
left_num--;
1291
1287
}
1292
1288
1293
1289
/* always use DMA mode. */
···
1293
1293
if (ret < 0)
1294
1294
goto err_exit;
1295
1295
1296
-
msgs++;
1296
+
if (i2c->op == I2C_MASTER_WRRD)
1297
+
msgs += 2;
1298
+
else
1299
+
msgs++;
1297
1300
}
1298
1301
/* the return value is number of executed messages */
1299
1302
ret = num;
-1
drivers/i2c/busses/i2c-s3c2410.c
-1
drivers/i2c/busses/i2c-s3c2410.c
···
138
138
139
139
#ifdef CONFIG_OF
140
140
static const struct of_device_id s3c24xx_i2c_match[] = {
141
-
{ .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
142
141
{ .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
143
142
{ .compatible = "samsung,s3c2440-hdmiphy-i2c",
144
143
.data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
+1
-1
drivers/i2c/busses/i2c-sprd.c
+1
-1
drivers/i2c/busses/i2c-sprd.c
···
425
425
* If we did not get one ACK from target when writing data, then we
426
426
* should finish this transmission since we got some errors.
427
427
*
428
-
* When writing data, if i2c_tran == 0 which means we have writen
428
+
* When writing data, if i2c_tran == 0 which means we have written
429
429
* done all data, then we can finish this transmission.
430
430
*
431
431
* When reading data, if conut < rx fifo full threshold, which
+1
-1
drivers/i2c/busses/i2c-st.c
+1
-1
drivers/i2c/busses/i2c-st.c
···
152
152
/**
153
153
* struct st_i2c_client - client specific data
154
154
* @addr: 8-bit target addr, including r/w bit
155
-
* @count: number of bytes to be transfered
155
+
* @count: number of bytes to be transferred
156
156
* @xfered: number of bytes already transferred
157
157
* @buf: data buffer
158
158
* @result: result of the transfer
+26
drivers/i2c/busses/i2c-tegra.c
+26
drivers/i2c/busses/i2c-tegra.c
···
1649
1649
.has_interface_timing_reg = true,
1650
1650
};
1651
1651
1652
+
static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
1653
+
.has_continue_xfer_support = true,
1654
+
.has_per_pkt_xfer_complete_irq = true,
1655
+
.clk_divisor_hs_mode = 7,
1656
+
.clk_divisor_std_mode = 0x7a,
1657
+
.clk_divisor_fast_mode = 0x40,
1658
+
.clk_divisor_fast_plus_mode = 0x19,
1659
+
.has_config_load_reg = true,
1660
+
.has_multi_master_mode = true,
1661
+
.has_slcg_override_reg = true,
1662
+
.has_mst_fifo = true,
1663
+
.has_mst_reset = true,
1664
+
.quirks = &tegra194_i2c_quirks,
1665
+
.supports_bus_clear = true,
1666
+
.has_apb_dma = false,
1667
+
.tlow_std_mode = 0x8,
1668
+
.thigh_std_mode = 0x7,
1669
+
.tlow_fast_fastplus_mode = 0x3,
1670
+
.thigh_fast_fastplus_mode = 0x3,
1671
+
.setup_hold_time_std_mode = 0x08080808,
1672
+
.setup_hold_time_fast_fast_plus_mode = 0x02020202,
1673
+
.setup_hold_time_hs_mode = 0x090909,
1674
+
.has_interface_timing_reg = true,
1675
+
};
1676
+
1652
1677
static const struct of_device_id tegra_i2c_of_match[] = {
1678
+
{ .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
1653
1679
{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1654
1680
{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1655
1681
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
+1
-1
drivers/i2c/busses/i2c-viperboard.c
+1
-1
drivers/i2c/busses/i2c-viperboard.c
+2
-2
drivers/i2c/i2c-boardinfo.c
+2
-2
drivers/i2c/i2c-boardinfo.c
···
22
22
LIST_HEAD(__i2c_board_list);
23
23
EXPORT_SYMBOL_GPL(__i2c_board_list);
24
24
25
-
int __i2c_first_dynamic_bus_num;
25
+
int __i2c_first_dynamic_bus_num __ro_after_init;
26
26
EXPORT_SYMBOL_GPL(__i2c_first_dynamic_bus_num);
27
27
28
28
···
48
48
* The board info passed can safely be __initdata, but be careful of embedded
49
49
* pointers (for platform_data, functions, etc) since that won't be copied.
50
50
*/
51
-
int i2c_register_board_info(int busnum, struct i2c_board_info const *info, unsigned len)
51
+
int __init i2c_register_board_info(int busnum, struct i2c_board_info const *info, unsigned len)
52
52
{
53
53
int status;
54
54
+3
-6
drivers/i2c/i2c-core-base.c
+3
-6
drivers/i2c/i2c-core-base.c
···
573
573
goto err_clear_wakeup_irq;
574
574
575
575
do_power_on = !i2c_acpi_waive_d0_probe(dev);
576
-
status = dev_pm_domain_attach(&client->dev, do_power_on ? PD_FLAG_ATTACH_POWER_ON : 0);
576
+
status = dev_pm_domain_attach(&client->dev, PD_FLAG_DETACH_POWER_OFF |
577
+
(do_power_on ? PD_FLAG_ATTACH_POWER_ON : 0));
577
578
if (status)
578
579
goto err_clear_wakeup_irq;
579
580
···
582
581
GFP_KERNEL);
583
582
if (!client->devres_group_id) {
584
583
status = -ENOMEM;
585
-
goto err_detach_pm_domain;
584
+
goto err_clear_wakeup_irq;
586
585
}
587
586
588
587
client->debugfs = debugfs_create_dir(dev_name(&client->dev),
···
609
608
err_release_driver_resources:
610
609
debugfs_remove_recursive(client->debugfs);
611
610
devres_release_group(&client->dev, client->devres_group_id);
612
-
err_detach_pm_domain:
613
-
dev_pm_domain_detach(&client->dev, do_power_on);
614
611
err_clear_wakeup_irq:
615
612
dev_pm_clear_wake_irq(&client->dev);
616
613
device_init_wakeup(&client->dev, false);
···
634
635
debugfs_remove_recursive(client->debugfs);
635
636
636
637
devres_release_group(&client->dev, client->devres_group_id);
637
-
638
-
dev_pm_domain_detach(&client->dev, true);
639
638
640
639
dev_pm_clear_wake_irq(&client->dev);
641
640
device_init_wakeup(&client->dev, false);
+1
-2
drivers/i2c/i2c-core-slave.c
+1
-2
drivers/i2c/i2c-core-slave.c
···
112
112
struct fwnode_handle *fwnode = dev_fwnode(dev);
113
113
114
114
if (is_of_node(fwnode)) {
115
-
struct fwnode_handle *child __free(fwnode_handle) = NULL;
116
115
u32 reg;
117
116
118
-
fwnode_for_each_child_node(fwnode, child) {
117
+
fwnode_for_each_child_node_scoped(fwnode, child) {
119
118
fwnode_property_read_u32(child, "reg", ®);
120
119
if (reg & I2C_OWN_SLAVE_ADDRESS)
121
120
return true;
+3
-6
drivers/i2c/i2c-mux.c
+3
-6
drivers/i2c/i2c-mux.c
···
241
241
242
242
muxc->parent = parent;
243
243
muxc->dev = dev;
244
-
if (flags & I2C_MUX_LOCKED)
245
-
muxc->mux_locked = true;
246
-
if (flags & I2C_MUX_ARBITRATOR)
247
-
muxc->arbitrator = true;
248
-
if (flags & I2C_MUX_GATE)
249
-
muxc->gate = true;
244
+
muxc->mux_locked = !!(flags & I2C_MUX_LOCKED);
245
+
muxc->arbitrator = !!(flags & I2C_MUX_ARBITRATOR);
246
+
muxc->gate = !!(flags & I2C_MUX_GATE);
250
247
muxc->select = select;
251
248
muxc->deselect = deselect;
252
249
muxc->max_adapters = max_adapters;
+6
-6
drivers/i2c/muxes/i2c-mux-pca9541.c
+6
-6
drivers/i2c/muxes/i2c-mux-pca9541.c
···
63
63
#define mybus(x) (!((x) & MYBUS) || ((x) & MYBUS) == MYBUS)
64
64
#define busoff(x) (!((x) & BUSON) || ((x) & BUSON) == BUSON)
65
65
66
-
/* arbitration timeouts, in jiffies */
67
-
#define ARB_TIMEOUT (HZ / 8) /* 125 ms until forcing bus ownership */
68
-
#define ARB2_TIMEOUT (HZ / 4) /* 250 ms until acquisition failure */
69
-
70
66
/* arbitration retry delays, in us */
71
67
#define SELECT_DELAY_SHORT 50
72
68
#define SELECT_DELAY_LONG 1000
···
225
229
*/
226
230
data->select_timeout = SELECT_DELAY_LONG;
227
231
if (time_is_before_eq_jiffies(data->arb_timeout)) {
232
+
dev_warn(&client->dev,
233
+
"Arbitration timeout on I2C bus, forcing bus ownership\n");
234
+
228
235
/* Time is up, take the bus and reset it. */
229
236
pca9541_reg_write(client,
230
237
PCA9541_CONTROL,
···
250
251
struct pca9541 *data = i2c_mux_priv(muxc);
251
252
struct i2c_client *client = data->client;
252
253
int ret;
253
-
unsigned long timeout = jiffies + ARB2_TIMEOUT;
254
+
unsigned long timeout = jiffies + (2 * client->adapter->timeout);
254
255
/* give up after this time */
255
256
256
-
data->arb_timeout = jiffies + ARB_TIMEOUT;
257
+
data->arb_timeout = jiffies + client->adapter->timeout;
257
258
/* force bus ownership after this time */
258
259
259
260
do {
···
266
267
else
267
268
msleep(data->select_timeout / 1000);
268
269
} while (time_is_after_eq_jiffies(timeout));
270
+
dev_warn(&client->dev, "Failed to acquire I2C bus, timed out\n");
269
271
270
272
return -ETIMEDOUT;
271
273
}
+27
-23
drivers/i2c/muxes/i2c-mux-pca954x.c
+27
-23
drivers/i2c/muxes/i2c-mux-pca954x.c
···
118
118
raw_spinlock_t lock;
119
119
struct regulator *supply;
120
120
121
-
struct gpio_desc *reset_gpio;
122
121
struct reset_control *reset_cont;
123
122
};
124
123
···
315
316
return 1 << chan;
316
317
}
317
318
319
+
static void pca954x_reset_assert(struct pca954x *data)
320
+
{
321
+
if (data->reset_cont)
322
+
reset_control_assert(data->reset_cont);
323
+
}
324
+
325
+
static void pca954x_reset_deassert(struct pca954x *data)
326
+
{
327
+
if (data->reset_cont)
328
+
reset_control_deassert(data->reset_cont);
329
+
}
330
+
331
+
static void pca954x_reset_mux(struct pca954x *data)
332
+
{
333
+
pca954x_reset_assert(data);
334
+
udelay(1);
335
+
pca954x_reset_deassert(data);
336
+
}
337
+
318
338
static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan)
319
339
{
320
340
struct pca954x *data = i2c_mux_priv(muxc);
···
347
329
ret = pca954x_reg_write(muxc->parent, client, regval);
348
330
data->last_chan = ret < 0 ? 0 : regval;
349
331
}
332
+
if (ret == -ETIMEDOUT && data->reset_cont)
333
+
pca954x_reset_mux(data);
350
334
351
335
return ret;
352
336
}
···
358
338
struct pca954x *data = i2c_mux_priv(muxc);
359
339
struct i2c_client *client = data->client;
360
340
s32 idle_state;
341
+
int ret = 0;
361
342
362
343
idle_state = READ_ONCE(data->idle_state);
363
344
if (idle_state >= 0)
···
368
347
if (idle_state == MUX_IDLE_DISCONNECT) {
369
348
/* Deselect active channel */
370
349
data->last_chan = 0;
371
-
return pca954x_reg_write(muxc->parent, client,
372
-
data->last_chan);
350
+
ret = pca954x_reg_write(muxc->parent, client,
351
+
data->last_chan);
352
+
if (ret == -ETIMEDOUT && data->reset_cont)
353
+
pca954x_reset_mux(data);
373
354
}
374
355
375
356
/* otherwise leave as-is */
···
550
527
if (IS_ERR(data->reset_cont))
551
528
return dev_err_probe(dev, PTR_ERR(data->reset_cont),
552
529
"Failed to get reset\n");
553
-
else if (data->reset_cont)
554
-
return 0;
555
-
556
-
/*
557
-
* fallback to legacy reset-gpios
558
-
*/
559
-
data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
560
-
if (IS_ERR(data->reset_gpio)) {
561
-
return dev_err_probe(dev, PTR_ERR(data->reset_gpio),
562
-
"Failed to get reset gpio");
563
-
}
564
530
565
531
return 0;
566
-
}
567
-
568
-
static void pca954x_reset_deassert(struct pca954x *data)
569
-
{
570
-
if (data->reset_cont)
571
-
reset_control_deassert(data->reset_cont);
572
-
else
573
-
gpiod_set_value_cansleep(data->reset_gpio, 0);
574
532
}
575
533
576
534
/*
···
593
589
if (ret)
594
590
goto fail_cleanup;
595
591
596
-
if (data->reset_cont || data->reset_gpio) {
592
+
if (data->reset_cont) {
597
593
udelay(1);
598
594
pca954x_reset_deassert(data);
599
595
/* Give the chip some time to recover. */
+1
-1
include/linux/i2c.h
+1
-1
include/linux/i2c.h
+10
include/linux/property.h
+10
include/linux/property.h
···
176
176
for (child = fwnode_get_next_available_child_node(fwnode, NULL); child;\
177
177
child = fwnode_get_next_available_child_node(fwnode, child))
178
178
179
+
#define fwnode_for_each_child_node_scoped(fwnode, child) \
180
+
for (struct fwnode_handle *child __free(fwnode_handle) = \
181
+
fwnode_get_next_child_node(fwnode, NULL); \
182
+
child; child = fwnode_get_next_child_node(fwnode, child))
183
+
184
+
#define fwnode_for_each_available_child_node_scoped(fwnode, child) \
185
+
for (struct fwnode_handle *child __free(fwnode_handle) = \
186
+
fwnode_get_next_available_child_node(fwnode, NULL); \
187
+
child; child = fwnode_get_next_available_child_node(fwnode, child))
188
+
179
189
struct fwnode_handle *device_get_next_child_node(const struct device *dev,
180
190
struct fwnode_handle *child);
181
191