Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: add the GCC driver for sa8775p
Add support for the Global Clock Controller found in the QTI SA8775P
platforms.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
[Bartosz: made the driver ready for upstream]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Moved to core_initcall(), per request of Konrad]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117180429.305266-3-brgl@bgdev.pl
authored by
Shazad Hussain
and committed by
Bjorn Andersson
08c51ceb
0fff9fa0
+4815
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
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Say Y if you want to support display devices and functionality such as
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411
splash screen.
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+
config SA_GCC_8775P
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+
tristate "SA8775 Global Clock Controller"
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select QCOM_GDSC
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depends on COMMON_CLK_QCOM
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help
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Support for the global clock controller on SA8775 devices.
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Say Y if you want to use peripheral devices such as UART, SPI,
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I2C, USB, UFS, SDCC, etc.
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+
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422
config SC_GCC_7180
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tristate "SC7180 Global Clock Controller"
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select QCOM_GDSC
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
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obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
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obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
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+
obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o
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obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
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obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
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obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
+4805
drivers/clk/qcom/gcc-sa8775p.c
+4805
drivers/clk/qcom/gcc-sa8775p.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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+
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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+
* Copyright (c) 2023, Linaro Limited
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+
*/
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+
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+
#include <linux/clk.h>
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+
#include <linux/clk-provider.h>
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+
#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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+
#include <linux/regmap.h>
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+
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+
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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+
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+
#include "clk-alpha-pll.h"
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+
#include "clk-branch.h"
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+
#include "clk-rcg.h"
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#include "clk-regmap.h"
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+
#include "clk-regmap-divider.h"
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+
#include "clk-regmap-mux.h"
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+
#include "clk-regmap-phy-mux.h"
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+
#include "common.h"
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+
#include "gdsc.h"
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+
#include "reset.h"
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+
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+
/* Need to match the order of clocks in DT binding */
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+
enum {
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DT_BI_TCXO,
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DT_SLEEP_CLK,
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+
DT_UFS_PHY_RX_SYMBOL_0_CLK,
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+
DT_UFS_PHY_RX_SYMBOL_1_CLK,
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+
DT_UFS_PHY_TX_SYMBOL_0_CLK,
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+
DT_UFS_CARD_RX_SYMBOL_0_CLK,
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+
DT_UFS_CARD_RX_SYMBOL_1_CLK,
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+
DT_UFS_CARD_TX_SYMBOL_0_CLK,
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+
DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
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+
DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK,
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+
DT_PCIE_0_PIPE_CLK,
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+
DT_PCIE_1_PIPE_CLK,
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+
DT_PCIE_PHY_AUX_CLK,
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+
DT_RXC0_REF_CLK,
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DT_RXC1_REF_CLK,
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+
};
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+
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enum {
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P_BI_TCXO,
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P_GCC_GPLL0_OUT_EVEN,
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P_GCC_GPLL0_OUT_MAIN,
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P_GCC_GPLL1_OUT_MAIN,
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+
P_GCC_GPLL4_OUT_MAIN,
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+
P_GCC_GPLL5_OUT_MAIN,
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+
P_GCC_GPLL7_OUT_MAIN,
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+
P_GCC_GPLL9_OUT_MAIN,
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+
P_PCIE_0_PIPE_CLK,
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+
P_PCIE_1_PIPE_CLK,
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+
P_PCIE_PHY_AUX_CLK,
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+
P_RXC0_REF_CLK,
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+
P_RXC1_REF_CLK,
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+
P_SLEEP_CLK,
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+
P_UFS_CARD_RX_SYMBOL_0_CLK,
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+
P_UFS_CARD_RX_SYMBOL_1_CLK,
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+
P_UFS_CARD_TX_SYMBOL_0_CLK,
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+
P_UFS_PHY_RX_SYMBOL_0_CLK,
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+
P_UFS_PHY_RX_SYMBOL_1_CLK,
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+
P_UFS_PHY_TX_SYMBOL_0_CLK,
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+
P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
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P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK,
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+
};
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+
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static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO };
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+
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+
static struct clk_alpha_pll gcc_gpll0 = {
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.offset = 0x0,
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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+
.clkr = {
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.enable_reg = 0x4b028,
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+
.enable_mask = BIT(0),
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+
.hw.init = &(const struct clk_init_data){
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.name = "gcc_gpll0",
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+
.parent_data = &gcc_parent_data_tcxo,
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+
.num_parents = 1,
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.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
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+
},
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},
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+
};
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+
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static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
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{ 0x1, 2 },
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{ }
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};
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+
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static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 10,
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.post_div_table = post_div_table_gcc_gpll0_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
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+
.width = 4,
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
102
+
.clkr.hw.init = &(const struct clk_init_data){
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+
.name = "gcc_gpll0_out_even",
104
+
.parent_hws = (const struct clk_hw*[]){
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&gcc_gpll0.clkr.hw,
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+
},
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+
.num_parents = 1,
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+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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+
},
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+
};
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+
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static struct clk_alpha_pll gcc_gpll1 = {
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.offset = 0x1000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
115
+
.clkr = {
116
+
.enable_reg = 0x4b028,
117
+
.enable_mask = BIT(1),
118
+
.hw.init = &(const struct clk_init_data){
119
+
.name = "gcc_gpll1",
120
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.parent_data = &gcc_parent_data_tcxo,
121
+
.num_parents = 1,
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.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
123
+
},
124
+
},
125
+
};
126
+
127
+
static struct clk_alpha_pll gcc_gpll4 = {
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+
.offset = 0x4000,
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
130
+
.clkr = {
131
+
.enable_reg = 0x4b028,
132
+
.enable_mask = BIT(4),
133
+
.hw.init = &(const struct clk_init_data){
134
+
.name = "gcc_gpll4",
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+
.parent_data = &gcc_parent_data_tcxo,
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+
.num_parents = 1,
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.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
138
+
},
139
+
},
140
+
};
141
+
142
+
static struct clk_alpha_pll gcc_gpll5 = {
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+
.offset = 0x5000,
144
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
145
+
.clkr = {
146
+
.enable_reg = 0x4b028,
147
+
.enable_mask = BIT(5),
148
+
.hw.init = &(const struct clk_init_data){
149
+
.name = "gcc_gpll5",
150
+
.parent_data = &gcc_parent_data_tcxo,
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+
.num_parents = 1,
152
+
.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
153
+
},
154
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},
155
+
};
156
+
157
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static struct clk_alpha_pll gcc_gpll7 = {
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.offset = 0x7000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.enable_reg = 0x4b028,
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.enable_mask = BIT(7),
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+
.hw.init = &(const struct clk_init_data){
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.name = "gcc_gpll7",
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.parent_data = &gcc_parent_data_tcxo,
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+
.num_parents = 1,
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.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
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},
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},
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};
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+
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static struct clk_alpha_pll gcc_gpll9 = {
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.offset = 0x9000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
175
+
.clkr = {
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+
.enable_reg = 0x4b028,
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+
.enable_mask = BIT(9),
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+
.hw.init = &(const struct clk_init_data){
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.name = "gcc_gpll9",
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.parent_data = &gcc_parent_data_tcxo,
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.num_parents = 1,
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.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
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},
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},
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};
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+
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+
static const struct parent_map gcc_parent_map_0[] = {
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+
{ P_BI_TCXO, 0 },
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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+
};
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+
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+
static const struct clk_parent_data gcc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gcc_gpll0.clkr.hw },
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+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
197
+
};
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+
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static const struct parent_map gcc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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{ P_GCC_GPLL4_OUT_MAIN, 5 },
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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+
};
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+
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static const struct clk_parent_data gcc_parent_data_1[] = {
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+
{ .index = DT_BI_TCXO },
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{ .hw = &gcc_gpll0.clkr.hw },
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+
{ .hw = &gcc_gpll4.clkr.hw },
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{ .hw = &gcc_gpll0_out_even.clkr.hw },
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+
};
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+
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static const struct parent_map gcc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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{ P_SLEEP_CLK, 5 },
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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+
};
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+
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static const struct clk_parent_data gcc_parent_data_2[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gcc_gpll0.clkr.hw },
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{ .index = DT_SLEEP_CLK },
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{ .hw = &gcc_gpll0_out_even.clkr.hw },
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};
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+
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static const struct parent_map gcc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_SLEEP_CLK, 5 },
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+
};
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+
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static const struct clk_parent_data gcc_parent_data_3[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_SLEEP_CLK },
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+
};
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+
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+
static const struct parent_map gcc_parent_map_4[] = {
238
+
{ P_BI_TCXO, 0 },
239
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
240
+
{ P_GCC_GPLL1_OUT_MAIN, 4 },
241
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{ P_GCC_GPLL4_OUT_MAIN, 5 },
242
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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};
244
+
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static const struct clk_parent_data gcc_parent_data_4[] = {
246
+
{ .index = DT_BI_TCXO },
247
+
{ .hw = &gcc_gpll0.clkr.hw },
248
+
{ .hw = &gcc_gpll1.clkr.hw },
249
+
{ .hw = &gcc_gpll4.clkr.hw },
250
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
251
+
};
252
+
253
+
static const struct parent_map gcc_parent_map_5[] = {
254
+
{ P_BI_TCXO, 0 },
255
+
};
256
+
257
+
static const struct clk_parent_data gcc_parent_data_5[] = {
258
+
{ .index = DT_BI_TCXO },
259
+
};
260
+
261
+
static const struct parent_map gcc_parent_map_6[] = {
262
+
{ P_BI_TCXO, 0 },
263
+
{ P_GCC_GPLL7_OUT_MAIN, 2 },
264
+
{ P_GCC_GPLL4_OUT_MAIN, 5 },
265
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
266
+
};
267
+
268
+
static const struct clk_parent_data gcc_parent_data_6[] = {
269
+
{ .index = DT_BI_TCXO },
270
+
{ .hw = &gcc_gpll7.clkr.hw },
271
+
{ .hw = &gcc_gpll4.clkr.hw },
272
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
273
+
};
274
+
275
+
static const struct parent_map gcc_parent_map_7[] = {
276
+
{ P_BI_TCXO, 0 },
277
+
{ P_GCC_GPLL7_OUT_MAIN, 2 },
278
+
{ P_RXC0_REF_CLK, 3 },
279
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
280
+
};
281
+
282
+
static const struct clk_parent_data gcc_parent_data_7[] = {
283
+
{ .index = DT_BI_TCXO },
284
+
{ .hw = &gcc_gpll7.clkr.hw },
285
+
{ .index = DT_RXC0_REF_CLK },
286
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
287
+
};
288
+
289
+
static const struct parent_map gcc_parent_map_8[] = {
290
+
{ P_BI_TCXO, 0 },
291
+
{ P_GCC_GPLL7_OUT_MAIN, 2 },
292
+
{ P_RXC1_REF_CLK, 3 },
293
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
294
+
};
295
+
296
+
static const struct clk_parent_data gcc_parent_data_8[] = {
297
+
{ .index = DT_BI_TCXO },
298
+
{ .hw = &gcc_gpll7.clkr.hw },
299
+
{ .index = DT_RXC1_REF_CLK },
300
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
301
+
};
302
+
303
+
static const struct parent_map gcc_parent_map_9[] = {
304
+
{ P_PCIE_PHY_AUX_CLK, 1 },
305
+
{ P_BI_TCXO, 2 },
306
+
};
307
+
308
+
static const struct clk_parent_data gcc_parent_data_9[] = {
309
+
{ .index = DT_PCIE_PHY_AUX_CLK },
310
+
{ .index = DT_BI_TCXO },
311
+
};
312
+
313
+
static const struct parent_map gcc_parent_map_10[] = {
314
+
{ P_PCIE_0_PIPE_CLK, 0 },
315
+
{ P_BI_TCXO, 2 },
316
+
};
317
+
318
+
static const struct clk_parent_data gcc_parent_data_10[] = {
319
+
{ .index = DT_PCIE_0_PIPE_CLK },
320
+
{ .index = DT_BI_TCXO },
321
+
};
322
+
323
+
static const struct parent_map gcc_parent_map_11[] = {
324
+
{ P_PCIE_PHY_AUX_CLK, 1 },
325
+
{ P_BI_TCXO, 2 },
326
+
};
327
+
328
+
static const struct clk_parent_data gcc_parent_data_11[] = {
329
+
{ .index = DT_PCIE_PHY_AUX_CLK },
330
+
{ .index = DT_BI_TCXO },
331
+
};
332
+
333
+
static const struct parent_map gcc_parent_map_12[] = {
334
+
{ P_PCIE_1_PIPE_CLK, 0 },
335
+
{ P_BI_TCXO, 2 },
336
+
};
337
+
338
+
static const struct clk_parent_data gcc_parent_data_12[] = {
339
+
{ .index = DT_PCIE_1_PIPE_CLK },
340
+
{ .index = DT_BI_TCXO },
341
+
};
342
+
343
+
static const struct parent_map gcc_parent_map_13[] = {
344
+
{ P_BI_TCXO, 0 },
345
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
346
+
{ P_GCC_GPLL9_OUT_MAIN, 2 },
347
+
{ P_GCC_GPLL4_OUT_MAIN, 5 },
348
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
349
+
};
350
+
351
+
static const struct clk_parent_data gcc_parent_data_13[] = {
352
+
{ .index = DT_BI_TCXO },
353
+
{ .hw = &gcc_gpll0.clkr.hw },
354
+
{ .hw = &gcc_gpll9.clkr.hw },
355
+
{ .hw = &gcc_gpll4.clkr.hw },
356
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
357
+
};
358
+
359
+
static const struct parent_map gcc_parent_map_14[] = {
360
+
{ P_BI_TCXO, 0 },
361
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
362
+
};
363
+
364
+
static const struct clk_parent_data gcc_parent_data_14[] = {
365
+
{ .index = DT_BI_TCXO },
366
+
{ .hw = &gcc_gpll0.clkr.hw },
367
+
};
368
+
369
+
static const struct parent_map gcc_parent_map_15[] = {
370
+
{ P_BI_TCXO, 0 },
371
+
{ P_GCC_GPLL7_OUT_MAIN, 2 },
372
+
{ P_GCC_GPLL5_OUT_MAIN, 3 },
373
+
{ P_GCC_GPLL4_OUT_MAIN, 5 },
374
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
375
+
};
376
+
377
+
static const struct clk_parent_data gcc_parent_data_15[] = {
378
+
{ .index = DT_BI_TCXO },
379
+
{ .hw = &gcc_gpll7.clkr.hw },
380
+
{ .hw = &gcc_gpll5.clkr.hw },
381
+
{ .hw = &gcc_gpll4.clkr.hw },
382
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
383
+
};
384
+
385
+
static const struct parent_map gcc_parent_map_16[] = {
386
+
{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
387
+
{ P_BI_TCXO, 2 },
388
+
};
389
+
390
+
static const struct clk_parent_data gcc_parent_data_16[] = {
391
+
{ .index = DT_UFS_CARD_RX_SYMBOL_0_CLK },
392
+
{ .index = DT_BI_TCXO },
393
+
};
394
+
395
+
static const struct parent_map gcc_parent_map_17[] = {
396
+
{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
397
+
{ P_BI_TCXO, 2 },
398
+
};
399
+
400
+
static const struct clk_parent_data gcc_parent_data_17[] = {
401
+
{ .index = DT_UFS_CARD_RX_SYMBOL_1_CLK },
402
+
{ .index = DT_BI_TCXO },
403
+
};
404
+
405
+
static const struct parent_map gcc_parent_map_18[] = {
406
+
{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
407
+
{ P_BI_TCXO, 2 },
408
+
};
409
+
410
+
static const struct clk_parent_data gcc_parent_data_18[] = {
411
+
{ .index = DT_UFS_CARD_TX_SYMBOL_0_CLK },
412
+
{ .index = DT_BI_TCXO },
413
+
};
414
+
415
+
static const struct parent_map gcc_parent_map_19[] = {
416
+
{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
417
+
{ P_BI_TCXO, 2 },
418
+
};
419
+
420
+
static const struct clk_parent_data gcc_parent_data_19[] = {
421
+
{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
422
+
{ .index = DT_BI_TCXO },
423
+
};
424
+
425
+
static const struct parent_map gcc_parent_map_20[] = {
426
+
{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
427
+
{ P_BI_TCXO, 2 },
428
+
};
429
+
430
+
static const struct clk_parent_data gcc_parent_data_20[] = {
431
+
{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
432
+
{ .index = DT_BI_TCXO },
433
+
};
434
+
435
+
static const struct parent_map gcc_parent_map_21[] = {
436
+
{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
437
+
{ P_BI_TCXO, 2 },
438
+
};
439
+
440
+
static const struct clk_parent_data gcc_parent_data_21[] = {
441
+
{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
442
+
{ .index = DT_BI_TCXO },
443
+
};
444
+
445
+
static const struct parent_map gcc_parent_map_22[] = {
446
+
{ P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
447
+
{ P_BI_TCXO, 2 },
448
+
};
449
+
450
+
static const struct clk_parent_data gcc_parent_data_22[] = {
451
+
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK },
452
+
{ .index = DT_BI_TCXO },
453
+
};
454
+
455
+
static const struct parent_map gcc_parent_map_23[] = {
456
+
{ P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 },
457
+
{ P_BI_TCXO, 2 },
458
+
};
459
+
460
+
static const struct clk_parent_data gcc_parent_data_23[] = {
461
+
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK },
462
+
{ .index = DT_BI_TCXO },
463
+
};
464
+
465
+
static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
466
+
.reg = 0xa9074,
467
+
.shift = 0,
468
+
.width = 2,
469
+
.parent_map = gcc_parent_map_9,
470
+
.clkr = {
471
+
.hw.init = &(const struct clk_init_data){
472
+
.name = "gcc_pcie_0_phy_aux_clk_src",
473
+
.parent_data = gcc_parent_data_9,
474
+
.num_parents = ARRAY_SIZE(gcc_parent_data_9),
475
+
.ops = &clk_regmap_mux_closest_ops,
476
+
},
477
+
},
478
+
};
479
+
480
+
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
481
+
.reg = 0xa906c,
482
+
.clkr = {
483
+
.hw.init = &(const struct clk_init_data){
484
+
.name = "gcc_pcie_0_pipe_clk_src",
485
+
.parent_data = &(const struct clk_parent_data){
486
+
.index = DT_PCIE_0_PIPE_CLK,
487
+
},
488
+
.num_parents = 1,
489
+
.ops = &clk_regmap_phy_mux_ops,
490
+
},
491
+
},
492
+
};
493
+
494
+
static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
495
+
.reg = 0x77074,
496
+
.shift = 0,
497
+
.width = 2,
498
+
.parent_map = gcc_parent_map_11,
499
+
.clkr = {
500
+
.hw.init = &(const struct clk_init_data){
501
+
.name = "gcc_pcie_1_phy_aux_clk_src",
502
+
.parent_data = gcc_parent_data_11,
503
+
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
504
+
.ops = &clk_regmap_mux_closest_ops,
505
+
},
506
+
},
507
+
};
508
+
509
+
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
510
+
.reg = 0x7706c,
511
+
.clkr = {
512
+
.hw.init = &(const struct clk_init_data){
513
+
.name = "gcc_pcie_1_pipe_clk_src",
514
+
.parent_data = &(const struct clk_parent_data) {
515
+
.index = DT_PCIE_1_PIPE_CLK,
516
+
},
517
+
.num_parents = 1,
518
+
.ops = &clk_regmap_phy_mux_ops,
519
+
},
520
+
},
521
+
};
522
+
523
+
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
524
+
.reg = 0x81060,
525
+
.shift = 0,
526
+
.width = 2,
527
+
.parent_map = gcc_parent_map_16,
528
+
.clkr = {
529
+
.hw.init = &(const struct clk_init_data){
530
+
.name = "gcc_ufs_card_rx_symbol_0_clk_src",
531
+
.parent_data = gcc_parent_data_16,
532
+
.num_parents = ARRAY_SIZE(gcc_parent_data_16),
533
+
.ops = &clk_regmap_mux_closest_ops,
534
+
},
535
+
},
536
+
};
537
+
538
+
static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
539
+
.reg = 0x810d0,
540
+
.shift = 0,
541
+
.width = 2,
542
+
.parent_map = gcc_parent_map_17,
543
+
.clkr = {
544
+
.hw.init = &(const struct clk_init_data){
545
+
.name = "gcc_ufs_card_rx_symbol_1_clk_src",
546
+
.parent_data = gcc_parent_data_17,
547
+
.num_parents = ARRAY_SIZE(gcc_parent_data_17),
548
+
.ops = &clk_regmap_mux_closest_ops,
549
+
},
550
+
},
551
+
};
552
+
553
+
static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
554
+
.reg = 0x81050,
555
+
.shift = 0,
556
+
.width = 2,
557
+
.parent_map = gcc_parent_map_18,
558
+
.clkr = {
559
+
.hw.init = &(const struct clk_init_data){
560
+
.name = "gcc_ufs_card_tx_symbol_0_clk_src",
561
+
.parent_data = gcc_parent_data_18,
562
+
.num_parents = ARRAY_SIZE(gcc_parent_data_18),
563
+
.ops = &clk_regmap_mux_closest_ops,
564
+
},
565
+
},
566
+
};
567
+
568
+
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
569
+
.reg = 0x83060,
570
+
.shift = 0,
571
+
.width = 2,
572
+
.parent_map = gcc_parent_map_19,
573
+
.clkr = {
574
+
.hw.init = &(const struct clk_init_data){
575
+
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
576
+
.parent_data = gcc_parent_data_19,
577
+
.num_parents = ARRAY_SIZE(gcc_parent_data_19),
578
+
.ops = &clk_regmap_mux_closest_ops,
579
+
},
580
+
},
581
+
};
582
+
583
+
static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
584
+
.reg = 0x830d0,
585
+
.shift = 0,
586
+
.width = 2,
587
+
.parent_map = gcc_parent_map_20,
588
+
.clkr = {
589
+
.hw.init = &(const struct clk_init_data){
590
+
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
591
+
.parent_data = gcc_parent_data_20,
592
+
.num_parents = ARRAY_SIZE(gcc_parent_data_20),
593
+
.ops = &clk_regmap_mux_closest_ops,
594
+
},
595
+
},
596
+
};
597
+
598
+
static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
599
+
.reg = 0x83050,
600
+
.shift = 0,
601
+
.width = 2,
602
+
.parent_map = gcc_parent_map_21,
603
+
.clkr = {
604
+
.hw.init = &(const struct clk_init_data){
605
+
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
606
+
.parent_data = gcc_parent_data_21,
607
+
.num_parents = ARRAY_SIZE(gcc_parent_data_21),
608
+
.ops = &clk_regmap_mux_closest_ops,
609
+
},
610
+
},
611
+
};
612
+
613
+
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
614
+
.reg = 0x1b068,
615
+
.shift = 0,
616
+
.width = 2,
617
+
.parent_map = gcc_parent_map_22,
618
+
.clkr = {
619
+
.hw.init = &(const struct clk_init_data){
620
+
.name = "gcc_usb3_prim_phy_pipe_clk_src",
621
+
.parent_data = gcc_parent_data_22,
622
+
.num_parents = ARRAY_SIZE(gcc_parent_data_22),
623
+
.ops = &clk_regmap_mux_closest_ops,
624
+
},
625
+
},
626
+
};
627
+
628
+
static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
629
+
.reg = 0x2f068,
630
+
.shift = 0,
631
+
.width = 2,
632
+
.parent_map = gcc_parent_map_23,
633
+
.clkr = {
634
+
.hw.init = &(const struct clk_init_data){
635
+
.name = "gcc_usb3_sec_phy_pipe_clk_src",
636
+
.parent_data = gcc_parent_data_23,
637
+
.num_parents = ARRAY_SIZE(gcc_parent_data_23),
638
+
.ops = &clk_regmap_mux_closest_ops,
639
+
},
640
+
},
641
+
};
642
+
643
+
static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
644
+
F(19200000, P_BI_TCXO, 1, 0, 0),
645
+
{ }
646
+
};
647
+
648
+
static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {
649
+
.cmd_rcgr = 0xb6028,
650
+
.mnd_width = 0,
651
+
.hid_width = 5,
652
+
.parent_map = gcc_parent_map_3,
653
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
654
+
.clkr.hw.init = &(const struct clk_init_data){
655
+
.name = "gcc_emac0_phy_aux_clk_src",
656
+
.parent_data = gcc_parent_data_3,
657
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
658
+
.ops = &clk_rcg2_shared_ops,
659
+
},
660
+
};
661
+
662
+
static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
663
+
F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
664
+
F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
665
+
{ }
666
+
};
667
+
668
+
static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
669
+
.cmd_rcgr = 0xb6060,
670
+
.mnd_width = 16,
671
+
.hid_width = 5,
672
+
.parent_map = gcc_parent_map_6,
673
+
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
674
+
.clkr.hw.init = &(const struct clk_init_data){
675
+
.name = "gcc_emac0_ptp_clk_src",
676
+
.parent_data = gcc_parent_data_6,
677
+
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
678
+
.ops = &clk_rcg2_shared_ops,
679
+
},
680
+
};
681
+
682
+
static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
683
+
F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
684
+
F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
685
+
{ }
686
+
};
687
+
688
+
static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
689
+
.cmd_rcgr = 0xb6048,
690
+
.mnd_width = 16,
691
+
.hid_width = 5,
692
+
.parent_map = gcc_parent_map_7,
693
+
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
694
+
.clkr.hw.init = &(const struct clk_init_data){
695
+
.name = "gcc_emac0_rgmii_clk_src",
696
+
.parent_data = gcc_parent_data_7,
697
+
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
698
+
.ops = &clk_rcg2_shared_ops,
699
+
},
700
+
};
701
+
702
+
static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = {
703
+
.cmd_rcgr = 0xb4028,
704
+
.mnd_width = 0,
705
+
.hid_width = 5,
706
+
.parent_map = gcc_parent_map_3,
707
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
708
+
.clkr.hw.init = &(const struct clk_init_data){
709
+
.name = "gcc_emac1_phy_aux_clk_src",
710
+
.parent_data = gcc_parent_data_3,
711
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
712
+
.ops = &clk_rcg2_shared_ops,
713
+
},
714
+
};
715
+
716
+
static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
717
+
.cmd_rcgr = 0xb4060,
718
+
.mnd_width = 16,
719
+
.hid_width = 5,
720
+
.parent_map = gcc_parent_map_6,
721
+
.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
722
+
.clkr.hw.init = &(const struct clk_init_data){
723
+
.name = "gcc_emac1_ptp_clk_src",
724
+
.parent_data = gcc_parent_data_6,
725
+
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
726
+
.ops = &clk_rcg2_shared_ops,
727
+
},
728
+
};
729
+
730
+
static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
731
+
.cmd_rcgr = 0xb4048,
732
+
.mnd_width = 16,
733
+
.hid_width = 5,
734
+
.parent_map = gcc_parent_map_8,
735
+
.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
736
+
.clkr.hw.init = &(const struct clk_init_data){
737
+
.name = "gcc_emac1_rgmii_clk_src",
738
+
.parent_data = gcc_parent_data_8,
739
+
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
740
+
.ops = &clk_rcg2_shared_ops,
741
+
},
742
+
};
743
+
744
+
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
745
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
746
+
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
747
+
{ }
748
+
};
749
+
750
+
static struct clk_rcg2 gcc_gp1_clk_src = {
751
+
.cmd_rcgr = 0x70004,
752
+
.mnd_width = 16,
753
+
.hid_width = 5,
754
+
.parent_map = gcc_parent_map_2,
755
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
756
+
.clkr.hw.init = &(const struct clk_init_data){
757
+
.name = "gcc_gp1_clk_src",
758
+
.parent_data = gcc_parent_data_2,
759
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
760
+
.ops = &clk_rcg2_shared_ops,
761
+
},
762
+
};
763
+
764
+
static struct clk_rcg2 gcc_gp2_clk_src = {
765
+
.cmd_rcgr = 0x71004,
766
+
.mnd_width = 16,
767
+
.hid_width = 5,
768
+
.parent_map = gcc_parent_map_2,
769
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
770
+
.clkr.hw.init = &(const struct clk_init_data){
771
+
.name = "gcc_gp2_clk_src",
772
+
.parent_data = gcc_parent_data_2,
773
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
774
+
.ops = &clk_rcg2_shared_ops,
775
+
},
776
+
};
777
+
778
+
static struct clk_rcg2 gcc_gp3_clk_src = {
779
+
.cmd_rcgr = 0x62004,
780
+
.mnd_width = 16,
781
+
.hid_width = 5,
782
+
.parent_map = gcc_parent_map_2,
783
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
784
+
.clkr.hw.init = &(const struct clk_init_data){
785
+
.name = "gcc_gp3_clk_src",
786
+
.parent_data = gcc_parent_data_2,
787
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
788
+
.ops = &clk_rcg2_shared_ops,
789
+
},
790
+
};
791
+
792
+
static struct clk_rcg2 gcc_gp4_clk_src = {
793
+
.cmd_rcgr = 0x1e004,
794
+
.mnd_width = 16,
795
+
.hid_width = 5,
796
+
.parent_map = gcc_parent_map_2,
797
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
798
+
.clkr.hw.init = &(const struct clk_init_data){
799
+
.name = "gcc_gp4_clk_src",
800
+
.parent_data = gcc_parent_data_2,
801
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
802
+
.ops = &clk_rcg2_shared_ops,
803
+
},
804
+
};
805
+
806
+
static struct clk_rcg2 gcc_gp5_clk_src = {
807
+
.cmd_rcgr = 0x1f004,
808
+
.mnd_width = 16,
809
+
.hid_width = 5,
810
+
.parent_map = gcc_parent_map_2,
811
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
812
+
.clkr.hw.init = &(const struct clk_init_data){
813
+
.name = "gcc_gp5_clk_src",
814
+
.parent_data = gcc_parent_data_2,
815
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
816
+
.ops = &clk_rcg2_shared_ops,
817
+
},
818
+
};
819
+
820
+
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
821
+
.cmd_rcgr = 0xa9078,
822
+
.mnd_width = 16,
823
+
.hid_width = 5,
824
+
.parent_map = gcc_parent_map_3,
825
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
826
+
.clkr.hw.init = &(const struct clk_init_data){
827
+
.name = "gcc_pcie_0_aux_clk_src",
828
+
.parent_data = gcc_parent_data_3,
829
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
830
+
.ops = &clk_rcg2_shared_ops,
831
+
},
832
+
};
833
+
834
+
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
835
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
836
+
{ }
837
+
};
838
+
839
+
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
840
+
.cmd_rcgr = 0xa9054,
841
+
.mnd_width = 0,
842
+
.hid_width = 5,
843
+
.parent_map = gcc_parent_map_0,
844
+
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
845
+
.clkr.hw.init = &(const struct clk_init_data){
846
+
.name = "gcc_pcie_0_phy_rchng_clk_src",
847
+
.parent_data = gcc_parent_data_0,
848
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
849
+
.ops = &clk_rcg2_shared_ops,
850
+
},
851
+
};
852
+
853
+
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
854
+
.cmd_rcgr = 0x77078,
855
+
.mnd_width = 16,
856
+
.hid_width = 5,
857
+
.parent_map = gcc_parent_map_3,
858
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
859
+
.clkr.hw.init = &(const struct clk_init_data){
860
+
.name = "gcc_pcie_1_aux_clk_src",
861
+
.parent_data = gcc_parent_data_3,
862
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
863
+
.ops = &clk_rcg2_shared_ops,
864
+
},
865
+
};
866
+
867
+
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
868
+
.cmd_rcgr = 0x77054,
869
+
.mnd_width = 0,
870
+
.hid_width = 5,
871
+
.parent_map = gcc_parent_map_0,
872
+
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
873
+
.clkr.hw.init = &(const struct clk_init_data){
874
+
.name = "gcc_pcie_1_phy_rchng_clk_src",
875
+
.parent_data = gcc_parent_data_0,
876
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
877
+
.ops = &clk_rcg2_shared_ops,
878
+
},
879
+
};
880
+
881
+
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
882
+
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
883
+
{ }
884
+
};
885
+
886
+
static struct clk_rcg2 gcc_pdm2_clk_src = {
887
+
.cmd_rcgr = 0x3f010,
888
+
.mnd_width = 0,
889
+
.hid_width = 5,
890
+
.parent_map = gcc_parent_map_0,
891
+
.freq_tbl = ftbl_gcc_pdm2_clk_src,
892
+
.clkr.hw.init = &(const struct clk_init_data){
893
+
.name = "gcc_pdm2_clk_src",
894
+
.parent_data = gcc_parent_data_0,
895
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
896
+
.ops = &clk_rcg2_shared_ops,
897
+
},
898
+
};
899
+
900
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
901
+
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
902
+
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
903
+
F(19200000, P_BI_TCXO, 1, 0, 0),
904
+
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
905
+
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
906
+
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
907
+
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
908
+
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
909
+
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
910
+
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
911
+
{ }
912
+
};
913
+
914
+
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
915
+
.name = "gcc_qupv3_wrap0_s0_clk_src",
916
+
.parent_data = gcc_parent_data_0,
917
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
918
+
.ops = &clk_rcg2_shared_ops,
919
+
};
920
+
921
+
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
922
+
.cmd_rcgr = 0x23154,
923
+
.mnd_width = 16,
924
+
.hid_width = 5,
925
+
.parent_map = gcc_parent_map_0,
926
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
927
+
.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
928
+
};
929
+
930
+
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
931
+
.name = "gcc_qupv3_wrap0_s1_clk_src",
932
+
.parent_data = gcc_parent_data_0,
933
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
934
+
.ops = &clk_rcg2_shared_ops,
935
+
};
936
+
937
+
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
938
+
.cmd_rcgr = 0x23288,
939
+
.mnd_width = 16,
940
+
.hid_width = 5,
941
+
.parent_map = gcc_parent_map_0,
942
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
943
+
.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
944
+
};
945
+
946
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
947
+
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
948
+
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
949
+
F(19200000, P_BI_TCXO, 1, 0, 0),
950
+
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
951
+
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
952
+
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
953
+
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
954
+
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
955
+
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
956
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
957
+
{ }
958
+
};
959
+
960
+
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
961
+
.name = "gcc_qupv3_wrap0_s2_clk_src",
962
+
.parent_data = gcc_parent_data_0,
963
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
964
+
.ops = &clk_rcg2_shared_ops,
965
+
};
966
+
967
+
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
968
+
.cmd_rcgr = 0x233bc,
969
+
.mnd_width = 16,
970
+
.hid_width = 5,
971
+
.parent_map = gcc_parent_map_0,
972
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
973
+
.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
974
+
};
975
+
976
+
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
977
+
.name = "gcc_qupv3_wrap0_s3_clk_src",
978
+
.parent_data = gcc_parent_data_0,
979
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
980
+
.ops = &clk_rcg2_shared_ops,
981
+
};
982
+
983
+
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
984
+
.cmd_rcgr = 0x234f0,
985
+
.mnd_width = 16,
986
+
.hid_width = 5,
987
+
.parent_map = gcc_parent_map_0,
988
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
989
+
.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
990
+
};
991
+
992
+
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
993
+
.name = "gcc_qupv3_wrap0_s4_clk_src",
994
+
.parent_data = gcc_parent_data_1,
995
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
996
+
.ops = &clk_rcg2_shared_ops,
997
+
};
998
+
999
+
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1000
+
.cmd_rcgr = 0x23624,
1001
+
.mnd_width = 16,
1002
+
.hid_width = 5,
1003
+
.parent_map = gcc_parent_map_1,
1004
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1005
+
.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1006
+
};
1007
+
1008
+
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1009
+
.name = "gcc_qupv3_wrap0_s5_clk_src",
1010
+
.parent_data = gcc_parent_data_0,
1011
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1012
+
.ops = &clk_rcg2_shared_ops,
1013
+
};
1014
+
1015
+
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1016
+
.cmd_rcgr = 0x23758,
1017
+
.mnd_width = 16,
1018
+
.hid_width = 5,
1019
+
.parent_map = gcc_parent_map_0,
1020
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1021
+
.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1022
+
};
1023
+
1024
+
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
1025
+
.name = "gcc_qupv3_wrap0_s6_clk_src",
1026
+
.parent_data = gcc_parent_data_0,
1027
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1028
+
.ops = &clk_rcg2_shared_ops,
1029
+
};
1030
+
1031
+
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
1032
+
.cmd_rcgr = 0x2388c,
1033
+
.mnd_width = 16,
1034
+
.hid_width = 5,
1035
+
.parent_map = gcc_parent_map_0,
1036
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1037
+
.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
1038
+
};
1039
+
1040
+
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1041
+
.name = "gcc_qupv3_wrap1_s0_clk_src",
1042
+
.parent_data = gcc_parent_data_0,
1043
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1044
+
.ops = &clk_rcg2_shared_ops,
1045
+
};
1046
+
1047
+
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1048
+
.cmd_rcgr = 0x24154,
1049
+
.mnd_width = 16,
1050
+
.hid_width = 5,
1051
+
.parent_map = gcc_parent_map_0,
1052
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1053
+
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1054
+
};
1055
+
1056
+
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1057
+
.name = "gcc_qupv3_wrap1_s1_clk_src",
1058
+
.parent_data = gcc_parent_data_0,
1059
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1060
+
.ops = &clk_rcg2_shared_ops,
1061
+
};
1062
+
1063
+
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1064
+
.cmd_rcgr = 0x24288,
1065
+
.mnd_width = 16,
1066
+
.hid_width = 5,
1067
+
.parent_map = gcc_parent_map_0,
1068
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1069
+
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1070
+
};
1071
+
1072
+
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1073
+
.name = "gcc_qupv3_wrap1_s2_clk_src",
1074
+
.parent_data = gcc_parent_data_0,
1075
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1076
+
.ops = &clk_rcg2_shared_ops,
1077
+
};
1078
+
1079
+
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1080
+
.cmd_rcgr = 0x243bc,
1081
+
.mnd_width = 16,
1082
+
.hid_width = 5,
1083
+
.parent_map = gcc_parent_map_0,
1084
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1085
+
.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1086
+
};
1087
+
1088
+
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1089
+
.name = "gcc_qupv3_wrap1_s3_clk_src",
1090
+
.parent_data = gcc_parent_data_0,
1091
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1092
+
.ops = &clk_rcg2_shared_ops,
1093
+
};
1094
+
1095
+
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1096
+
.cmd_rcgr = 0x244f0,
1097
+
.mnd_width = 16,
1098
+
.hid_width = 5,
1099
+
.parent_map = gcc_parent_map_0,
1100
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1101
+
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1102
+
};
1103
+
1104
+
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1105
+
.name = "gcc_qupv3_wrap1_s4_clk_src",
1106
+
.parent_data = gcc_parent_data_1,
1107
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1108
+
.ops = &clk_rcg2_shared_ops,
1109
+
};
1110
+
1111
+
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1112
+
.cmd_rcgr = 0x24624,
1113
+
.mnd_width = 16,
1114
+
.hid_width = 5,
1115
+
.parent_map = gcc_parent_map_1,
1116
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1117
+
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1118
+
};
1119
+
1120
+
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1121
+
.name = "gcc_qupv3_wrap1_s5_clk_src",
1122
+
.parent_data = gcc_parent_data_0,
1123
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1124
+
.ops = &clk_rcg2_shared_ops,
1125
+
};
1126
+
1127
+
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1128
+
.cmd_rcgr = 0x24758,
1129
+
.mnd_width = 16,
1130
+
.hid_width = 5,
1131
+
.parent_map = gcc_parent_map_0,
1132
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1133
+
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1134
+
};
1135
+
1136
+
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
1137
+
.name = "gcc_qupv3_wrap1_s6_clk_src",
1138
+
.parent_data = gcc_parent_data_0,
1139
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1140
+
.ops = &clk_rcg2_shared_ops,
1141
+
};
1142
+
1143
+
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
1144
+
.cmd_rcgr = 0x2488c,
1145
+
.mnd_width = 16,
1146
+
.hid_width = 5,
1147
+
.parent_map = gcc_parent_map_0,
1148
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1149
+
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
1150
+
};
1151
+
1152
+
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
1153
+
.name = "gcc_qupv3_wrap2_s0_clk_src",
1154
+
.parent_data = gcc_parent_data_1,
1155
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1156
+
.ops = &clk_rcg2_shared_ops,
1157
+
};
1158
+
1159
+
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
1160
+
.cmd_rcgr = 0x2a154,
1161
+
.mnd_width = 16,
1162
+
.hid_width = 5,
1163
+
.parent_map = gcc_parent_map_1,
1164
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1165
+
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
1166
+
};
1167
+
1168
+
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
1169
+
.name = "gcc_qupv3_wrap2_s1_clk_src",
1170
+
.parent_data = gcc_parent_data_1,
1171
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1172
+
.ops = &clk_rcg2_shared_ops,
1173
+
};
1174
+
1175
+
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
1176
+
.cmd_rcgr = 0x2a288,
1177
+
.mnd_width = 16,
1178
+
.hid_width = 5,
1179
+
.parent_map = gcc_parent_map_1,
1180
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1181
+
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1182
+
};
1183
+
1184
+
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1185
+
.name = "gcc_qupv3_wrap2_s2_clk_src",
1186
+
.parent_data = gcc_parent_data_1,
1187
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1188
+
.ops = &clk_rcg2_shared_ops,
1189
+
};
1190
+
1191
+
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1192
+
.cmd_rcgr = 0x2a3bc,
1193
+
.mnd_width = 16,
1194
+
.hid_width = 5,
1195
+
.parent_map = gcc_parent_map_1,
1196
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1197
+
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1198
+
};
1199
+
1200
+
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1201
+
.name = "gcc_qupv3_wrap2_s3_clk_src",
1202
+
.parent_data = gcc_parent_data_1,
1203
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1204
+
.ops = &clk_rcg2_shared_ops,
1205
+
};
1206
+
1207
+
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1208
+
.cmd_rcgr = 0x2a4f0,
1209
+
.mnd_width = 16,
1210
+
.hid_width = 5,
1211
+
.parent_map = gcc_parent_map_1,
1212
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1213
+
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1214
+
};
1215
+
1216
+
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1217
+
.name = "gcc_qupv3_wrap2_s4_clk_src",
1218
+
.parent_data = gcc_parent_data_1,
1219
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1220
+
.ops = &clk_rcg2_shared_ops,
1221
+
};
1222
+
1223
+
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1224
+
.cmd_rcgr = 0x2a624,
1225
+
.mnd_width = 16,
1226
+
.hid_width = 5,
1227
+
.parent_map = gcc_parent_map_1,
1228
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1229
+
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1230
+
};
1231
+
1232
+
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1233
+
.name = "gcc_qupv3_wrap2_s5_clk_src",
1234
+
.parent_data = gcc_parent_data_1,
1235
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1236
+
.ops = &clk_rcg2_shared_ops,
1237
+
};
1238
+
1239
+
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1240
+
.cmd_rcgr = 0x2a758,
1241
+
.mnd_width = 16,
1242
+
.hid_width = 5,
1243
+
.parent_map = gcc_parent_map_1,
1244
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1245
+
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1246
+
};
1247
+
1248
+
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1249
+
.name = "gcc_qupv3_wrap2_s6_clk_src",
1250
+
.parent_data = gcc_parent_data_1,
1251
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1252
+
.ops = &clk_rcg2_shared_ops,
1253
+
};
1254
+
1255
+
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1256
+
.cmd_rcgr = 0x2a88c,
1257
+
.mnd_width = 16,
1258
+
.hid_width = 5,
1259
+
.parent_map = gcc_parent_map_1,
1260
+
.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1261
+
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1262
+
};
1263
+
1264
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
1265
+
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1266
+
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1267
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1268
+
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1269
+
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1270
+
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1271
+
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1272
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1273
+
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1274
+
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1275
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1276
+
F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1277
+
{ }
1278
+
};
1279
+
1280
+
static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = {
1281
+
.name = "gcc_qupv3_wrap3_s0_clk_src",
1282
+
.parent_data = gcc_parent_data_4,
1283
+
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1284
+
.ops = &clk_rcg2_shared_ops,
1285
+
};
1286
+
1287
+
static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = {
1288
+
.cmd_rcgr = 0xc4154,
1289
+
.mnd_width = 16,
1290
+
.hid_width = 5,
1291
+
.parent_map = gcc_parent_map_4,
1292
+
.freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src,
1293
+
.clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init,
1294
+
};
1295
+
1296
+
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1297
+
F(144000, P_BI_TCXO, 16, 3, 25),
1298
+
F(400000, P_BI_TCXO, 12, 1, 4),
1299
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1300
+
F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
1301
+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1302
+
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1303
+
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1304
+
F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1305
+
F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
1306
+
{ }
1307
+
};
1308
+
1309
+
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1310
+
.cmd_rcgr = 0x20014,
1311
+
.mnd_width = 8,
1312
+
.hid_width = 5,
1313
+
.parent_map = gcc_parent_map_13,
1314
+
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1315
+
.clkr.hw.init = &(const struct clk_init_data){
1316
+
.name = "gcc_sdcc1_apps_clk_src",
1317
+
.parent_data = gcc_parent_data_13,
1318
+
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
1319
+
.ops = &clk_rcg2_floor_ops,
1320
+
},
1321
+
};
1322
+
1323
+
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1324
+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1325
+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1326
+
{ }
1327
+
};
1328
+
1329
+
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1330
+
.cmd_rcgr = 0x2002c,
1331
+
.mnd_width = 0,
1332
+
.hid_width = 5,
1333
+
.parent_map = gcc_parent_map_14,
1334
+
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1335
+
.clkr.hw.init = &(const struct clk_init_data){
1336
+
.name = "gcc_sdcc1_ice_core_clk_src",
1337
+
.parent_data = gcc_parent_data_14,
1338
+
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
1339
+
.ops = &clk_rcg2_floor_ops,
1340
+
},
1341
+
};
1342
+
1343
+
static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = {
1344
+
F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4),
1345
+
{ }
1346
+
};
1347
+
1348
+
static struct clk_rcg2 gcc_tscss_cntr_clk_src = {
1349
+
.cmd_rcgr = 0x21008,
1350
+
.mnd_width = 16,
1351
+
.hid_width = 5,
1352
+
.parent_map = gcc_parent_map_15,
1353
+
.freq_tbl = ftbl_gcc_tscss_cntr_clk_src,
1354
+
.clkr.hw.init = &(const struct clk_init_data){
1355
+
.name = "gcc_tscss_cntr_clk_src",
1356
+
.parent_data = gcc_parent_data_15,
1357
+
.num_parents = ARRAY_SIZE(gcc_parent_data_15),
1358
+
.ops = &clk_rcg2_shared_ops,
1359
+
},
1360
+
};
1361
+
1362
+
static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1363
+
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1364
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1365
+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1366
+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1367
+
F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1368
+
{ }
1369
+
};
1370
+
1371
+
static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1372
+
.cmd_rcgr = 0x8102c,
1373
+
.mnd_width = 8,
1374
+
.hid_width = 5,
1375
+
.parent_map = gcc_parent_map_0,
1376
+
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1377
+
.clkr.hw.init = &(const struct clk_init_data){
1378
+
.name = "gcc_ufs_card_axi_clk_src",
1379
+
.parent_data = gcc_parent_data_0,
1380
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1381
+
.ops = &clk_rcg2_shared_ops,
1382
+
},
1383
+
};
1384
+
1385
+
static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1386
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1387
+
F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1388
+
F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1389
+
F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1390
+
{ }
1391
+
};
1392
+
1393
+
static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1394
+
.cmd_rcgr = 0x81074,
1395
+
.mnd_width = 0,
1396
+
.hid_width = 5,
1397
+
.parent_map = gcc_parent_map_0,
1398
+
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1399
+
.clkr.hw.init = &(const struct clk_init_data){
1400
+
.name = "gcc_ufs_card_ice_core_clk_src",
1401
+
.parent_data = gcc_parent_data_0,
1402
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1403
+
.ops = &clk_rcg2_shared_ops,
1404
+
},
1405
+
};
1406
+
1407
+
static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1408
+
.cmd_rcgr = 0x810a8,
1409
+
.mnd_width = 0,
1410
+
.hid_width = 5,
1411
+
.parent_map = gcc_parent_map_5,
1412
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1413
+
.clkr.hw.init = &(const struct clk_init_data){
1414
+
.name = "gcc_ufs_card_phy_aux_clk_src",
1415
+
.parent_data = gcc_parent_data_5,
1416
+
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1417
+
.ops = &clk_rcg2_shared_ops,
1418
+
},
1419
+
};
1420
+
1421
+
static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1422
+
.cmd_rcgr = 0x8108c,
1423
+
.mnd_width = 0,
1424
+
.hid_width = 5,
1425
+
.parent_map = gcc_parent_map_0,
1426
+
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1427
+
.clkr.hw.init = &(const struct clk_init_data){
1428
+
.name = "gcc_ufs_card_unipro_core_clk_src",
1429
+
.parent_data = gcc_parent_data_0,
1430
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1431
+
.ops = &clk_rcg2_shared_ops,
1432
+
},
1433
+
};
1434
+
1435
+
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1436
+
.cmd_rcgr = 0x8302c,
1437
+
.mnd_width = 8,
1438
+
.hid_width = 5,
1439
+
.parent_map = gcc_parent_map_0,
1440
+
.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1441
+
.clkr.hw.init = &(const struct clk_init_data){
1442
+
.name = "gcc_ufs_phy_axi_clk_src",
1443
+
.parent_data = gcc_parent_data_0,
1444
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1445
+
.ops = &clk_rcg2_shared_ops,
1446
+
},
1447
+
};
1448
+
1449
+
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1450
+
.cmd_rcgr = 0x83074,
1451
+
.mnd_width = 0,
1452
+
.hid_width = 5,
1453
+
.parent_map = gcc_parent_map_0,
1454
+
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1455
+
.clkr.hw.init = &(const struct clk_init_data){
1456
+
.name = "gcc_ufs_phy_ice_core_clk_src",
1457
+
.parent_data = gcc_parent_data_0,
1458
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1459
+
.ops = &clk_rcg2_shared_ops,
1460
+
},
1461
+
};
1462
+
1463
+
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1464
+
.cmd_rcgr = 0x830a8,
1465
+
.mnd_width = 0,
1466
+
.hid_width = 5,
1467
+
.parent_map = gcc_parent_map_5,
1468
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1469
+
.clkr.hw.init = &(const struct clk_init_data){
1470
+
.name = "gcc_ufs_phy_phy_aux_clk_src",
1471
+
.parent_data = gcc_parent_data_5,
1472
+
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1473
+
.ops = &clk_rcg2_shared_ops,
1474
+
},
1475
+
};
1476
+
1477
+
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1478
+
.cmd_rcgr = 0x8308c,
1479
+
.mnd_width = 0,
1480
+
.hid_width = 5,
1481
+
.parent_map = gcc_parent_map_0,
1482
+
.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1483
+
.clkr.hw.init = &(const struct clk_init_data){
1484
+
.name = "gcc_ufs_phy_unipro_core_clk_src",
1485
+
.parent_data = gcc_parent_data_0,
1486
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1487
+
.ops = &clk_rcg2_shared_ops,
1488
+
},
1489
+
};
1490
+
1491
+
static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
1492
+
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1493
+
{ }
1494
+
};
1495
+
1496
+
static struct clk_rcg2 gcc_usb20_master_clk_src = {
1497
+
.cmd_rcgr = 0x1c028,
1498
+
.mnd_width = 8,
1499
+
.hid_width = 5,
1500
+
.parent_map = gcc_parent_map_0,
1501
+
.freq_tbl = ftbl_gcc_usb20_master_clk_src,
1502
+
.clkr.hw.init = &(const struct clk_init_data){
1503
+
.name = "gcc_usb20_master_clk_src",
1504
+
.parent_data = gcc_parent_data_0,
1505
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1506
+
.ops = &clk_rcg2_shared_ops,
1507
+
},
1508
+
};
1509
+
1510
+
static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
1511
+
.cmd_rcgr = 0x1c040,
1512
+
.mnd_width = 0,
1513
+
.hid_width = 5,
1514
+
.parent_map = gcc_parent_map_0,
1515
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1516
+
.clkr.hw.init = &(const struct clk_init_data){
1517
+
.name = "gcc_usb20_mock_utmi_clk_src",
1518
+
.parent_data = gcc_parent_data_0,
1519
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1520
+
.ops = &clk_rcg2_shared_ops,
1521
+
},
1522
+
};
1523
+
1524
+
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1525
+
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1526
+
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1527
+
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1528
+
{ }
1529
+
};
1530
+
1531
+
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1532
+
.cmd_rcgr = 0x1b028,
1533
+
.mnd_width = 8,
1534
+
.hid_width = 5,
1535
+
.parent_map = gcc_parent_map_0,
1536
+
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1537
+
.clkr.hw.init = &(const struct clk_init_data){
1538
+
.name = "gcc_usb30_prim_master_clk_src",
1539
+
.parent_data = gcc_parent_data_0,
1540
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1541
+
.ops = &clk_rcg2_shared_ops,
1542
+
},
1543
+
};
1544
+
1545
+
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1546
+
.cmd_rcgr = 0x1b040,
1547
+
.mnd_width = 0,
1548
+
.hid_width = 5,
1549
+
.parent_map = gcc_parent_map_0,
1550
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1551
+
.clkr.hw.init = &(const struct clk_init_data){
1552
+
.name = "gcc_usb30_prim_mock_utmi_clk_src",
1553
+
.parent_data = gcc_parent_data_0,
1554
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1555
+
.ops = &clk_rcg2_shared_ops,
1556
+
},
1557
+
};
1558
+
1559
+
static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1560
+
.cmd_rcgr = 0x2f028,
1561
+
.mnd_width = 8,
1562
+
.hid_width = 5,
1563
+
.parent_map = gcc_parent_map_0,
1564
+
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1565
+
.clkr.hw.init = &(const struct clk_init_data){
1566
+
.name = "gcc_usb30_sec_master_clk_src",
1567
+
.parent_data = gcc_parent_data_0,
1568
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1569
+
.ops = &clk_rcg2_shared_ops,
1570
+
},
1571
+
};
1572
+
1573
+
static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1574
+
.cmd_rcgr = 0x2f040,
1575
+
.mnd_width = 0,
1576
+
.hid_width = 5,
1577
+
.parent_map = gcc_parent_map_0,
1578
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1579
+
.clkr.hw.init = &(const struct clk_init_data){
1580
+
.name = "gcc_usb30_sec_mock_utmi_clk_src",
1581
+
.parent_data = gcc_parent_data_0,
1582
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1583
+
.ops = &clk_rcg2_shared_ops,
1584
+
},
1585
+
};
1586
+
1587
+
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1588
+
.cmd_rcgr = 0x1b06c,
1589
+
.mnd_width = 0,
1590
+
.hid_width = 5,
1591
+
.parent_map = gcc_parent_map_3,
1592
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1593
+
.clkr.hw.init = &(const struct clk_init_data){
1594
+
.name = "gcc_usb3_prim_phy_aux_clk_src",
1595
+
.parent_data = gcc_parent_data_3,
1596
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1597
+
.ops = &clk_rcg2_shared_ops,
1598
+
},
1599
+
};
1600
+
1601
+
static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1602
+
.cmd_rcgr = 0x2f06c,
1603
+
.mnd_width = 0,
1604
+
.hid_width = 5,
1605
+
.parent_map = gcc_parent_map_3,
1606
+
.freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1607
+
.clkr.hw.init = &(const struct clk_init_data){
1608
+
.name = "gcc_usb3_sec_phy_aux_clk_src",
1609
+
.parent_data = gcc_parent_data_3,
1610
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1611
+
.ops = &clk_rcg2_shared_ops,
1612
+
},
1613
+
};
1614
+
1615
+
static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = {
1616
+
.reg = 0xa9070,
1617
+
.shift = 0,
1618
+
.width = 4,
1619
+
.clkr.hw.init = &(const struct clk_init_data) {
1620
+
.name = "gcc_pcie_0_pipe_div_clk_src",
1621
+
.parent_hws = (const struct clk_hw*[]){
1622
+
&gcc_pcie_0_pipe_clk_src.clkr.hw,
1623
+
},
1624
+
.num_parents = 1,
1625
+
.flags = CLK_SET_RATE_PARENT,
1626
+
.ops = &clk_regmap_div_ro_ops,
1627
+
},
1628
+
};
1629
+
1630
+
static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = {
1631
+
.reg = 0x77070,
1632
+
.shift = 0,
1633
+
.width = 4,
1634
+
.clkr.hw.init = &(const struct clk_init_data) {
1635
+
.name = "gcc_pcie_1_pipe_div_clk_src",
1636
+
.parent_hws = (const struct clk_hw*[]){
1637
+
&gcc_pcie_1_pipe_clk_src.clkr.hw,
1638
+
},
1639
+
.num_parents = 1,
1640
+
.flags = CLK_SET_RATE_PARENT,
1641
+
.ops = &clk_regmap_div_ro_ops,
1642
+
},
1643
+
};
1644
+
1645
+
static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = {
1646
+
.reg = 0xc4284,
1647
+
.shift = 0,
1648
+
.width = 4,
1649
+
.clkr.hw.init = &(const struct clk_init_data) {
1650
+
.name = "gcc_qupv3_wrap3_s0_div_clk_src",
1651
+
.parent_hws = (const struct clk_hw*[]){
1652
+
&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
1653
+
},
1654
+
.num_parents = 1,
1655
+
.flags = CLK_SET_RATE_PARENT,
1656
+
.ops = &clk_regmap_div_ro_ops,
1657
+
},
1658
+
};
1659
+
1660
+
static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
1661
+
.reg = 0x1c058,
1662
+
.shift = 0,
1663
+
.width = 4,
1664
+
.clkr.hw.init = &(const struct clk_init_data) {
1665
+
.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
1666
+
.parent_hws = (const struct clk_hw*[]){
1667
+
&gcc_usb20_mock_utmi_clk_src.clkr.hw,
1668
+
},
1669
+
.num_parents = 1,
1670
+
.flags = CLK_SET_RATE_PARENT,
1671
+
.ops = &clk_regmap_div_ro_ops,
1672
+
},
1673
+
};
1674
+
1675
+
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1676
+
.reg = 0x1b058,
1677
+
.shift = 0,
1678
+
.width = 4,
1679
+
.clkr.hw.init = &(const struct clk_init_data) {
1680
+
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1681
+
.parent_hws = (const struct clk_hw*[]){
1682
+
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1683
+
},
1684
+
.num_parents = 1,
1685
+
.flags = CLK_SET_RATE_PARENT,
1686
+
.ops = &clk_regmap_div_ro_ops,
1687
+
},
1688
+
};
1689
+
1690
+
static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1691
+
.reg = 0x2f058,
1692
+
.shift = 0,
1693
+
.width = 4,
1694
+
.clkr.hw.init = &(const struct clk_init_data) {
1695
+
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1696
+
.parent_hws = (const struct clk_hw*[]){
1697
+
&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1698
+
},
1699
+
.num_parents = 1,
1700
+
.flags = CLK_SET_RATE_PARENT,
1701
+
.ops = &clk_regmap_div_ro_ops,
1702
+
},
1703
+
};
1704
+
1705
+
static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = {
1706
+
.halt_reg = 0x8e200,
1707
+
.halt_check = BRANCH_HALT_VOTED,
1708
+
.hwcg_reg = 0x8e200,
1709
+
.hwcg_bit = 1,
1710
+
.clkr = {
1711
+
.enable_reg = 0x4b000,
1712
+
.enable_mask = BIT(28),
1713
+
.hw.init = &(const struct clk_init_data){
1714
+
.name = "gcc_aggre_noc_qupv3_axi_clk",
1715
+
.ops = &clk_branch2_ops,
1716
+
},
1717
+
},
1718
+
};
1719
+
1720
+
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1721
+
.halt_reg = 0x810d4,
1722
+
.halt_check = BRANCH_HALT_VOTED,
1723
+
.hwcg_reg = 0x810d4,
1724
+
.hwcg_bit = 1,
1725
+
.clkr = {
1726
+
.enable_reg = 0x810d4,
1727
+
.enable_mask = BIT(0),
1728
+
.hw.init = &(const struct clk_init_data){
1729
+
.name = "gcc_aggre_ufs_card_axi_clk",
1730
+
.parent_hws = (const struct clk_hw*[]){
1731
+
&gcc_ufs_card_axi_clk_src.clkr.hw,
1732
+
},
1733
+
.num_parents = 1,
1734
+
.flags = CLK_SET_RATE_PARENT,
1735
+
.ops = &clk_branch2_ops,
1736
+
},
1737
+
},
1738
+
};
1739
+
1740
+
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1741
+
.halt_reg = 0x830d4,
1742
+
.halt_check = BRANCH_HALT_VOTED,
1743
+
.hwcg_reg = 0x830d4,
1744
+
.hwcg_bit = 1,
1745
+
.clkr = {
1746
+
.enable_reg = 0x830d4,
1747
+
.enable_mask = BIT(0),
1748
+
.hw.init = &(const struct clk_init_data){
1749
+
.name = "gcc_aggre_ufs_phy_axi_clk",
1750
+
.parent_hws = (const struct clk_hw*[]){
1751
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
1752
+
},
1753
+
.num_parents = 1,
1754
+
.flags = CLK_SET_RATE_PARENT,
1755
+
.ops = &clk_branch2_ops,
1756
+
},
1757
+
},
1758
+
};
1759
+
1760
+
static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1761
+
.halt_reg = 0x830d4,
1762
+
.halt_check = BRANCH_HALT_VOTED,
1763
+
.hwcg_reg = 0x830d4,
1764
+
.hwcg_bit = 1,
1765
+
.clkr = {
1766
+
.enable_reg = 0x830d4,
1767
+
.enable_mask = BIT(1),
1768
+
.hw.init = &(const struct clk_init_data){
1769
+
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1770
+
.parent_hws = (const struct clk_hw*[]){
1771
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
1772
+
},
1773
+
.num_parents = 1,
1774
+
.flags = CLK_SET_RATE_PARENT,
1775
+
.ops = &clk_branch2_ops,
1776
+
},
1777
+
},
1778
+
};
1779
+
1780
+
static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
1781
+
.halt_reg = 0x1c05c,
1782
+
.halt_check = BRANCH_HALT_VOTED,
1783
+
.hwcg_reg = 0x1c05c,
1784
+
.hwcg_bit = 1,
1785
+
.clkr = {
1786
+
.enable_reg = 0x1c05c,
1787
+
.enable_mask = BIT(0),
1788
+
.hw.init = &(const struct clk_init_data){
1789
+
.name = "gcc_aggre_usb2_prim_axi_clk",
1790
+
.parent_hws = (const struct clk_hw*[]){
1791
+
&gcc_usb20_master_clk_src.clkr.hw,
1792
+
},
1793
+
.num_parents = 1,
1794
+
.flags = CLK_SET_RATE_PARENT,
1795
+
.ops = &clk_branch2_ops,
1796
+
},
1797
+
},
1798
+
};
1799
+
1800
+
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1801
+
.halt_reg = 0x1b084,
1802
+
.halt_check = BRANCH_HALT_VOTED,
1803
+
.hwcg_reg = 0x1b084,
1804
+
.hwcg_bit = 1,
1805
+
.clkr = {
1806
+
.enable_reg = 0x1b084,
1807
+
.enable_mask = BIT(0),
1808
+
.hw.init = &(const struct clk_init_data){
1809
+
.name = "gcc_aggre_usb3_prim_axi_clk",
1810
+
.parent_hws = (const struct clk_hw*[]){
1811
+
&gcc_usb30_prim_master_clk_src.clkr.hw,
1812
+
},
1813
+
.num_parents = 1,
1814
+
.flags = CLK_SET_RATE_PARENT,
1815
+
.ops = &clk_branch2_ops,
1816
+
},
1817
+
},
1818
+
};
1819
+
1820
+
static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1821
+
.halt_reg = 0x2f088,
1822
+
.halt_check = BRANCH_HALT_VOTED,
1823
+
.hwcg_reg = 0x2f088,
1824
+
.hwcg_bit = 1,
1825
+
.clkr = {
1826
+
.enable_reg = 0x2f088,
1827
+
.enable_mask = BIT(0),
1828
+
.hw.init = &(const struct clk_init_data){
1829
+
.name = "gcc_aggre_usb3_sec_axi_clk",
1830
+
.parent_hws = (const struct clk_hw*[]){
1831
+
&gcc_usb30_sec_master_clk_src.clkr.hw,
1832
+
},
1833
+
.num_parents = 1,
1834
+
.flags = CLK_SET_RATE_PARENT,
1835
+
.ops = &clk_branch2_ops,
1836
+
},
1837
+
},
1838
+
};
1839
+
1840
+
static struct clk_branch gcc_ahb2phy0_clk = {
1841
+
.halt_reg = 0x76004,
1842
+
.halt_check = BRANCH_HALT_VOTED,
1843
+
.hwcg_reg = 0x76004,
1844
+
.hwcg_bit = 1,
1845
+
.clkr = {
1846
+
.enable_reg = 0x76004,
1847
+
.enable_mask = BIT(0),
1848
+
.hw.init = &(const struct clk_init_data){
1849
+
.name = "gcc_ahb2phy0_clk",
1850
+
.ops = &clk_branch2_ops,
1851
+
},
1852
+
},
1853
+
};
1854
+
1855
+
static struct clk_branch gcc_ahb2phy2_clk = {
1856
+
.halt_reg = 0x76008,
1857
+
.halt_check = BRANCH_HALT_VOTED,
1858
+
.hwcg_reg = 0x76008,
1859
+
.hwcg_bit = 1,
1860
+
.clkr = {
1861
+
.enable_reg = 0x76008,
1862
+
.enable_mask = BIT(0),
1863
+
.hw.init = &(const struct clk_init_data){
1864
+
.name = "gcc_ahb2phy2_clk",
1865
+
.ops = &clk_branch2_ops,
1866
+
},
1867
+
},
1868
+
};
1869
+
1870
+
static struct clk_branch gcc_ahb2phy3_clk = {
1871
+
.halt_reg = 0x7600c,
1872
+
.halt_check = BRANCH_HALT_VOTED,
1873
+
.hwcg_reg = 0x7600c,
1874
+
.hwcg_bit = 1,
1875
+
.clkr = {
1876
+
.enable_reg = 0x7600c,
1877
+
.enable_mask = BIT(0),
1878
+
.hw.init = &(const struct clk_init_data){
1879
+
.name = "gcc_ahb2phy3_clk",
1880
+
.ops = &clk_branch2_ops,
1881
+
},
1882
+
},
1883
+
};
1884
+
1885
+
static struct clk_branch gcc_boot_rom_ahb_clk = {
1886
+
.halt_reg = 0x44004,
1887
+
.halt_check = BRANCH_HALT_VOTED,
1888
+
.hwcg_reg = 0x44004,
1889
+
.hwcg_bit = 1,
1890
+
.clkr = {
1891
+
.enable_reg = 0x4b000,
1892
+
.enable_mask = BIT(10),
1893
+
.hw.init = &(const struct clk_init_data){
1894
+
.name = "gcc_boot_rom_ahb_clk",
1895
+
.ops = &clk_branch2_ops,
1896
+
},
1897
+
},
1898
+
};
1899
+
1900
+
static struct clk_branch gcc_camera_hf_axi_clk = {
1901
+
.halt_reg = 0x32010,
1902
+
.halt_check = BRANCH_HALT_SKIP,
1903
+
.hwcg_reg = 0x32010,
1904
+
.hwcg_bit = 1,
1905
+
.clkr = {
1906
+
.enable_reg = 0x32010,
1907
+
.enable_mask = BIT(0),
1908
+
.hw.init = &(const struct clk_init_data){
1909
+
.name = "gcc_camera_hf_axi_clk",
1910
+
.ops = &clk_branch2_ops,
1911
+
},
1912
+
},
1913
+
};
1914
+
1915
+
static struct clk_branch gcc_camera_sf_axi_clk = {
1916
+
.halt_reg = 0x32018,
1917
+
.halt_check = BRANCH_HALT_SKIP,
1918
+
.hwcg_reg = 0x32018,
1919
+
.hwcg_bit = 1,
1920
+
.clkr = {
1921
+
.enable_reg = 0x32018,
1922
+
.enable_mask = BIT(0),
1923
+
.hw.init = &(const struct clk_init_data){
1924
+
.name = "gcc_camera_sf_axi_clk",
1925
+
.ops = &clk_branch2_ops,
1926
+
},
1927
+
},
1928
+
};
1929
+
1930
+
static struct clk_branch gcc_camera_throttle_xo_clk = {
1931
+
.halt_reg = 0x32024,
1932
+
.halt_check = BRANCH_HALT,
1933
+
.clkr = {
1934
+
.enable_reg = 0x32024,
1935
+
.enable_mask = BIT(0),
1936
+
.hw.init = &(const struct clk_init_data){
1937
+
.name = "gcc_camera_throttle_xo_clk",
1938
+
.ops = &clk_branch2_ops,
1939
+
},
1940
+
},
1941
+
};
1942
+
1943
+
static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
1944
+
.halt_reg = 0x1c060,
1945
+
.halt_check = BRANCH_HALT_VOTED,
1946
+
.hwcg_reg = 0x1c060,
1947
+
.hwcg_bit = 1,
1948
+
.clkr = {
1949
+
.enable_reg = 0x1c060,
1950
+
.enable_mask = BIT(0),
1951
+
.hw.init = &(const struct clk_init_data){
1952
+
.name = "gcc_cfg_noc_usb2_prim_axi_clk",
1953
+
.parent_hws = (const struct clk_hw*[]){
1954
+
&gcc_usb20_master_clk_src.clkr.hw,
1955
+
},
1956
+
.num_parents = 1,
1957
+
.flags = CLK_SET_RATE_PARENT,
1958
+
.ops = &clk_branch2_ops,
1959
+
},
1960
+
},
1961
+
};
1962
+
1963
+
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1964
+
.halt_reg = 0x1b088,
1965
+
.halt_check = BRANCH_HALT_VOTED,
1966
+
.hwcg_reg = 0x1b088,
1967
+
.hwcg_bit = 1,
1968
+
.clkr = {
1969
+
.enable_reg = 0x1b088,
1970
+
.enable_mask = BIT(0),
1971
+
.hw.init = &(const struct clk_init_data){
1972
+
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1973
+
.parent_hws = (const struct clk_hw*[]){
1974
+
&gcc_usb30_prim_master_clk_src.clkr.hw,
1975
+
},
1976
+
.num_parents = 1,
1977
+
.flags = CLK_SET_RATE_PARENT,
1978
+
.ops = &clk_branch2_ops,
1979
+
},
1980
+
},
1981
+
};
1982
+
1983
+
static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1984
+
.halt_reg = 0x2f084,
1985
+
.halt_check = BRANCH_HALT_VOTED,
1986
+
.hwcg_reg = 0x2f084,
1987
+
.hwcg_bit = 1,
1988
+
.clkr = {
1989
+
.enable_reg = 0x2f084,
1990
+
.enable_mask = BIT(0),
1991
+
.hw.init = &(const struct clk_init_data){
1992
+
.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1993
+
.parent_hws = (const struct clk_hw*[]){
1994
+
&gcc_usb30_sec_master_clk_src.clkr.hw,
1995
+
},
1996
+
.num_parents = 1,
1997
+
.flags = CLK_SET_RATE_PARENT,
1998
+
.ops = &clk_branch2_ops,
1999
+
},
2000
+
},
2001
+
};
2002
+
2003
+
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
2004
+
.halt_reg = 0x7d164,
2005
+
.halt_check = BRANCH_HALT_VOTED,
2006
+
.hwcg_reg = 0x7d164,
2007
+
.hwcg_bit = 1,
2008
+
.clkr = {
2009
+
.enable_reg = 0x7d164,
2010
+
.enable_mask = BIT(0),
2011
+
.hw.init = &(const struct clk_init_data){
2012
+
.name = "gcc_ddrss_gpu_axi_clk",
2013
+
.ops = &clk_branch2_aon_ops,
2014
+
},
2015
+
},
2016
+
};
2017
+
2018
+
static struct clk_branch gcc_disp1_hf_axi_clk = {
2019
+
.halt_reg = 0xc7010,
2020
+
.halt_check = BRANCH_HALT_VOTED,
2021
+
.hwcg_reg = 0xc7010,
2022
+
.hwcg_bit = 1,
2023
+
.clkr = {
2024
+
.enable_reg = 0xc7010,
2025
+
.enable_mask = BIT(0),
2026
+
.hw.init = &(const struct clk_init_data){
2027
+
.name = "gcc_disp1_hf_axi_clk",
2028
+
.ops = &clk_branch2_ops,
2029
+
},
2030
+
},
2031
+
};
2032
+
2033
+
static struct clk_branch gcc_disp_hf_axi_clk = {
2034
+
.halt_reg = 0x33010,
2035
+
.halt_check = BRANCH_HALT_VOTED,
2036
+
.hwcg_reg = 0x33010,
2037
+
.hwcg_bit = 1,
2038
+
.clkr = {
2039
+
.enable_reg = 0x33010,
2040
+
.enable_mask = BIT(0),
2041
+
.hw.init = &(const struct clk_init_data){
2042
+
.name = "gcc_disp_hf_axi_clk",
2043
+
.ops = &clk_branch2_ops,
2044
+
},
2045
+
},
2046
+
};
2047
+
2048
+
static struct clk_branch gcc_edp_ref_clkref_en = {
2049
+
.halt_reg = 0x97448,
2050
+
.halt_check = BRANCH_HALT_DELAY,
2051
+
.clkr = {
2052
+
.enable_reg = 0x97448,
2053
+
.enable_mask = BIT(0),
2054
+
.hw.init = &(const struct clk_init_data){
2055
+
.name = "gcc_edp_ref_clkref_en",
2056
+
.ops = &clk_branch2_ops,
2057
+
},
2058
+
},
2059
+
};
2060
+
2061
+
static struct clk_branch gcc_emac0_axi_clk = {
2062
+
.halt_reg = 0xb6018,
2063
+
.halt_check = BRANCH_HALT_VOTED,
2064
+
.hwcg_reg = 0xb6018,
2065
+
.hwcg_bit = 1,
2066
+
.clkr = {
2067
+
.enable_reg = 0xb6018,
2068
+
.enable_mask = BIT(0),
2069
+
.hw.init = &(const struct clk_init_data){
2070
+
.name = "gcc_emac0_axi_clk",
2071
+
.ops = &clk_branch2_ops,
2072
+
},
2073
+
},
2074
+
};
2075
+
2076
+
static struct clk_branch gcc_emac0_phy_aux_clk = {
2077
+
.halt_reg = 0xb6024,
2078
+
.halt_check = BRANCH_HALT,
2079
+
.clkr = {
2080
+
.enable_reg = 0xb6024,
2081
+
.enable_mask = BIT(0),
2082
+
.hw.init = &(const struct clk_init_data){
2083
+
.name = "gcc_emac0_phy_aux_clk",
2084
+
.parent_hws = (const struct clk_hw*[]){
2085
+
&gcc_emac0_phy_aux_clk_src.clkr.hw,
2086
+
},
2087
+
.num_parents = 1,
2088
+
.flags = CLK_SET_RATE_PARENT,
2089
+
.ops = &clk_branch2_ops,
2090
+
},
2091
+
},
2092
+
};
2093
+
2094
+
static struct clk_branch gcc_emac0_ptp_clk = {
2095
+
.halt_reg = 0xb6040,
2096
+
.halt_check = BRANCH_HALT,
2097
+
.clkr = {
2098
+
.enable_reg = 0xb6040,
2099
+
.enable_mask = BIT(0),
2100
+
.hw.init = &(const struct clk_init_data){
2101
+
.name = "gcc_emac0_ptp_clk",
2102
+
.parent_hws = (const struct clk_hw*[]){
2103
+
&gcc_emac0_ptp_clk_src.clkr.hw,
2104
+
},
2105
+
.num_parents = 1,
2106
+
.flags = CLK_SET_RATE_PARENT,
2107
+
.ops = &clk_branch2_ops,
2108
+
},
2109
+
},
2110
+
};
2111
+
2112
+
static struct clk_branch gcc_emac0_rgmii_clk = {
2113
+
.halt_reg = 0xb6044,
2114
+
.halt_check = BRANCH_HALT,
2115
+
.clkr = {
2116
+
.enable_reg = 0xb6044,
2117
+
.enable_mask = BIT(0),
2118
+
.hw.init = &(const struct clk_init_data){
2119
+
.name = "gcc_emac0_rgmii_clk",
2120
+
.parent_hws = (const struct clk_hw*[]){
2121
+
&gcc_emac0_rgmii_clk_src.clkr.hw,
2122
+
},
2123
+
.num_parents = 1,
2124
+
.flags = CLK_SET_RATE_PARENT,
2125
+
.ops = &clk_branch2_ops,
2126
+
},
2127
+
},
2128
+
};
2129
+
2130
+
static struct clk_branch gcc_emac0_slv_ahb_clk = {
2131
+
.halt_reg = 0xb6020,
2132
+
.halt_check = BRANCH_HALT_VOTED,
2133
+
.hwcg_reg = 0xb6020,
2134
+
.hwcg_bit = 1,
2135
+
.clkr = {
2136
+
.enable_reg = 0xb6020,
2137
+
.enable_mask = BIT(0),
2138
+
.hw.init = &(const struct clk_init_data){
2139
+
.name = "gcc_emac0_slv_ahb_clk",
2140
+
.ops = &clk_branch2_ops,
2141
+
},
2142
+
},
2143
+
};
2144
+
2145
+
static struct clk_branch gcc_emac1_axi_clk = {
2146
+
.halt_reg = 0xb4018,
2147
+
.halt_check = BRANCH_HALT_VOTED,
2148
+
.hwcg_reg = 0xb4018,
2149
+
.hwcg_bit = 1,
2150
+
.clkr = {
2151
+
.enable_reg = 0xb4018,
2152
+
.enable_mask = BIT(0),
2153
+
.hw.init = &(const struct clk_init_data){
2154
+
.name = "gcc_emac1_axi_clk",
2155
+
.ops = &clk_branch2_ops,
2156
+
},
2157
+
},
2158
+
};
2159
+
2160
+
static struct clk_branch gcc_emac1_phy_aux_clk = {
2161
+
.halt_reg = 0xb4024,
2162
+
.halt_check = BRANCH_HALT,
2163
+
.clkr = {
2164
+
.enable_reg = 0xb4024,
2165
+
.enable_mask = BIT(0),
2166
+
.hw.init = &(const struct clk_init_data){
2167
+
.name = "gcc_emac1_phy_aux_clk",
2168
+
.parent_hws = (const struct clk_hw*[]){
2169
+
&gcc_emac1_phy_aux_clk_src.clkr.hw,
2170
+
},
2171
+
.num_parents = 1,
2172
+
.flags = CLK_SET_RATE_PARENT,
2173
+
.ops = &clk_branch2_ops,
2174
+
},
2175
+
},
2176
+
};
2177
+
2178
+
static struct clk_branch gcc_emac1_ptp_clk = {
2179
+
.halt_reg = 0xb4040,
2180
+
.halt_check = BRANCH_HALT,
2181
+
.clkr = {
2182
+
.enable_reg = 0xb4040,
2183
+
.enable_mask = BIT(0),
2184
+
.hw.init = &(const struct clk_init_data){
2185
+
.name = "gcc_emac1_ptp_clk",
2186
+
.parent_hws = (const struct clk_hw*[]){
2187
+
&gcc_emac1_ptp_clk_src.clkr.hw,
2188
+
},
2189
+
.num_parents = 1,
2190
+
.flags = CLK_SET_RATE_PARENT,
2191
+
.ops = &clk_branch2_ops,
2192
+
},
2193
+
},
2194
+
};
2195
+
2196
+
static struct clk_branch gcc_emac1_rgmii_clk = {
2197
+
.halt_reg = 0xb4044,
2198
+
.halt_check = BRANCH_HALT,
2199
+
.clkr = {
2200
+
.enable_reg = 0xb4044,
2201
+
.enable_mask = BIT(0),
2202
+
.hw.init = &(const struct clk_init_data){
2203
+
.name = "gcc_emac1_rgmii_clk",
2204
+
.parent_hws = (const struct clk_hw*[]){
2205
+
&gcc_emac1_rgmii_clk_src.clkr.hw,
2206
+
},
2207
+
.num_parents = 1,
2208
+
.flags = CLK_SET_RATE_PARENT,
2209
+
.ops = &clk_branch2_ops,
2210
+
},
2211
+
},
2212
+
};
2213
+
2214
+
static struct clk_branch gcc_emac1_slv_ahb_clk = {
2215
+
.halt_reg = 0xb4020,
2216
+
.halt_check = BRANCH_HALT_VOTED,
2217
+
.hwcg_reg = 0xb4020,
2218
+
.hwcg_bit = 1,
2219
+
.clkr = {
2220
+
.enable_reg = 0xb4020,
2221
+
.enable_mask = BIT(0),
2222
+
.hw.init = &(const struct clk_init_data){
2223
+
.name = "gcc_emac1_slv_ahb_clk",
2224
+
.ops = &clk_branch2_ops,
2225
+
},
2226
+
},
2227
+
};
2228
+
2229
+
static struct clk_branch gcc_gp1_clk = {
2230
+
.halt_reg = 0x70000,
2231
+
.halt_check = BRANCH_HALT,
2232
+
.clkr = {
2233
+
.enable_reg = 0x70000,
2234
+
.enable_mask = BIT(0),
2235
+
.hw.init = &(const struct clk_init_data){
2236
+
.name = "gcc_gp1_clk",
2237
+
.parent_hws = (const struct clk_hw*[]){
2238
+
&gcc_gp1_clk_src.clkr.hw,
2239
+
},
2240
+
.num_parents = 1,
2241
+
.flags = CLK_SET_RATE_PARENT,
2242
+
.ops = &clk_branch2_ops,
2243
+
},
2244
+
},
2245
+
};
2246
+
2247
+
static struct clk_branch gcc_gp2_clk = {
2248
+
.halt_reg = 0x71000,
2249
+
.halt_check = BRANCH_HALT,
2250
+
.clkr = {
2251
+
.enable_reg = 0x71000,
2252
+
.enable_mask = BIT(0),
2253
+
.hw.init = &(const struct clk_init_data){
2254
+
.name = "gcc_gp2_clk",
2255
+
.parent_hws = (const struct clk_hw*[]){
2256
+
&gcc_gp2_clk_src.clkr.hw,
2257
+
},
2258
+
.num_parents = 1,
2259
+
.flags = CLK_SET_RATE_PARENT,
2260
+
.ops = &clk_branch2_ops,
2261
+
},
2262
+
},
2263
+
};
2264
+
2265
+
static struct clk_branch gcc_gp3_clk = {
2266
+
.halt_reg = 0x62000,
2267
+
.halt_check = BRANCH_HALT,
2268
+
.clkr = {
2269
+
.enable_reg = 0x62000,
2270
+
.enable_mask = BIT(0),
2271
+
.hw.init = &(const struct clk_init_data){
2272
+
.name = "gcc_gp3_clk",
2273
+
.parent_hws = (const struct clk_hw*[]){
2274
+
&gcc_gp3_clk_src.clkr.hw,
2275
+
},
2276
+
.num_parents = 1,
2277
+
.flags = CLK_SET_RATE_PARENT,
2278
+
.ops = &clk_branch2_ops,
2279
+
},
2280
+
},
2281
+
};
2282
+
2283
+
static struct clk_branch gcc_gp4_clk = {
2284
+
.halt_reg = 0x1e000,
2285
+
.halt_check = BRANCH_HALT,
2286
+
.clkr = {
2287
+
.enable_reg = 0x1e000,
2288
+
.enable_mask = BIT(0),
2289
+
.hw.init = &(const struct clk_init_data){
2290
+
.name = "gcc_gp4_clk",
2291
+
.parent_hws = (const struct clk_hw*[]){
2292
+
&gcc_gp4_clk_src.clkr.hw,
2293
+
},
2294
+
.num_parents = 1,
2295
+
.flags = CLK_SET_RATE_PARENT,
2296
+
.ops = &clk_branch2_ops,
2297
+
},
2298
+
},
2299
+
};
2300
+
2301
+
static struct clk_branch gcc_gp5_clk = {
2302
+
.halt_reg = 0x1f000,
2303
+
.halt_check = BRANCH_HALT,
2304
+
.clkr = {
2305
+
.enable_reg = 0x1f000,
2306
+
.enable_mask = BIT(0),
2307
+
.hw.init = &(const struct clk_init_data){
2308
+
.name = "gcc_gp5_clk",
2309
+
.parent_hws = (const struct clk_hw*[]){
2310
+
&gcc_gp5_clk_src.clkr.hw,
2311
+
},
2312
+
.num_parents = 1,
2313
+
.flags = CLK_SET_RATE_PARENT,
2314
+
.ops = &clk_branch2_ops,
2315
+
},
2316
+
},
2317
+
};
2318
+
2319
+
static struct clk_branch gcc_gpu_gpll0_clk_src = {
2320
+
.halt_check = BRANCH_HALT_DELAY,
2321
+
.clkr = {
2322
+
.enable_reg = 0x4b000,
2323
+
.enable_mask = BIT(15),
2324
+
.hw.init = &(const struct clk_init_data){
2325
+
.name = "gcc_gpu_gpll0_clk_src",
2326
+
.parent_hws = (const struct clk_hw*[]){
2327
+
&gcc_gpll0.clkr.hw,
2328
+
},
2329
+
.num_parents = 1,
2330
+
.flags = CLK_SET_RATE_PARENT,
2331
+
.ops = &clk_branch2_ops,
2332
+
},
2333
+
},
2334
+
};
2335
+
2336
+
static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2337
+
.halt_check = BRANCH_HALT_DELAY,
2338
+
.clkr = {
2339
+
.enable_reg = 0x4b000,
2340
+
.enable_mask = BIT(16),
2341
+
.hw.init = &(const struct clk_init_data){
2342
+
.name = "gcc_gpu_gpll0_div_clk_src",
2343
+
.parent_hws = (const struct clk_hw*[]){
2344
+
&gcc_gpll0_out_even.clkr.hw,
2345
+
},
2346
+
.num_parents = 1,
2347
+
.flags = CLK_SET_RATE_PARENT,
2348
+
.ops = &clk_branch2_ops,
2349
+
},
2350
+
},
2351
+
};
2352
+
2353
+
static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2354
+
.halt_reg = 0x7d010,
2355
+
.halt_check = BRANCH_HALT_VOTED,
2356
+
.hwcg_reg = 0x7d010,
2357
+
.hwcg_bit = 1,
2358
+
.clkr = {
2359
+
.enable_reg = 0x7d010,
2360
+
.enable_mask = BIT(0),
2361
+
.hw.init = &(const struct clk_init_data){
2362
+
.name = "gcc_gpu_memnoc_gfx_clk",
2363
+
.ops = &clk_branch2_aon_ops,
2364
+
},
2365
+
},
2366
+
};
2367
+
2368
+
static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2369
+
.halt_reg = 0x7d01c,
2370
+
.halt_check = BRANCH_HALT_DELAY,
2371
+
.clkr = {
2372
+
.enable_reg = 0x7d01c,
2373
+
.enable_mask = BIT(0),
2374
+
.hw.init = &(const struct clk_init_data){
2375
+
.name = "gcc_gpu_snoc_dvm_gfx_clk",
2376
+
.ops = &clk_branch2_aon_ops,
2377
+
},
2378
+
},
2379
+
};
2380
+
2381
+
static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {
2382
+
.halt_reg = 0x7d008,
2383
+
.halt_check = BRANCH_HALT_VOTED,
2384
+
.hwcg_reg = 0x7d008,
2385
+
.hwcg_bit = 1,
2386
+
.clkr = {
2387
+
.enable_reg = 0x7d008,
2388
+
.enable_mask = BIT(0),
2389
+
.hw.init = &(const struct clk_init_data){
2390
+
.name = "gcc_gpu_tcu_throttle_ahb_clk",
2391
+
.ops = &clk_branch2_ops,
2392
+
},
2393
+
},
2394
+
};
2395
+
2396
+
static struct clk_branch gcc_gpu_tcu_throttle_clk = {
2397
+
.halt_reg = 0x7d014,
2398
+
.halt_check = BRANCH_HALT_VOTED,
2399
+
.hwcg_reg = 0x7d014,
2400
+
.hwcg_bit = 1,
2401
+
.clkr = {
2402
+
.enable_reg = 0x7d014,
2403
+
.enable_mask = BIT(0),
2404
+
.hw.init = &(const struct clk_init_data){
2405
+
.name = "gcc_gpu_tcu_throttle_clk",
2406
+
.ops = &clk_branch2_ops,
2407
+
},
2408
+
},
2409
+
};
2410
+
2411
+
static struct clk_branch gcc_pcie_0_aux_clk = {
2412
+
.halt_reg = 0xa9038,
2413
+
.halt_check = BRANCH_HALT_VOTED,
2414
+
.clkr = {
2415
+
.enable_reg = 0x4b010,
2416
+
.enable_mask = BIT(16),
2417
+
.hw.init = &(const struct clk_init_data){
2418
+
.name = "gcc_pcie_0_aux_clk",
2419
+
.parent_hws = (const struct clk_hw*[]){
2420
+
&gcc_pcie_0_aux_clk_src.clkr.hw,
2421
+
},
2422
+
.num_parents = 1,
2423
+
.flags = CLK_SET_RATE_PARENT,
2424
+
.ops = &clk_branch2_ops,
2425
+
},
2426
+
},
2427
+
};
2428
+
2429
+
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2430
+
.halt_reg = 0xa902c,
2431
+
.halt_check = BRANCH_HALT_VOTED,
2432
+
.hwcg_reg = 0xa902c,
2433
+
.hwcg_bit = 1,
2434
+
.clkr = {
2435
+
.enable_reg = 0x4b010,
2436
+
.enable_mask = BIT(12),
2437
+
.hw.init = &(const struct clk_init_data){
2438
+
.name = "gcc_pcie_0_cfg_ahb_clk",
2439
+
.ops = &clk_branch2_ops,
2440
+
},
2441
+
},
2442
+
};
2443
+
2444
+
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2445
+
.halt_reg = 0xa9024,
2446
+
.halt_check = BRANCH_HALT_VOTED,
2447
+
.clkr = {
2448
+
.enable_reg = 0x4b010,
2449
+
.enable_mask = BIT(11),
2450
+
.hw.init = &(const struct clk_init_data){
2451
+
.name = "gcc_pcie_0_mstr_axi_clk",
2452
+
.ops = &clk_branch2_ops,
2453
+
},
2454
+
},
2455
+
};
2456
+
2457
+
static struct clk_branch gcc_pcie_0_phy_aux_clk = {
2458
+
.halt_reg = 0xa9030,
2459
+
.halt_check = BRANCH_HALT_VOTED,
2460
+
.clkr = {
2461
+
.enable_reg = 0x4b010,
2462
+
.enable_mask = BIT(13),
2463
+
.hw.init = &(const struct clk_init_data){
2464
+
.name = "gcc_pcie_0_phy_aux_clk",
2465
+
.parent_hws = (const struct clk_hw*[]){
2466
+
&gcc_pcie_0_phy_aux_clk_src.clkr.hw,
2467
+
},
2468
+
.num_parents = 1,
2469
+
.flags = CLK_SET_RATE_PARENT,
2470
+
.ops = &clk_branch2_ops,
2471
+
},
2472
+
},
2473
+
};
2474
+
2475
+
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
2476
+
.halt_reg = 0xa9050,
2477
+
.halt_check = BRANCH_HALT_VOTED,
2478
+
.clkr = {
2479
+
.enable_reg = 0x4b010,
2480
+
.enable_mask = BIT(15),
2481
+
.hw.init = &(const struct clk_init_data){
2482
+
.name = "gcc_pcie_0_phy_rchng_clk",
2483
+
.parent_hws = (const struct clk_hw*[]){
2484
+
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
2485
+
},
2486
+
.num_parents = 1,
2487
+
.flags = CLK_SET_RATE_PARENT,
2488
+
.ops = &clk_branch2_ops,
2489
+
},
2490
+
},
2491
+
};
2492
+
2493
+
static struct clk_branch gcc_pcie_0_pipe_clk = {
2494
+
.halt_reg = 0xa9040,
2495
+
.halt_check = BRANCH_HALT_SKIP,
2496
+
.clkr = {
2497
+
.enable_reg = 0x4b010,
2498
+
.enable_mask = BIT(14),
2499
+
.hw.init = &(const struct clk_init_data){
2500
+
.name = "gcc_pcie_0_pipe_clk",
2501
+
.parent_hws = (const struct clk_hw*[]){
2502
+
&gcc_pcie_0_pipe_clk_src.clkr.hw,
2503
+
},
2504
+
.num_parents = 1,
2505
+
.flags = CLK_SET_RATE_PARENT,
2506
+
.ops = &clk_branch2_ops,
2507
+
},
2508
+
},
2509
+
};
2510
+
2511
+
static struct clk_branch gcc_pcie_0_pipediv2_clk = {
2512
+
.halt_reg = 0xa9048,
2513
+
.halt_check = BRANCH_HALT_SKIP,
2514
+
.clkr = {
2515
+
.enable_reg = 0x4b018,
2516
+
.enable_mask = BIT(22),
2517
+
.hw.init = &(const struct clk_init_data){
2518
+
.name = "gcc_pcie_0_pipediv2_clk",
2519
+
.parent_hws = (const struct clk_hw*[]){
2520
+
&gcc_pcie_0_pipe_div_clk_src.clkr.hw,
2521
+
},
2522
+
.num_parents = 1,
2523
+
.flags = CLK_SET_RATE_PARENT,
2524
+
.ops = &clk_branch2_ops,
2525
+
},
2526
+
},
2527
+
};
2528
+
2529
+
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2530
+
.halt_reg = 0xa901c,
2531
+
.halt_check = BRANCH_HALT_VOTED,
2532
+
.clkr = {
2533
+
.enable_reg = 0x4b010,
2534
+
.enable_mask = BIT(10),
2535
+
.hw.init = &(const struct clk_init_data){
2536
+
.name = "gcc_pcie_0_slv_axi_clk",
2537
+
.ops = &clk_branch2_ops,
2538
+
},
2539
+
},
2540
+
};
2541
+
2542
+
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2543
+
.halt_reg = 0xa9018,
2544
+
.halt_check = BRANCH_HALT_VOTED,
2545
+
.clkr = {
2546
+
.enable_reg = 0x4b018,
2547
+
.enable_mask = BIT(12),
2548
+
.hw.init = &(const struct clk_init_data){
2549
+
.name = "gcc_pcie_0_slv_q2a_axi_clk",
2550
+
.ops = &clk_branch2_ops,
2551
+
},
2552
+
},
2553
+
};
2554
+
2555
+
static struct clk_branch gcc_pcie_1_aux_clk = {
2556
+
.halt_reg = 0x77038,
2557
+
.halt_check = BRANCH_HALT_VOTED,
2558
+
.clkr = {
2559
+
.enable_reg = 0x4b000,
2560
+
.enable_mask = BIT(31),
2561
+
.hw.init = &(const struct clk_init_data){
2562
+
.name = "gcc_pcie_1_aux_clk",
2563
+
.parent_hws = (const struct clk_hw*[]){
2564
+
&gcc_pcie_1_aux_clk_src.clkr.hw,
2565
+
},
2566
+
.num_parents = 1,
2567
+
.flags = CLK_SET_RATE_PARENT,
2568
+
.ops = &clk_branch2_ops,
2569
+
},
2570
+
},
2571
+
};
2572
+
2573
+
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2574
+
.halt_reg = 0x7702c,
2575
+
.halt_check = BRANCH_HALT_VOTED,
2576
+
.hwcg_reg = 0x7702c,
2577
+
.hwcg_bit = 1,
2578
+
.clkr = {
2579
+
.enable_reg = 0x4b008,
2580
+
.enable_mask = BIT(2),
2581
+
.hw.init = &(const struct clk_init_data){
2582
+
.name = "gcc_pcie_1_cfg_ahb_clk",
2583
+
.ops = &clk_branch2_ops,
2584
+
},
2585
+
},
2586
+
};
2587
+
2588
+
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2589
+
.halt_reg = 0x77024,
2590
+
.halt_check = BRANCH_HALT_VOTED,
2591
+
.clkr = {
2592
+
.enable_reg = 0x4b008,
2593
+
.enable_mask = BIT(1),
2594
+
.hw.init = &(const struct clk_init_data){
2595
+
.name = "gcc_pcie_1_mstr_axi_clk",
2596
+
.ops = &clk_branch2_ops,
2597
+
},
2598
+
},
2599
+
};
2600
+
2601
+
static struct clk_branch gcc_pcie_1_phy_aux_clk = {
2602
+
.halt_reg = 0x77030,
2603
+
.halt_check = BRANCH_HALT_VOTED,
2604
+
.clkr = {
2605
+
.enable_reg = 0x4b008,
2606
+
.enable_mask = BIT(3),
2607
+
.hw.init = &(const struct clk_init_data){
2608
+
.name = "gcc_pcie_1_phy_aux_clk",
2609
+
.parent_hws = (const struct clk_hw*[]){
2610
+
&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
2611
+
},
2612
+
.num_parents = 1,
2613
+
.flags = CLK_SET_RATE_PARENT,
2614
+
.ops = &clk_branch2_ops,
2615
+
},
2616
+
},
2617
+
};
2618
+
2619
+
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
2620
+
.halt_reg = 0x77050,
2621
+
.halt_check = BRANCH_HALT_VOTED,
2622
+
.clkr = {
2623
+
.enable_reg = 0x4b000,
2624
+
.enable_mask = BIT(22),
2625
+
.hw.init = &(const struct clk_init_data){
2626
+
.name = "gcc_pcie_1_phy_rchng_clk",
2627
+
.parent_hws = (const struct clk_hw*[]){
2628
+
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
2629
+
},
2630
+
.num_parents = 1,
2631
+
.flags = CLK_SET_RATE_PARENT,
2632
+
.ops = &clk_branch2_ops,
2633
+
},
2634
+
},
2635
+
};
2636
+
2637
+
static struct clk_branch gcc_pcie_1_pipe_clk = {
2638
+
.halt_reg = 0x77040,
2639
+
.halt_check = BRANCH_HALT_SKIP,
2640
+
.clkr = {
2641
+
.enable_reg = 0x4b008,
2642
+
.enable_mask = BIT(4),
2643
+
.hw.init = &(const struct clk_init_data){
2644
+
.name = "gcc_pcie_1_pipe_clk",
2645
+
.parent_hws = (const struct clk_hw*[]){
2646
+
&gcc_pcie_1_pipe_clk_src.clkr.hw,
2647
+
},
2648
+
.num_parents = 1,
2649
+
.flags = CLK_SET_RATE_PARENT,
2650
+
.ops = &clk_branch2_ops,
2651
+
},
2652
+
},
2653
+
};
2654
+
2655
+
static struct clk_branch gcc_pcie_1_pipediv2_clk = {
2656
+
.halt_reg = 0x77048,
2657
+
.halt_check = BRANCH_HALT_SKIP,
2658
+
.clkr = {
2659
+
.enable_reg = 0x4b018,
2660
+
.enable_mask = BIT(16),
2661
+
.hw.init = &(const struct clk_init_data){
2662
+
.name = "gcc_pcie_1_pipediv2_clk",
2663
+
.parent_hws = (const struct clk_hw*[]){
2664
+
&gcc_pcie_1_pipe_div_clk_src.clkr.hw,
2665
+
},
2666
+
.num_parents = 1,
2667
+
.flags = CLK_SET_RATE_PARENT,
2668
+
.ops = &clk_branch2_ops,
2669
+
},
2670
+
},
2671
+
};
2672
+
2673
+
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2674
+
.halt_reg = 0x7701c,
2675
+
.halt_check = BRANCH_HALT_VOTED,
2676
+
.clkr = {
2677
+
.enable_reg = 0x4b008,
2678
+
.enable_mask = BIT(0),
2679
+
.hw.init = &(const struct clk_init_data){
2680
+
.name = "gcc_pcie_1_slv_axi_clk",
2681
+
.ops = &clk_branch2_ops,
2682
+
},
2683
+
},
2684
+
};
2685
+
2686
+
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2687
+
.halt_reg = 0x77018,
2688
+
.halt_check = BRANCH_HALT_VOTED,
2689
+
.clkr = {
2690
+
.enable_reg = 0x4b008,
2691
+
.enable_mask = BIT(5),
2692
+
.hw.init = &(const struct clk_init_data){
2693
+
.name = "gcc_pcie_1_slv_q2a_axi_clk",
2694
+
.ops = &clk_branch2_ops,
2695
+
},
2696
+
},
2697
+
};
2698
+
2699
+
static struct clk_branch gcc_pcie_clkref_en = {
2700
+
.halt_reg = 0x9746c,
2701
+
.halt_check = BRANCH_HALT_DELAY,
2702
+
.clkr = {
2703
+
.enable_reg = 0x9746c,
2704
+
.enable_mask = BIT(0),
2705
+
.hw.init = &(const struct clk_init_data){
2706
+
.name = "gcc_pcie_clkref_en",
2707
+
.ops = &clk_branch2_ops,
2708
+
},
2709
+
},
2710
+
};
2711
+
2712
+
static struct clk_branch gcc_pcie_throttle_cfg_clk = {
2713
+
.halt_reg = 0xb2034,
2714
+
.halt_check = BRANCH_HALT_VOTED,
2715
+
.clkr = {
2716
+
.enable_reg = 0x4b020,
2717
+
.enable_mask = BIT(15),
2718
+
.hw.init = &(const struct clk_init_data){
2719
+
.name = "gcc_pcie_throttle_cfg_clk",
2720
+
.ops = &clk_branch2_ops,
2721
+
},
2722
+
},
2723
+
};
2724
+
2725
+
static struct clk_branch gcc_pdm2_clk = {
2726
+
.halt_reg = 0x3f00c,
2727
+
.halt_check = BRANCH_HALT,
2728
+
.clkr = {
2729
+
.enable_reg = 0x3f00c,
2730
+
.enable_mask = BIT(0),
2731
+
.hw.init = &(const struct clk_init_data){
2732
+
.name = "gcc_pdm2_clk",
2733
+
.parent_hws = (const struct clk_hw*[]){
2734
+
&gcc_pdm2_clk_src.clkr.hw,
2735
+
},
2736
+
.num_parents = 1,
2737
+
.flags = CLK_SET_RATE_PARENT,
2738
+
.ops = &clk_branch2_ops,
2739
+
},
2740
+
},
2741
+
};
2742
+
2743
+
static struct clk_branch gcc_pdm_ahb_clk = {
2744
+
.halt_reg = 0x3f004,
2745
+
.halt_check = BRANCH_HALT_VOTED,
2746
+
.hwcg_reg = 0x3f004,
2747
+
.hwcg_bit = 1,
2748
+
.clkr = {
2749
+
.enable_reg = 0x3f004,
2750
+
.enable_mask = BIT(0),
2751
+
.hw.init = &(const struct clk_init_data){
2752
+
.name = "gcc_pdm_ahb_clk",
2753
+
.ops = &clk_branch2_ops,
2754
+
},
2755
+
},
2756
+
};
2757
+
2758
+
static struct clk_branch gcc_pdm_xo4_clk = {
2759
+
.halt_reg = 0x3f008,
2760
+
.halt_check = BRANCH_HALT,
2761
+
.clkr = {
2762
+
.enable_reg = 0x3f008,
2763
+
.enable_mask = BIT(0),
2764
+
.hw.init = &(const struct clk_init_data){
2765
+
.name = "gcc_pdm_xo4_clk",
2766
+
.ops = &clk_branch2_ops,
2767
+
},
2768
+
},
2769
+
};
2770
+
2771
+
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2772
+
.halt_reg = 0x32008,
2773
+
.halt_check = BRANCH_HALT_VOTED,
2774
+
.hwcg_reg = 0x32008,
2775
+
.hwcg_bit = 1,
2776
+
.clkr = {
2777
+
.enable_reg = 0x32008,
2778
+
.enable_mask = BIT(0),
2779
+
.hw.init = &(const struct clk_init_data){
2780
+
.name = "gcc_qmip_camera_nrt_ahb_clk",
2781
+
.ops = &clk_branch2_ops,
2782
+
},
2783
+
},
2784
+
};
2785
+
2786
+
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2787
+
.halt_reg = 0x3200c,
2788
+
.halt_check = BRANCH_HALT_VOTED,
2789
+
.hwcg_reg = 0x3200c,
2790
+
.hwcg_bit = 1,
2791
+
.clkr = {
2792
+
.enable_reg = 0x3200c,
2793
+
.enable_mask = BIT(0),
2794
+
.hw.init = &(const struct clk_init_data){
2795
+
.name = "gcc_qmip_camera_rt_ahb_clk",
2796
+
.ops = &clk_branch2_ops,
2797
+
},
2798
+
},
2799
+
};
2800
+
2801
+
static struct clk_branch gcc_qmip_disp1_ahb_clk = {
2802
+
.halt_reg = 0xc7008,
2803
+
.halt_check = BRANCH_HALT_VOTED,
2804
+
.hwcg_reg = 0xc7008,
2805
+
.hwcg_bit = 1,
2806
+
.clkr = {
2807
+
.enable_reg = 0xc7008,
2808
+
.enable_mask = BIT(0),
2809
+
.hw.init = &(const struct clk_init_data){
2810
+
.name = "gcc_qmip_disp1_ahb_clk",
2811
+
.ops = &clk_branch2_ops,
2812
+
},
2813
+
},
2814
+
};
2815
+
2816
+
static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = {
2817
+
.halt_reg = 0xc700c,
2818
+
.halt_check = BRANCH_HALT_VOTED,
2819
+
.clkr = {
2820
+
.enable_reg = 0xc700c,
2821
+
.enable_mask = BIT(0),
2822
+
.hw.init = &(const struct clk_init_data){
2823
+
.name = "gcc_qmip_disp1_rot_ahb_clk",
2824
+
.ops = &clk_branch2_ops,
2825
+
},
2826
+
},
2827
+
};
2828
+
2829
+
static struct clk_branch gcc_qmip_disp_ahb_clk = {
2830
+
.halt_reg = 0x33008,
2831
+
.halt_check = BRANCH_HALT_VOTED,
2832
+
.hwcg_reg = 0x33008,
2833
+
.hwcg_bit = 1,
2834
+
.clkr = {
2835
+
.enable_reg = 0x33008,
2836
+
.enable_mask = BIT(0),
2837
+
.hw.init = &(const struct clk_init_data){
2838
+
.name = "gcc_qmip_disp_ahb_clk",
2839
+
.ops = &clk_branch2_ops,
2840
+
},
2841
+
},
2842
+
};
2843
+
2844
+
static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {
2845
+
.halt_reg = 0x3300c,
2846
+
.halt_check = BRANCH_HALT_VOTED,
2847
+
.clkr = {
2848
+
.enable_reg = 0x3300c,
2849
+
.enable_mask = BIT(0),
2850
+
.hw.init = &(const struct clk_init_data){
2851
+
.name = "gcc_qmip_disp_rot_ahb_clk",
2852
+
.ops = &clk_branch2_ops,
2853
+
},
2854
+
},
2855
+
};
2856
+
2857
+
static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2858
+
.halt_reg = 0x34008,
2859
+
.halt_check = BRANCH_HALT_VOTED,
2860
+
.hwcg_reg = 0x34008,
2861
+
.hwcg_bit = 1,
2862
+
.clkr = {
2863
+
.enable_reg = 0x34008,
2864
+
.enable_mask = BIT(0),
2865
+
.hw.init = &(const struct clk_init_data){
2866
+
.name = "gcc_qmip_video_cvp_ahb_clk",
2867
+
.ops = &clk_branch2_ops,
2868
+
},
2869
+
},
2870
+
};
2871
+
2872
+
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2873
+
.halt_reg = 0x3400c,
2874
+
.halt_check = BRANCH_HALT_VOTED,
2875
+
.hwcg_reg = 0x3400c,
2876
+
.hwcg_bit = 1,
2877
+
.clkr = {
2878
+
.enable_reg = 0x3400c,
2879
+
.enable_mask = BIT(0),
2880
+
.hw.init = &(const struct clk_init_data){
2881
+
.name = "gcc_qmip_video_vcodec_ahb_clk",
2882
+
.ops = &clk_branch2_ops,
2883
+
},
2884
+
},
2885
+
};
2886
+
2887
+
static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = {
2888
+
.halt_reg = 0x34010,
2889
+
.halt_check = BRANCH_HALT_VOTED,
2890
+
.hwcg_reg = 0x34010,
2891
+
.hwcg_bit = 1,
2892
+
.clkr = {
2893
+
.enable_reg = 0x34010,
2894
+
.enable_mask = BIT(0),
2895
+
.hw.init = &(const struct clk_init_data){
2896
+
.name = "gcc_qmip_video_vcpu_ahb_clk",
2897
+
.ops = &clk_branch2_ops,
2898
+
},
2899
+
},
2900
+
};
2901
+
2902
+
static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2903
+
.halt_reg = 0x23018,
2904
+
.halt_check = BRANCH_HALT_VOTED,
2905
+
.clkr = {
2906
+
.enable_reg = 0x4b008,
2907
+
.enable_mask = BIT(9),
2908
+
.hw.init = &(const struct clk_init_data){
2909
+
.name = "gcc_qupv3_wrap0_core_2x_clk",
2910
+
.ops = &clk_branch2_ops,
2911
+
},
2912
+
},
2913
+
};
2914
+
2915
+
static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2916
+
.halt_reg = 0x2300c,
2917
+
.halt_check = BRANCH_HALT_VOTED,
2918
+
.clkr = {
2919
+
.enable_reg = 0x4b008,
2920
+
.enable_mask = BIT(8),
2921
+
.hw.init = &(const struct clk_init_data){
2922
+
.name = "gcc_qupv3_wrap0_core_clk",
2923
+
.ops = &clk_branch2_ops,
2924
+
},
2925
+
},
2926
+
};
2927
+
2928
+
static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2929
+
.halt_reg = 0x2314c,
2930
+
.halt_check = BRANCH_HALT_VOTED,
2931
+
.clkr = {
2932
+
.enable_reg = 0x4b008,
2933
+
.enable_mask = BIT(10),
2934
+
.hw.init = &(const struct clk_init_data){
2935
+
.name = "gcc_qupv3_wrap0_s0_clk",
2936
+
.parent_hws = (const struct clk_hw*[]){
2937
+
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2938
+
},
2939
+
.num_parents = 1,
2940
+
.flags = CLK_SET_RATE_PARENT,
2941
+
.ops = &clk_branch2_ops,
2942
+
},
2943
+
},
2944
+
};
2945
+
2946
+
static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2947
+
.halt_reg = 0x23280,
2948
+
.halt_check = BRANCH_HALT_VOTED,
2949
+
.clkr = {
2950
+
.enable_reg = 0x4b008,
2951
+
.enable_mask = BIT(11),
2952
+
.hw.init = &(const struct clk_init_data){
2953
+
.name = "gcc_qupv3_wrap0_s1_clk",
2954
+
.parent_hws = (const struct clk_hw*[]){
2955
+
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2956
+
},
2957
+
.num_parents = 1,
2958
+
.flags = CLK_SET_RATE_PARENT,
2959
+
.ops = &clk_branch2_ops,
2960
+
},
2961
+
},
2962
+
};
2963
+
2964
+
static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2965
+
.halt_reg = 0x233b4,
2966
+
.halt_check = BRANCH_HALT_VOTED,
2967
+
.clkr = {
2968
+
.enable_reg = 0x4b008,
2969
+
.enable_mask = BIT(12),
2970
+
.hw.init = &(const struct clk_init_data){
2971
+
.name = "gcc_qupv3_wrap0_s2_clk",
2972
+
.parent_hws = (const struct clk_hw*[]){
2973
+
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2974
+
},
2975
+
.num_parents = 1,
2976
+
.flags = CLK_SET_RATE_PARENT,
2977
+
.ops = &clk_branch2_ops,
2978
+
},
2979
+
},
2980
+
};
2981
+
2982
+
static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2983
+
.halt_reg = 0x234e8,
2984
+
.halt_check = BRANCH_HALT_VOTED,
2985
+
.clkr = {
2986
+
.enable_reg = 0x4b008,
2987
+
.enable_mask = BIT(13),
2988
+
.hw.init = &(const struct clk_init_data){
2989
+
.name = "gcc_qupv3_wrap0_s3_clk",
2990
+
.parent_hws = (const struct clk_hw*[]){
2991
+
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2992
+
},
2993
+
.num_parents = 1,
2994
+
.flags = CLK_SET_RATE_PARENT,
2995
+
.ops = &clk_branch2_ops,
2996
+
},
2997
+
},
2998
+
};
2999
+
3000
+
static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
3001
+
.halt_reg = 0x2361c,
3002
+
.halt_check = BRANCH_HALT_VOTED,
3003
+
.clkr = {
3004
+
.enable_reg = 0x4b008,
3005
+
.enable_mask = BIT(14),
3006
+
.hw.init = &(const struct clk_init_data){
3007
+
.name = "gcc_qupv3_wrap0_s4_clk",
3008
+
.parent_hws = (const struct clk_hw*[]){
3009
+
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
3010
+
},
3011
+
.num_parents = 1,
3012
+
.flags = CLK_SET_RATE_PARENT,
3013
+
.ops = &clk_branch2_ops,
3014
+
},
3015
+
},
3016
+
};
3017
+
3018
+
static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
3019
+
.halt_reg = 0x23750,
3020
+
.halt_check = BRANCH_HALT_VOTED,
3021
+
.clkr = {
3022
+
.enable_reg = 0x4b008,
3023
+
.enable_mask = BIT(15),
3024
+
.hw.init = &(const struct clk_init_data){
3025
+
.name = "gcc_qupv3_wrap0_s5_clk",
3026
+
.parent_hws = (const struct clk_hw*[]){
3027
+
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
3028
+
},
3029
+
.num_parents = 1,
3030
+
.flags = CLK_SET_RATE_PARENT,
3031
+
.ops = &clk_branch2_ops,
3032
+
},
3033
+
},
3034
+
};
3035
+
3036
+
static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
3037
+
.halt_reg = 0x23884,
3038
+
.halt_check = BRANCH_HALT_VOTED,
3039
+
.clkr = {
3040
+
.enable_reg = 0x4b008,
3041
+
.enable_mask = BIT(16),
3042
+
.hw.init = &(const struct clk_init_data){
3043
+
.name = "gcc_qupv3_wrap0_s6_clk",
3044
+
.parent_hws = (const struct clk_hw*[]){
3045
+
&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
3046
+
},
3047
+
.num_parents = 1,
3048
+
.flags = CLK_SET_RATE_PARENT,
3049
+
.ops = &clk_branch2_ops,
3050
+
},
3051
+
},
3052
+
};
3053
+
3054
+
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
3055
+
.halt_reg = 0x24018,
3056
+
.halt_check = BRANCH_HALT_VOTED,
3057
+
.clkr = {
3058
+
.enable_reg = 0x4b008,
3059
+
.enable_mask = BIT(18),
3060
+
.hw.init = &(const struct clk_init_data){
3061
+
.name = "gcc_qupv3_wrap1_core_2x_clk",
3062
+
.ops = &clk_branch2_ops,
3063
+
},
3064
+
},
3065
+
};
3066
+
3067
+
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
3068
+
.halt_reg = 0x2400c,
3069
+
.halt_check = BRANCH_HALT_VOTED,
3070
+
.clkr = {
3071
+
.enable_reg = 0x4b008,
3072
+
.enable_mask = BIT(19),
3073
+
.hw.init = &(const struct clk_init_data){
3074
+
.name = "gcc_qupv3_wrap1_core_clk",
3075
+
.ops = &clk_branch2_ops,
3076
+
},
3077
+
},
3078
+
};
3079
+
3080
+
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
3081
+
.halt_reg = 0x2414c,
3082
+
.halt_check = BRANCH_HALT_VOTED,
3083
+
.clkr = {
3084
+
.enable_reg = 0x4b008,
3085
+
.enable_mask = BIT(22),
3086
+
.hw.init = &(const struct clk_init_data){
3087
+
.name = "gcc_qupv3_wrap1_s0_clk",
3088
+
.parent_hws = (const struct clk_hw*[]){
3089
+
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
3090
+
},
3091
+
.num_parents = 1,
3092
+
.flags = CLK_SET_RATE_PARENT,
3093
+
.ops = &clk_branch2_ops,
3094
+
},
3095
+
},
3096
+
};
3097
+
3098
+
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
3099
+
.halt_reg = 0x24280,
3100
+
.halt_check = BRANCH_HALT_VOTED,
3101
+
.clkr = {
3102
+
.enable_reg = 0x4b008,
3103
+
.enable_mask = BIT(23),
3104
+
.hw.init = &(const struct clk_init_data){
3105
+
.name = "gcc_qupv3_wrap1_s1_clk",
3106
+
.parent_hws = (const struct clk_hw*[]){
3107
+
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
3108
+
},
3109
+
.num_parents = 1,
3110
+
.flags = CLK_SET_RATE_PARENT,
3111
+
.ops = &clk_branch2_ops,
3112
+
},
3113
+
},
3114
+
};
3115
+
3116
+
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
3117
+
.halt_reg = 0x243b4,
3118
+
.halt_check = BRANCH_HALT_VOTED,
3119
+
.clkr = {
3120
+
.enable_reg = 0x4b008,
3121
+
.enable_mask = BIT(24),
3122
+
.hw.init = &(const struct clk_init_data){
3123
+
.name = "gcc_qupv3_wrap1_s2_clk",
3124
+
.parent_hws = (const struct clk_hw*[]){
3125
+
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
3126
+
},
3127
+
.num_parents = 1,
3128
+
.flags = CLK_SET_RATE_PARENT,
3129
+
.ops = &clk_branch2_ops,
3130
+
},
3131
+
},
3132
+
};
3133
+
3134
+
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
3135
+
.halt_reg = 0x244e8,
3136
+
.halt_check = BRANCH_HALT_VOTED,
3137
+
.clkr = {
3138
+
.enable_reg = 0x4b008,
3139
+
.enable_mask = BIT(25),
3140
+
.hw.init = &(const struct clk_init_data){
3141
+
.name = "gcc_qupv3_wrap1_s3_clk",
3142
+
.parent_hws = (const struct clk_hw*[]){
3143
+
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
3144
+
},
3145
+
.num_parents = 1,
3146
+
.flags = CLK_SET_RATE_PARENT,
3147
+
.ops = &clk_branch2_ops,
3148
+
},
3149
+
},
3150
+
};
3151
+
3152
+
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
3153
+
.halt_reg = 0x2461c,
3154
+
.halt_check = BRANCH_HALT_VOTED,
3155
+
.clkr = {
3156
+
.enable_reg = 0x4b008,
3157
+
.enable_mask = BIT(26),
3158
+
.hw.init = &(const struct clk_init_data){
3159
+
.name = "gcc_qupv3_wrap1_s4_clk",
3160
+
.parent_hws = (const struct clk_hw*[]){
3161
+
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
3162
+
},
3163
+
.num_parents = 1,
3164
+
.flags = CLK_SET_RATE_PARENT,
3165
+
.ops = &clk_branch2_ops,
3166
+
},
3167
+
},
3168
+
};
3169
+
3170
+
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
3171
+
.halt_reg = 0x24750,
3172
+
.halt_check = BRANCH_HALT_VOTED,
3173
+
.clkr = {
3174
+
.enable_reg = 0x4b008,
3175
+
.enable_mask = BIT(27),
3176
+
.hw.init = &(const struct clk_init_data){
3177
+
.name = "gcc_qupv3_wrap1_s5_clk",
3178
+
.parent_hws = (const struct clk_hw*[]){
3179
+
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
3180
+
},
3181
+
.num_parents = 1,
3182
+
.flags = CLK_SET_RATE_PARENT,
3183
+
.ops = &clk_branch2_ops,
3184
+
},
3185
+
},
3186
+
};
3187
+
3188
+
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
3189
+
.halt_reg = 0x24884,
3190
+
.halt_check = BRANCH_HALT_VOTED,
3191
+
.clkr = {
3192
+
.enable_reg = 0x4b018,
3193
+
.enable_mask = BIT(27),
3194
+
.hw.init = &(const struct clk_init_data){
3195
+
.name = "gcc_qupv3_wrap1_s6_clk",
3196
+
.parent_hws = (const struct clk_hw*[]){
3197
+
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
3198
+
},
3199
+
.num_parents = 1,
3200
+
.flags = CLK_SET_RATE_PARENT,
3201
+
.ops = &clk_branch2_ops,
3202
+
},
3203
+
},
3204
+
};
3205
+
3206
+
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
3207
+
.halt_reg = 0x2a018,
3208
+
.halt_check = BRANCH_HALT_VOTED,
3209
+
.clkr = {
3210
+
.enable_reg = 0x4b010,
3211
+
.enable_mask = BIT(3),
3212
+
.hw.init = &(const struct clk_init_data){
3213
+
.name = "gcc_qupv3_wrap2_core_2x_clk",
3214
+
.ops = &clk_branch2_ops,
3215
+
},
3216
+
},
3217
+
};
3218
+
3219
+
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
3220
+
.halt_reg = 0x2a00c,
3221
+
.halt_check = BRANCH_HALT_VOTED,
3222
+
.clkr = {
3223
+
.enable_reg = 0x4b010,
3224
+
.enable_mask = BIT(0),
3225
+
.hw.init = &(const struct clk_init_data){
3226
+
.name = "gcc_qupv3_wrap2_core_clk",
3227
+
.ops = &clk_branch2_ops,
3228
+
},
3229
+
},
3230
+
};
3231
+
3232
+
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
3233
+
.halt_reg = 0x2a14c,
3234
+
.halt_check = BRANCH_HALT_VOTED,
3235
+
.clkr = {
3236
+
.enable_reg = 0x4b010,
3237
+
.enable_mask = BIT(4),
3238
+
.hw.init = &(const struct clk_init_data){
3239
+
.name = "gcc_qupv3_wrap2_s0_clk",
3240
+
.parent_hws = (const struct clk_hw*[]){
3241
+
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
3242
+
},
3243
+
.num_parents = 1,
3244
+
.flags = CLK_SET_RATE_PARENT,
3245
+
.ops = &clk_branch2_ops,
3246
+
},
3247
+
},
3248
+
};
3249
+
3250
+
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
3251
+
.halt_reg = 0x2a280,
3252
+
.halt_check = BRANCH_HALT_VOTED,
3253
+
.clkr = {
3254
+
.enable_reg = 0x4b010,
3255
+
.enable_mask = BIT(5),
3256
+
.hw.init = &(const struct clk_init_data){
3257
+
.name = "gcc_qupv3_wrap2_s1_clk",
3258
+
.parent_hws = (const struct clk_hw*[]){
3259
+
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
3260
+
},
3261
+
.num_parents = 1,
3262
+
.flags = CLK_SET_RATE_PARENT,
3263
+
.ops = &clk_branch2_ops,
3264
+
},
3265
+
},
3266
+
};
3267
+
3268
+
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
3269
+
.halt_reg = 0x2a3b4,
3270
+
.halt_check = BRANCH_HALT_VOTED,
3271
+
.clkr = {
3272
+
.enable_reg = 0x4b010,
3273
+
.enable_mask = BIT(6),
3274
+
.hw.init = &(const struct clk_init_data){
3275
+
.name = "gcc_qupv3_wrap2_s2_clk",
3276
+
.parent_hws = (const struct clk_hw*[]){
3277
+
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
3278
+
},
3279
+
.num_parents = 1,
3280
+
.flags = CLK_SET_RATE_PARENT,
3281
+
.ops = &clk_branch2_ops,
3282
+
},
3283
+
},
3284
+
};
3285
+
3286
+
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
3287
+
.halt_reg = 0x2a4e8,
3288
+
.halt_check = BRANCH_HALT_VOTED,
3289
+
.clkr = {
3290
+
.enable_reg = 0x4b010,
3291
+
.enable_mask = BIT(7),
3292
+
.hw.init = &(const struct clk_init_data){
3293
+
.name = "gcc_qupv3_wrap2_s3_clk",
3294
+
.parent_hws = (const struct clk_hw*[]){
3295
+
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
3296
+
},
3297
+
.num_parents = 1,
3298
+
.flags = CLK_SET_RATE_PARENT,
3299
+
.ops = &clk_branch2_ops,
3300
+
},
3301
+
},
3302
+
};
3303
+
3304
+
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
3305
+
.halt_reg = 0x2a61c,
3306
+
.halt_check = BRANCH_HALT_VOTED,
3307
+
.clkr = {
3308
+
.enable_reg = 0x4b010,
3309
+
.enable_mask = BIT(8),
3310
+
.hw.init = &(const struct clk_init_data){
3311
+
.name = "gcc_qupv3_wrap2_s4_clk",
3312
+
.parent_hws = (const struct clk_hw*[]){
3313
+
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
3314
+
},
3315
+
.num_parents = 1,
3316
+
.flags = CLK_SET_RATE_PARENT,
3317
+
.ops = &clk_branch2_ops,
3318
+
},
3319
+
},
3320
+
};
3321
+
3322
+
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
3323
+
.halt_reg = 0x2a750,
3324
+
.halt_check = BRANCH_HALT_VOTED,
3325
+
.clkr = {
3326
+
.enable_reg = 0x4b010,
3327
+
.enable_mask = BIT(9),
3328
+
.hw.init = &(const struct clk_init_data){
3329
+
.name = "gcc_qupv3_wrap2_s5_clk",
3330
+
.parent_hws = (const struct clk_hw*[]){
3331
+
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
3332
+
},
3333
+
.num_parents = 1,
3334
+
.flags = CLK_SET_RATE_PARENT,
3335
+
.ops = &clk_branch2_ops,
3336
+
},
3337
+
},
3338
+
};
3339
+
3340
+
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
3341
+
.halt_reg = 0x2a884,
3342
+
.halt_check = BRANCH_HALT_VOTED,
3343
+
.clkr = {
3344
+
.enable_reg = 0x4b018,
3345
+
.enable_mask = BIT(29),
3346
+
.hw.init = &(const struct clk_init_data){
3347
+
.name = "gcc_qupv3_wrap2_s6_clk",
3348
+
.parent_hws = (const struct clk_hw*[]){
3349
+
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
3350
+
},
3351
+
.num_parents = 1,
3352
+
.flags = CLK_SET_RATE_PARENT,
3353
+
.ops = &clk_branch2_ops,
3354
+
},
3355
+
},
3356
+
};
3357
+
3358
+
static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
3359
+
.halt_reg = 0xc4018,
3360
+
.halt_check = BRANCH_HALT_VOTED,
3361
+
.clkr = {
3362
+
.enable_reg = 0x4b000,
3363
+
.enable_mask = BIT(24),
3364
+
.hw.init = &(const struct clk_init_data){
3365
+
.name = "gcc_qupv3_wrap3_core_2x_clk",
3366
+
.ops = &clk_branch2_ops,
3367
+
},
3368
+
},
3369
+
};
3370
+
3371
+
static struct clk_branch gcc_qupv3_wrap3_core_clk = {
3372
+
.halt_reg = 0xc400c,
3373
+
.halt_check = BRANCH_HALT_VOTED,
3374
+
.clkr = {
3375
+
.enable_reg = 0x4b000,
3376
+
.enable_mask = BIT(23),
3377
+
.hw.init = &(const struct clk_init_data){
3378
+
.name = "gcc_qupv3_wrap3_core_clk",
3379
+
.ops = &clk_branch2_ops,
3380
+
},
3381
+
},
3382
+
};
3383
+
3384
+
static struct clk_branch gcc_qupv3_wrap3_qspi_clk = {
3385
+
.halt_reg = 0xc4280,
3386
+
.halt_check = BRANCH_HALT_VOTED,
3387
+
.clkr = {
3388
+
.enable_reg = 0x4b000,
3389
+
.enable_mask = BIT(26),
3390
+
.hw.init = &(const struct clk_init_data){
3391
+
.name = "gcc_qupv3_wrap3_qspi_clk",
3392
+
.parent_hws = (const struct clk_hw*[]){
3393
+
&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
3394
+
},
3395
+
.num_parents = 1,
3396
+
.flags = CLK_SET_RATE_PARENT,
3397
+
.ops = &clk_branch2_ops,
3398
+
},
3399
+
},
3400
+
};
3401
+
3402
+
static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
3403
+
.halt_reg = 0xc414c,
3404
+
.halt_check = BRANCH_HALT_VOTED,
3405
+
.clkr = {
3406
+
.enable_reg = 0x4b000,
3407
+
.enable_mask = BIT(25),
3408
+
.hw.init = &(const struct clk_init_data){
3409
+
.name = "gcc_qupv3_wrap3_s0_clk",
3410
+
.parent_hws = (const struct clk_hw*[]){
3411
+
&gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw,
3412
+
},
3413
+
.num_parents = 1,
3414
+
.flags = CLK_SET_RATE_PARENT,
3415
+
.ops = &clk_branch2_ops,
3416
+
},
3417
+
},
3418
+
};
3419
+
3420
+
static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3421
+
.halt_reg = 0x23004,
3422
+
.halt_check = BRANCH_HALT_VOTED,
3423
+
.hwcg_reg = 0x23004,
3424
+
.hwcg_bit = 1,
3425
+
.clkr = {
3426
+
.enable_reg = 0x4b008,
3427
+
.enable_mask = BIT(6),
3428
+
.hw.init = &(const struct clk_init_data){
3429
+
.name = "gcc_qupv3_wrap_0_m_ahb_clk",
3430
+
.ops = &clk_branch2_ops,
3431
+
},
3432
+
},
3433
+
};
3434
+
3435
+
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3436
+
.halt_reg = 0x23008,
3437
+
.halt_check = BRANCH_HALT_VOTED,
3438
+
.hwcg_reg = 0x23008,
3439
+
.hwcg_bit = 1,
3440
+
.clkr = {
3441
+
.enable_reg = 0x4b008,
3442
+
.enable_mask = BIT(7),
3443
+
.hw.init = &(const struct clk_init_data){
3444
+
.name = "gcc_qupv3_wrap_0_s_ahb_clk",
3445
+
.ops = &clk_branch2_ops,
3446
+
},
3447
+
},
3448
+
};
3449
+
3450
+
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3451
+
.halt_reg = 0x24004,
3452
+
.halt_check = BRANCH_HALT_VOTED,
3453
+
.hwcg_reg = 0x24004,
3454
+
.hwcg_bit = 1,
3455
+
.clkr = {
3456
+
.enable_reg = 0x4b008,
3457
+
.enable_mask = BIT(20),
3458
+
.hw.init = &(const struct clk_init_data){
3459
+
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
3460
+
.ops = &clk_branch2_ops,
3461
+
},
3462
+
},
3463
+
};
3464
+
3465
+
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3466
+
.halt_reg = 0x24008,
3467
+
.halt_check = BRANCH_HALT_VOTED,
3468
+
.hwcg_reg = 0x24008,
3469
+
.hwcg_bit = 1,
3470
+
.clkr = {
3471
+
.enable_reg = 0x4b008,
3472
+
.enable_mask = BIT(21),
3473
+
.hw.init = &(const struct clk_init_data){
3474
+
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
3475
+
.ops = &clk_branch2_ops,
3476
+
},
3477
+
},
3478
+
};
3479
+
3480
+
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
3481
+
.halt_reg = 0x2a004,
3482
+
.halt_check = BRANCH_HALT_VOTED,
3483
+
.hwcg_reg = 0x2a004,
3484
+
.hwcg_bit = 1,
3485
+
.clkr = {
3486
+
.enable_reg = 0x4b010,
3487
+
.enable_mask = BIT(2),
3488
+
.hw.init = &(const struct clk_init_data){
3489
+
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
3490
+
.ops = &clk_branch2_ops,
3491
+
},
3492
+
},
3493
+
};
3494
+
3495
+
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
3496
+
.halt_reg = 0x2a008,
3497
+
.halt_check = BRANCH_HALT_VOTED,
3498
+
.hwcg_reg = 0x2a008,
3499
+
.hwcg_bit = 1,
3500
+
.clkr = {
3501
+
.enable_reg = 0x4b010,
3502
+
.enable_mask = BIT(1),
3503
+
.hw.init = &(const struct clk_init_data){
3504
+
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
3505
+
.ops = &clk_branch2_ops,
3506
+
},
3507
+
},
3508
+
};
3509
+
3510
+
static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = {
3511
+
.halt_reg = 0xc4004,
3512
+
.halt_check = BRANCH_HALT_VOTED,
3513
+
.hwcg_reg = 0xc4004,
3514
+
.hwcg_bit = 1,
3515
+
.clkr = {
3516
+
.enable_reg = 0x4b000,
3517
+
.enable_mask = BIT(27),
3518
+
.hw.init = &(const struct clk_init_data){
3519
+
.name = "gcc_qupv3_wrap_3_m_ahb_clk",
3520
+
.ops = &clk_branch2_ops,
3521
+
},
3522
+
},
3523
+
};
3524
+
3525
+
static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = {
3526
+
.halt_reg = 0xc4008,
3527
+
.halt_check = BRANCH_HALT_VOTED,
3528
+
.hwcg_reg = 0xc4008,
3529
+
.hwcg_bit = 1,
3530
+
.clkr = {
3531
+
.enable_reg = 0x4b000,
3532
+
.enable_mask = BIT(20),
3533
+
.hw.init = &(const struct clk_init_data){
3534
+
.name = "gcc_qupv3_wrap_3_s_ahb_clk",
3535
+
.ops = &clk_branch2_ops,
3536
+
},
3537
+
},
3538
+
};
3539
+
3540
+
static struct clk_branch gcc_sdcc1_ahb_clk = {
3541
+
.halt_reg = 0x2000c,
3542
+
.halt_check = BRANCH_HALT,
3543
+
.clkr = {
3544
+
.enable_reg = 0x2000c,
3545
+
.enable_mask = BIT(0),
3546
+
.hw.init = &(const struct clk_init_data){
3547
+
.name = "gcc_sdcc1_ahb_clk",
3548
+
.ops = &clk_branch2_ops,
3549
+
},
3550
+
},
3551
+
};
3552
+
3553
+
static struct clk_branch gcc_sdcc1_apps_clk = {
3554
+
.halt_reg = 0x20004,
3555
+
.halt_check = BRANCH_HALT,
3556
+
.clkr = {
3557
+
.enable_reg = 0x20004,
3558
+
.enable_mask = BIT(0),
3559
+
.hw.init = &(const struct clk_init_data){
3560
+
.name = "gcc_sdcc1_apps_clk",
3561
+
.parent_hws = (const struct clk_hw*[]){
3562
+
&gcc_sdcc1_apps_clk_src.clkr.hw,
3563
+
},
3564
+
.num_parents = 1,
3565
+
.flags = CLK_SET_RATE_PARENT,
3566
+
.ops = &clk_branch2_ops,
3567
+
},
3568
+
},
3569
+
};
3570
+
3571
+
static struct clk_branch gcc_sdcc1_ice_core_clk = {
3572
+
.halt_reg = 0x20044,
3573
+
.halt_check = BRANCH_HALT_VOTED,
3574
+
.hwcg_reg = 0x20044,
3575
+
.hwcg_bit = 1,
3576
+
.clkr = {
3577
+
.enable_reg = 0x20044,
3578
+
.enable_mask = BIT(0),
3579
+
.hw.init = &(const struct clk_init_data){
3580
+
.name = "gcc_sdcc1_ice_core_clk",
3581
+
.parent_hws = (const struct clk_hw*[]){
3582
+
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
3583
+
},
3584
+
.num_parents = 1,
3585
+
.flags = CLK_SET_RATE_PARENT,
3586
+
.ops = &clk_branch2_ops,
3587
+
},
3588
+
},
3589
+
};
3590
+
3591
+
static struct clk_branch gcc_sgmi_clkref_en = {
3592
+
.halt_reg = 0x9c034,
3593
+
.halt_check = BRANCH_HALT_DELAY,
3594
+
.clkr = {
3595
+
.enable_reg = 0x9c034,
3596
+
.enable_mask = BIT(0),
3597
+
.hw.init = &(const struct clk_init_data){
3598
+
.name = "gcc_sgmi_clkref_en",
3599
+
.ops = &clk_branch2_ops,
3600
+
},
3601
+
},
3602
+
};
3603
+
3604
+
static struct clk_branch gcc_tscss_ahb_clk = {
3605
+
.halt_reg = 0x21024,
3606
+
.halt_check = BRANCH_HALT,
3607
+
.clkr = {
3608
+
.enable_reg = 0x21024,
3609
+
.enable_mask = BIT(0),
3610
+
.hw.init = &(const struct clk_init_data){
3611
+
.name = "gcc_tscss_ahb_clk",
3612
+
.ops = &clk_branch2_ops,
3613
+
},
3614
+
},
3615
+
};
3616
+
3617
+
static struct clk_branch gcc_tscss_etu_clk = {
3618
+
.halt_reg = 0x21020,
3619
+
.halt_check = BRANCH_HALT,
3620
+
.clkr = {
3621
+
.enable_reg = 0x21020,
3622
+
.enable_mask = BIT(0),
3623
+
.hw.init = &(const struct clk_init_data){
3624
+
.name = "gcc_tscss_etu_clk",
3625
+
.ops = &clk_branch2_ops,
3626
+
},
3627
+
},
3628
+
};
3629
+
3630
+
static struct clk_branch gcc_tscss_global_cntr_clk = {
3631
+
.halt_reg = 0x21004,
3632
+
.halt_check = BRANCH_HALT_VOTED,
3633
+
.clkr = {
3634
+
.enable_reg = 0x21004,
3635
+
.enable_mask = BIT(0),
3636
+
.hw.init = &(const struct clk_init_data){
3637
+
.name = "gcc_tscss_global_cntr_clk",
3638
+
.parent_hws = (const struct clk_hw*[]){
3639
+
&gcc_tscss_cntr_clk_src.clkr.hw,
3640
+
},
3641
+
.num_parents = 1,
3642
+
.flags = CLK_SET_RATE_PARENT,
3643
+
.ops = &clk_branch2_ops,
3644
+
},
3645
+
},
3646
+
};
3647
+
3648
+
static struct clk_branch gcc_ufs_card_ahb_clk = {
3649
+
.halt_reg = 0x81020,
3650
+
.halt_check = BRANCH_HALT_VOTED,
3651
+
.hwcg_reg = 0x81020,
3652
+
.hwcg_bit = 1,
3653
+
.clkr = {
3654
+
.enable_reg = 0x81020,
3655
+
.enable_mask = BIT(0),
3656
+
.hw.init = &(const struct clk_init_data){
3657
+
.name = "gcc_ufs_card_ahb_clk",
3658
+
.ops = &clk_branch2_ops,
3659
+
},
3660
+
},
3661
+
};
3662
+
3663
+
static struct clk_branch gcc_ufs_card_axi_clk = {
3664
+
.halt_reg = 0x81018,
3665
+
.halt_check = BRANCH_HALT_VOTED,
3666
+
.hwcg_reg = 0x81018,
3667
+
.hwcg_bit = 1,
3668
+
.clkr = {
3669
+
.enable_reg = 0x81018,
3670
+
.enable_mask = BIT(0),
3671
+
.hw.init = &(const struct clk_init_data){
3672
+
.name = "gcc_ufs_card_axi_clk",
3673
+
.parent_hws = (const struct clk_hw*[]){
3674
+
&gcc_ufs_card_axi_clk_src.clkr.hw,
3675
+
},
3676
+
.num_parents = 1,
3677
+
.flags = CLK_SET_RATE_PARENT,
3678
+
.ops = &clk_branch2_ops,
3679
+
},
3680
+
},
3681
+
};
3682
+
3683
+
static struct clk_branch gcc_ufs_card_ice_core_clk = {
3684
+
.halt_reg = 0x8106c,
3685
+
.halt_check = BRANCH_HALT_VOTED,
3686
+
.hwcg_reg = 0x8106c,
3687
+
.hwcg_bit = 1,
3688
+
.clkr = {
3689
+
.enable_reg = 0x8106c,
3690
+
.enable_mask = BIT(0),
3691
+
.hw.init = &(const struct clk_init_data){
3692
+
.name = "gcc_ufs_card_ice_core_clk",
3693
+
.parent_hws = (const struct clk_hw*[]){
3694
+
&gcc_ufs_card_ice_core_clk_src.clkr.hw,
3695
+
},
3696
+
.num_parents = 1,
3697
+
.flags = CLK_SET_RATE_PARENT,
3698
+
.ops = &clk_branch2_ops,
3699
+
},
3700
+
},
3701
+
};
3702
+
3703
+
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
3704
+
.halt_reg = 0x810a4,
3705
+
.halt_check = BRANCH_HALT_VOTED,
3706
+
.hwcg_reg = 0x810a4,
3707
+
.hwcg_bit = 1,
3708
+
.clkr = {
3709
+
.enable_reg = 0x810a4,
3710
+
.enable_mask = BIT(0),
3711
+
.hw.init = &(const struct clk_init_data){
3712
+
.name = "gcc_ufs_card_phy_aux_clk",
3713
+
.parent_hws = (const struct clk_hw*[]){
3714
+
&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
3715
+
},
3716
+
.num_parents = 1,
3717
+
.flags = CLK_SET_RATE_PARENT,
3718
+
.ops = &clk_branch2_ops,
3719
+
},
3720
+
},
3721
+
};
3722
+
3723
+
static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
3724
+
.halt_reg = 0x81028,
3725
+
.halt_check = BRANCH_HALT_DELAY,
3726
+
.clkr = {
3727
+
.enable_reg = 0x81028,
3728
+
.enable_mask = BIT(0),
3729
+
.hw.init = &(const struct clk_init_data){
3730
+
.name = "gcc_ufs_card_rx_symbol_0_clk",
3731
+
.parent_hws = (const struct clk_hw*[]){
3732
+
&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
3733
+
},
3734
+
.num_parents = 1,
3735
+
.flags = CLK_SET_RATE_PARENT,
3736
+
.ops = &clk_branch2_ops,
3737
+
},
3738
+
},
3739
+
};
3740
+
3741
+
static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
3742
+
.halt_reg = 0x810c0,
3743
+
.halt_check = BRANCH_HALT_DELAY,
3744
+
.clkr = {
3745
+
.enable_reg = 0x810c0,
3746
+
.enable_mask = BIT(0),
3747
+
.hw.init = &(const struct clk_init_data){
3748
+
.name = "gcc_ufs_card_rx_symbol_1_clk",
3749
+
.parent_hws = (const struct clk_hw*[]){
3750
+
&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
3751
+
},
3752
+
.num_parents = 1,
3753
+
.flags = CLK_SET_RATE_PARENT,
3754
+
.ops = &clk_branch2_ops,
3755
+
},
3756
+
},
3757
+
};
3758
+
3759
+
static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
3760
+
.halt_reg = 0x81024,
3761
+
.halt_check = BRANCH_HALT_DELAY,
3762
+
.clkr = {
3763
+
.enable_reg = 0x81024,
3764
+
.enable_mask = BIT(0),
3765
+
.hw.init = &(const struct clk_init_data){
3766
+
.name = "gcc_ufs_card_tx_symbol_0_clk",
3767
+
.parent_hws = (const struct clk_hw*[]){
3768
+
&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
3769
+
},
3770
+
.num_parents = 1,
3771
+
.flags = CLK_SET_RATE_PARENT,
3772
+
.ops = &clk_branch2_ops,
3773
+
},
3774
+
},
3775
+
};
3776
+
3777
+
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
3778
+
.halt_reg = 0x81064,
3779
+
.halt_check = BRANCH_HALT_VOTED,
3780
+
.hwcg_reg = 0x81064,
3781
+
.hwcg_bit = 1,
3782
+
.clkr = {
3783
+
.enable_reg = 0x81064,
3784
+
.enable_mask = BIT(0),
3785
+
.hw.init = &(const struct clk_init_data){
3786
+
.name = "gcc_ufs_card_unipro_core_clk",
3787
+
.parent_hws = (const struct clk_hw*[]){
3788
+
&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
3789
+
},
3790
+
.num_parents = 1,
3791
+
.flags = CLK_SET_RATE_PARENT,
3792
+
.ops = &clk_branch2_ops,
3793
+
},
3794
+
},
3795
+
};
3796
+
3797
+
static struct clk_branch gcc_ufs_phy_ahb_clk = {
3798
+
.halt_reg = 0x83020,
3799
+
.halt_check = BRANCH_HALT_VOTED,
3800
+
.hwcg_reg = 0x83020,
3801
+
.hwcg_bit = 1,
3802
+
.clkr = {
3803
+
.enable_reg = 0x83020,
3804
+
.enable_mask = BIT(0),
3805
+
.hw.init = &(const struct clk_init_data){
3806
+
.name = "gcc_ufs_phy_ahb_clk",
3807
+
.ops = &clk_branch2_ops,
3808
+
},
3809
+
},
3810
+
};
3811
+
3812
+
static struct clk_branch gcc_ufs_phy_axi_clk = {
3813
+
.halt_reg = 0x83018,
3814
+
.halt_check = BRANCH_HALT_VOTED,
3815
+
.hwcg_reg = 0x83018,
3816
+
.hwcg_bit = 1,
3817
+
.clkr = {
3818
+
.enable_reg = 0x83018,
3819
+
.enable_mask = BIT(0),
3820
+
.hw.init = &(const struct clk_init_data){
3821
+
.name = "gcc_ufs_phy_axi_clk",
3822
+
.parent_hws = (const struct clk_hw*[]){
3823
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
3824
+
},
3825
+
.num_parents = 1,
3826
+
.flags = CLK_SET_RATE_PARENT,
3827
+
.ops = &clk_branch2_ops,
3828
+
},
3829
+
},
3830
+
};
3831
+
3832
+
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3833
+
.halt_reg = 0x83018,
3834
+
.halt_check = BRANCH_HALT_VOTED,
3835
+
.hwcg_reg = 0x83018,
3836
+
.hwcg_bit = 1,
3837
+
.clkr = {
3838
+
.enable_reg = 0x83018,
3839
+
.enable_mask = BIT(1),
3840
+
.hw.init = &(const struct clk_init_data){
3841
+
.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3842
+
.parent_hws = (const struct clk_hw*[]){
3843
+
&gcc_ufs_phy_axi_clk_src.clkr.hw,
3844
+
},
3845
+
.num_parents = 1,
3846
+
.flags = CLK_SET_RATE_PARENT,
3847
+
.ops = &clk_branch2_ops,
3848
+
},
3849
+
},
3850
+
};
3851
+
3852
+
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3853
+
.halt_reg = 0x8306c,
3854
+
.halt_check = BRANCH_HALT_VOTED,
3855
+
.hwcg_reg = 0x8306c,
3856
+
.hwcg_bit = 1,
3857
+
.clkr = {
3858
+
.enable_reg = 0x8306c,
3859
+
.enable_mask = BIT(0),
3860
+
.hw.init = &(const struct clk_init_data){
3861
+
.name = "gcc_ufs_phy_ice_core_clk",
3862
+
.parent_hws = (const struct clk_hw*[]){
3863
+
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3864
+
},
3865
+
.num_parents = 1,
3866
+
.flags = CLK_SET_RATE_PARENT,
3867
+
.ops = &clk_branch2_ops,
3868
+
},
3869
+
},
3870
+
};
3871
+
3872
+
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3873
+
.halt_reg = 0x8306c,
3874
+
.halt_check = BRANCH_HALT_VOTED,
3875
+
.hwcg_reg = 0x8306c,
3876
+
.hwcg_bit = 1,
3877
+
.clkr = {
3878
+
.enable_reg = 0x8306c,
3879
+
.enable_mask = BIT(1),
3880
+
.hw.init = &(const struct clk_init_data){
3881
+
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3882
+
.parent_hws = (const struct clk_hw*[]){
3883
+
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3884
+
},
3885
+
.num_parents = 1,
3886
+
.flags = CLK_SET_RATE_PARENT,
3887
+
.ops = &clk_branch2_ops,
3888
+
},
3889
+
},
3890
+
};
3891
+
3892
+
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3893
+
.halt_reg = 0x830a4,
3894
+
.halt_check = BRANCH_HALT_VOTED,
3895
+
.hwcg_reg = 0x830a4,
3896
+
.hwcg_bit = 1,
3897
+
.clkr = {
3898
+
.enable_reg = 0x830a4,
3899
+
.enable_mask = BIT(0),
3900
+
.hw.init = &(const struct clk_init_data){
3901
+
.name = "gcc_ufs_phy_phy_aux_clk",
3902
+
.parent_hws = (const struct clk_hw*[]){
3903
+
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3904
+
},
3905
+
.num_parents = 1,
3906
+
.flags = CLK_SET_RATE_PARENT,
3907
+
.ops = &clk_branch2_ops,
3908
+
},
3909
+
},
3910
+
};
3911
+
3912
+
static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3913
+
.halt_reg = 0x830a4,
3914
+
.halt_check = BRANCH_HALT_VOTED,
3915
+
.hwcg_reg = 0x830a4,
3916
+
.hwcg_bit = 1,
3917
+
.clkr = {
3918
+
.enable_reg = 0x830a4,
3919
+
.enable_mask = BIT(1),
3920
+
.hw.init = &(const struct clk_init_data){
3921
+
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3922
+
.parent_hws = (const struct clk_hw*[]){
3923
+
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3924
+
},
3925
+
.num_parents = 1,
3926
+
.flags = CLK_SET_RATE_PARENT,
3927
+
.ops = &clk_branch2_ops,
3928
+
},
3929
+
},
3930
+
};
3931
+
3932
+
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3933
+
.halt_reg = 0x83028,
3934
+
.halt_check = BRANCH_HALT_DELAY,
3935
+
.clkr = {
3936
+
.enable_reg = 0x83028,
3937
+
.enable_mask = BIT(0),
3938
+
.hw.init = &(const struct clk_init_data){
3939
+
.name = "gcc_ufs_phy_rx_symbol_0_clk",
3940
+
.parent_hws = (const struct clk_hw*[]){
3941
+
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3942
+
},
3943
+
.num_parents = 1,
3944
+
.flags = CLK_SET_RATE_PARENT,
3945
+
.ops = &clk_branch2_ops,
3946
+
},
3947
+
},
3948
+
};
3949
+
3950
+
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3951
+
.halt_reg = 0x830c0,
3952
+
.halt_check = BRANCH_HALT_DELAY,
3953
+
.clkr = {
3954
+
.enable_reg = 0x830c0,
3955
+
.enable_mask = BIT(0),
3956
+
.hw.init = &(const struct clk_init_data){
3957
+
.name = "gcc_ufs_phy_rx_symbol_1_clk",
3958
+
.parent_hws = (const struct clk_hw*[]){
3959
+
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3960
+
},
3961
+
.num_parents = 1,
3962
+
.flags = CLK_SET_RATE_PARENT,
3963
+
.ops = &clk_branch2_ops,
3964
+
},
3965
+
},
3966
+
};
3967
+
3968
+
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3969
+
.halt_reg = 0x83024,
3970
+
.halt_check = BRANCH_HALT_DELAY,
3971
+
.clkr = {
3972
+
.enable_reg = 0x83024,
3973
+
.enable_mask = BIT(0),
3974
+
.hw.init = &(const struct clk_init_data){
3975
+
.name = "gcc_ufs_phy_tx_symbol_0_clk",
3976
+
.parent_hws = (const struct clk_hw*[]){
3977
+
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3978
+
},
3979
+
.num_parents = 1,
3980
+
.flags = CLK_SET_RATE_PARENT,
3981
+
.ops = &clk_branch2_ops,
3982
+
},
3983
+
},
3984
+
};
3985
+
3986
+
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3987
+
.halt_reg = 0x83064,
3988
+
.halt_check = BRANCH_HALT_VOTED,
3989
+
.hwcg_reg = 0x83064,
3990
+
.hwcg_bit = 1,
3991
+
.clkr = {
3992
+
.enable_reg = 0x83064,
3993
+
.enable_mask = BIT(0),
3994
+
.hw.init = &(const struct clk_init_data){
3995
+
.name = "gcc_ufs_phy_unipro_core_clk",
3996
+
.parent_hws = (const struct clk_hw*[]){
3997
+
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3998
+
},
3999
+
.num_parents = 1,
4000
+
.flags = CLK_SET_RATE_PARENT,
4001
+
.ops = &clk_branch2_ops,
4002
+
},
4003
+
},
4004
+
};
4005
+
4006
+
static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
4007
+
.halt_reg = 0x83064,
4008
+
.halt_check = BRANCH_HALT_VOTED,
4009
+
.hwcg_reg = 0x83064,
4010
+
.hwcg_bit = 1,
4011
+
.clkr = {
4012
+
.enable_reg = 0x83064,
4013
+
.enable_mask = BIT(1),
4014
+
.hw.init = &(const struct clk_init_data){
4015
+
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
4016
+
.parent_hws = (const struct clk_hw*[]){
4017
+
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
4018
+
},
4019
+
.num_parents = 1,
4020
+
.flags = CLK_SET_RATE_PARENT,
4021
+
.ops = &clk_branch2_ops,
4022
+
},
4023
+
},
4024
+
};
4025
+
4026
+
static struct clk_branch gcc_usb20_master_clk = {
4027
+
.halt_reg = 0x1c018,
4028
+
.halt_check = BRANCH_HALT,
4029
+
.clkr = {
4030
+
.enable_reg = 0x1c018,
4031
+
.enable_mask = BIT(0),
4032
+
.hw.init = &(const struct clk_init_data){
4033
+
.name = "gcc_usb20_master_clk",
4034
+
.parent_hws = (const struct clk_hw*[]){
4035
+
&gcc_usb20_master_clk_src.clkr.hw,
4036
+
},
4037
+
.num_parents = 1,
4038
+
.flags = CLK_SET_RATE_PARENT,
4039
+
.ops = &clk_branch2_ops,
4040
+
},
4041
+
},
4042
+
};
4043
+
4044
+
static struct clk_branch gcc_usb20_mock_utmi_clk = {
4045
+
.halt_reg = 0x1c024,
4046
+
.halt_check = BRANCH_HALT,
4047
+
.clkr = {
4048
+
.enable_reg = 0x1c024,
4049
+
.enable_mask = BIT(0),
4050
+
.hw.init = &(const struct clk_init_data){
4051
+
.name = "gcc_usb20_mock_utmi_clk",
4052
+
.parent_hws = (const struct clk_hw*[]){
4053
+
&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
4054
+
},
4055
+
.num_parents = 1,
4056
+
.flags = CLK_SET_RATE_PARENT,
4057
+
.ops = &clk_branch2_ops,
4058
+
},
4059
+
},
4060
+
};
4061
+
4062
+
static struct clk_branch gcc_usb20_sleep_clk = {
4063
+
.halt_reg = 0x1c020,
4064
+
.halt_check = BRANCH_HALT,
4065
+
.clkr = {
4066
+
.enable_reg = 0x1c020,
4067
+
.enable_mask = BIT(0),
4068
+
.hw.init = &(const struct clk_init_data){
4069
+
.name = "gcc_usb20_sleep_clk",
4070
+
.ops = &clk_branch2_ops,
4071
+
},
4072
+
},
4073
+
};
4074
+
4075
+
static struct clk_branch gcc_usb30_prim_master_clk = {
4076
+
.halt_reg = 0x1b018,
4077
+
.halt_check = BRANCH_HALT,
4078
+
.clkr = {
4079
+
.enable_reg = 0x1b018,
4080
+
.enable_mask = BIT(0),
4081
+
.hw.init = &(const struct clk_init_data){
4082
+
.name = "gcc_usb30_prim_master_clk",
4083
+
.parent_hws = (const struct clk_hw*[]){
4084
+
&gcc_usb30_prim_master_clk_src.clkr.hw,
4085
+
},
4086
+
.num_parents = 1,
4087
+
.flags = CLK_SET_RATE_PARENT,
4088
+
.ops = &clk_branch2_ops,
4089
+
},
4090
+
},
4091
+
};
4092
+
4093
+
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
4094
+
.halt_reg = 0x1b024,
4095
+
.halt_check = BRANCH_HALT,
4096
+
.clkr = {
4097
+
.enable_reg = 0x1b024,
4098
+
.enable_mask = BIT(0),
4099
+
.hw.init = &(const struct clk_init_data){
4100
+
.name = "gcc_usb30_prim_mock_utmi_clk",
4101
+
.parent_hws = (const struct clk_hw*[]){
4102
+
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
4103
+
},
4104
+
.num_parents = 1,
4105
+
.flags = CLK_SET_RATE_PARENT,
4106
+
.ops = &clk_branch2_ops,
4107
+
},
4108
+
},
4109
+
};
4110
+
4111
+
static struct clk_branch gcc_usb30_prim_sleep_clk = {
4112
+
.halt_reg = 0x1b020,
4113
+
.halt_check = BRANCH_HALT,
4114
+
.clkr = {
4115
+
.enable_reg = 0x1b020,
4116
+
.enable_mask = BIT(0),
4117
+
.hw.init = &(const struct clk_init_data){
4118
+
.name = "gcc_usb30_prim_sleep_clk",
4119
+
.ops = &clk_branch2_ops,
4120
+
},
4121
+
},
4122
+
};
4123
+
4124
+
static struct clk_branch gcc_usb30_sec_master_clk = {
4125
+
.halt_reg = 0x2f018,
4126
+
.halt_check = BRANCH_HALT,
4127
+
.clkr = {
4128
+
.enable_reg = 0x2f018,
4129
+
.enable_mask = BIT(0),
4130
+
.hw.init = &(const struct clk_init_data){
4131
+
.name = "gcc_usb30_sec_master_clk",
4132
+
.parent_hws = (const struct clk_hw*[]){
4133
+
&gcc_usb30_sec_master_clk_src.clkr.hw,
4134
+
},
4135
+
.num_parents = 1,
4136
+
.flags = CLK_SET_RATE_PARENT,
4137
+
.ops = &clk_branch2_ops,
4138
+
},
4139
+
},
4140
+
};
4141
+
4142
+
static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
4143
+
.halt_reg = 0x2f024,
4144
+
.halt_check = BRANCH_HALT,
4145
+
.clkr = {
4146
+
.enable_reg = 0x2f024,
4147
+
.enable_mask = BIT(0),
4148
+
.hw.init = &(const struct clk_init_data){
4149
+
.name = "gcc_usb30_sec_mock_utmi_clk",
4150
+
.parent_hws = (const struct clk_hw*[]){
4151
+
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
4152
+
},
4153
+
.num_parents = 1,
4154
+
.flags = CLK_SET_RATE_PARENT,
4155
+
.ops = &clk_branch2_ops,
4156
+
},
4157
+
},
4158
+
};
4159
+
4160
+
static struct clk_branch gcc_usb30_sec_sleep_clk = {
4161
+
.halt_reg = 0x2f020,
4162
+
.halt_check = BRANCH_HALT,
4163
+
.clkr = {
4164
+
.enable_reg = 0x2f020,
4165
+
.enable_mask = BIT(0),
4166
+
.hw.init = &(const struct clk_init_data){
4167
+
.name = "gcc_usb30_sec_sleep_clk",
4168
+
.ops = &clk_branch2_ops,
4169
+
},
4170
+
},
4171
+
};
4172
+
4173
+
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
4174
+
.halt_reg = 0x1b05c,
4175
+
.halt_check = BRANCH_HALT,
4176
+
.clkr = {
4177
+
.enable_reg = 0x1b05c,
4178
+
.enable_mask = BIT(0),
4179
+
.hw.init = &(const struct clk_init_data){
4180
+
.name = "gcc_usb3_prim_phy_aux_clk",
4181
+
.parent_hws = (const struct clk_hw*[]){
4182
+
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
4183
+
},
4184
+
.num_parents = 1,
4185
+
.flags = CLK_SET_RATE_PARENT,
4186
+
.ops = &clk_branch2_ops,
4187
+
},
4188
+
},
4189
+
};
4190
+
4191
+
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
4192
+
.halt_reg = 0x1b060,
4193
+
.halt_check = BRANCH_HALT,
4194
+
.clkr = {
4195
+
.enable_reg = 0x1b060,
4196
+
.enable_mask = BIT(0),
4197
+
.hw.init = &(const struct clk_init_data){
4198
+
.name = "gcc_usb3_prim_phy_com_aux_clk",
4199
+
.parent_hws = (const struct clk_hw*[]){
4200
+
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
4201
+
},
4202
+
.num_parents = 1,
4203
+
.flags = CLK_SET_RATE_PARENT,
4204
+
.ops = &clk_branch2_ops,
4205
+
},
4206
+
},
4207
+
};
4208
+
4209
+
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
4210
+
.halt_reg = 0x1b064,
4211
+
.halt_check = BRANCH_HALT_DELAY,
4212
+
.hwcg_reg = 0x1b064,
4213
+
.hwcg_bit = 1,
4214
+
.clkr = {
4215
+
.enable_reg = 0x1b064,
4216
+
.enable_mask = BIT(0),
4217
+
.hw.init = &(const struct clk_init_data){
4218
+
.name = "gcc_usb3_prim_phy_pipe_clk",
4219
+
.parent_hws = (const struct clk_hw*[]){
4220
+
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
4221
+
},
4222
+
.num_parents = 1,
4223
+
.flags = CLK_SET_RATE_PARENT,
4224
+
.ops = &clk_branch2_ops,
4225
+
},
4226
+
},
4227
+
};
4228
+
4229
+
static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
4230
+
.halt_reg = 0x2f05c,
4231
+
.halt_check = BRANCH_HALT,
4232
+
.clkr = {
4233
+
.enable_reg = 0x2f05c,
4234
+
.enable_mask = BIT(0),
4235
+
.hw.init = &(const struct clk_init_data){
4236
+
.name = "gcc_usb3_sec_phy_aux_clk",
4237
+
.parent_hws = (const struct clk_hw*[]){
4238
+
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
4239
+
},
4240
+
.num_parents = 1,
4241
+
.flags = CLK_SET_RATE_PARENT,
4242
+
.ops = &clk_branch2_ops,
4243
+
},
4244
+
},
4245
+
};
4246
+
4247
+
static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
4248
+
.halt_reg = 0x2f060,
4249
+
.halt_check = BRANCH_HALT,
4250
+
.clkr = {
4251
+
.enable_reg = 0x2f060,
4252
+
.enable_mask = BIT(0),
4253
+
.hw.init = &(const struct clk_init_data){
4254
+
.name = "gcc_usb3_sec_phy_com_aux_clk",
4255
+
.parent_hws = (const struct clk_hw*[]){
4256
+
&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
4257
+
},
4258
+
.num_parents = 1,
4259
+
.flags = CLK_SET_RATE_PARENT,
4260
+
.ops = &clk_branch2_ops,
4261
+
},
4262
+
},
4263
+
};
4264
+
4265
+
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
4266
+
.halt_reg = 0x2f064,
4267
+
.halt_check = BRANCH_HALT_DELAY,
4268
+
.clkr = {
4269
+
.enable_reg = 0x2f064,
4270
+
.enable_mask = BIT(0),
4271
+
.hw.init = &(const struct clk_init_data){
4272
+
.name = "gcc_usb3_sec_phy_pipe_clk",
4273
+
.parent_hws = (const struct clk_hw*[]){
4274
+
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
4275
+
},
4276
+
.num_parents = 1,
4277
+
.flags = CLK_SET_RATE_PARENT,
4278
+
.ops = &clk_branch2_ops,
4279
+
},
4280
+
},
4281
+
};
4282
+
4283
+
static struct clk_branch gcc_usb_clkref_en = {
4284
+
.halt_reg = 0x97468,
4285
+
.halt_check = BRANCH_HALT_DELAY,
4286
+
.clkr = {
4287
+
.enable_reg = 0x97468,
4288
+
.enable_mask = BIT(0),
4289
+
.hw.init = &(const struct clk_init_data){
4290
+
.name = "gcc_usb_clkref_en",
4291
+
.ops = &clk_branch2_ops,
4292
+
},
4293
+
},
4294
+
};
4295
+
4296
+
static struct clk_branch gcc_video_axi0_clk = {
4297
+
.halt_reg = 0x34014,
4298
+
.halt_check = BRANCH_HALT_VOTED,
4299
+
.hwcg_reg = 0x34014,
4300
+
.hwcg_bit = 1,
4301
+
.clkr = {
4302
+
.enable_reg = 0x34014,
4303
+
.enable_mask = BIT(0),
4304
+
.hw.init = &(const struct clk_init_data){
4305
+
.name = "gcc_video_axi0_clk",
4306
+
.ops = &clk_branch2_ops,
4307
+
},
4308
+
},
4309
+
};
4310
+
4311
+
static struct clk_branch gcc_video_axi1_clk = {
4312
+
.halt_reg = 0x3401c,
4313
+
.halt_check = BRANCH_HALT_VOTED,
4314
+
.hwcg_reg = 0x3401c,
4315
+
.hwcg_bit = 1,
4316
+
.clkr = {
4317
+
.enable_reg = 0x3401c,
4318
+
.enable_mask = BIT(0),
4319
+
.hw.init = &(const struct clk_init_data){
4320
+
.name = "gcc_video_axi1_clk",
4321
+
.ops = &clk_branch2_ops,
4322
+
},
4323
+
},
4324
+
};
4325
+
4326
+
static struct gdsc pcie_0_gdsc = {
4327
+
.gdscr = 0xa9004,
4328
+
.pd = {
4329
+
.name = "pcie_0_gdsc",
4330
+
},
4331
+
.pwrsts = PWRSTS_OFF_ON,
4332
+
};
4333
+
4334
+
static struct gdsc pcie_1_gdsc = {
4335
+
.gdscr = 0x77004,
4336
+
.pd = {
4337
+
.name = "pcie_1_gdsc",
4338
+
},
4339
+
.pwrsts = PWRSTS_OFF_ON,
4340
+
};
4341
+
4342
+
static struct gdsc ufs_card_gdsc = {
4343
+
.gdscr = 0x81004,
4344
+
.pd = {
4345
+
.name = "ufs_card_gdsc",
4346
+
},
4347
+
.pwrsts = PWRSTS_OFF_ON,
4348
+
};
4349
+
4350
+
static struct gdsc ufs_phy_gdsc = {
4351
+
.gdscr = 0x83004,
4352
+
.pd = {
4353
+
.name = "ufs_phy_gdsc",
4354
+
},
4355
+
.pwrsts = PWRSTS_OFF_ON,
4356
+
};
4357
+
4358
+
static struct gdsc usb20_prim_gdsc = {
4359
+
.gdscr = 0x1c004,
4360
+
.pd = {
4361
+
.name = "usb20_prim_gdsc",
4362
+
},
4363
+
.pwrsts = PWRSTS_OFF_ON,
4364
+
};
4365
+
4366
+
static struct gdsc usb30_prim_gdsc = {
4367
+
.gdscr = 0x1b004,
4368
+
.pd = {
4369
+
.name = "usb30_prim_gdsc",
4370
+
},
4371
+
.pwrsts = PWRSTS_OFF_ON,
4372
+
};
4373
+
4374
+
static struct gdsc usb30_sec_gdsc = {
4375
+
.gdscr = 0x2f004,
4376
+
.pd = {
4377
+
.name = "usb30_sec_gdsc",
4378
+
},
4379
+
.pwrsts = PWRSTS_OFF_ON,
4380
+
};
4381
+
4382
+
static struct gdsc emac0_gdsc = {
4383
+
.gdscr = 0xb6004,
4384
+
.pd = {
4385
+
.name = "emac0_gdsc",
4386
+
},
4387
+
.pwrsts = PWRSTS_OFF_ON,
4388
+
};
4389
+
4390
+
static struct gdsc emac1_gdsc = {
4391
+
.gdscr = 0xb4004,
4392
+
.pd = {
4393
+
.name = "emac1_gdsc",
4394
+
},
4395
+
.pwrsts = PWRSTS_OFF_ON,
4396
+
};
4397
+
4398
+
static struct clk_regmap *gcc_sa8775p_clocks[] = {
4399
+
[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
4400
+
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
4401
+
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4402
+
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
4403
+
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
4404
+
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
4405
+
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
4406
+
[GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,
4407
+
[GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,
4408
+
[GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr,
4409
+
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
4410
+
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
4411
+
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
4412
+
[GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,
4413
+
[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
4414
+
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
4415
+
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
4416
+
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
4417
+
[GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr,
4418
+
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
4419
+
[GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr,
4420
+
[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
4421
+
[GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,
4422
+
[GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,
4423
+
[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
4424
+
[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
4425
+
[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
4426
+
[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
4427
+
[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
4428
+
[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
4429
+
[GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr,
4430
+
[GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr,
4431
+
[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
4432
+
[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
4433
+
[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
4434
+
[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
4435
+
[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
4436
+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4437
+
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
4438
+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4439
+
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
4440
+
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4441
+
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
4442
+
[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
4443
+
[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
4444
+
[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
4445
+
[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
4446
+
[GCC_GPLL0] = &gcc_gpll0.clkr,
4447
+
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
4448
+
[GCC_GPLL1] = &gcc_gpll1.clkr,
4449
+
[GCC_GPLL4] = &gcc_gpll4.clkr,
4450
+
[GCC_GPLL5] = &gcc_gpll5.clkr,
4451
+
[GCC_GPLL7] = &gcc_gpll7.clkr,
4452
+
[GCC_GPLL9] = &gcc_gpll9.clkr,
4453
+
[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
4454
+
[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
4455
+
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
4456
+
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
4457
+
[GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,
4458
+
[GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,
4459
+
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
4460
+
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
4461
+
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
4462
+
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
4463
+
[GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
4464
+
[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
4465
+
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
4466
+
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
4467
+
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
4468
+
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
4469
+
[GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr,
4470
+
[GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr,
4471
+
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
4472
+
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
4473
+
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
4474
+
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
4475
+
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
4476
+
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
4477
+
[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
4478
+
[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
4479
+
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
4480
+
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
4481
+
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
4482
+
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
4483
+
[GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr,
4484
+
[GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr,
4485
+
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
4486
+
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
4487
+
[GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
4488
+
[GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,
4489
+
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4490
+
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
4491
+
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4492
+
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
4493
+
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
4494
+
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
4495
+
[GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr,
4496
+
[GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr,
4497
+
[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
4498
+
[GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,
4499
+
[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
4500
+
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
4501
+
[GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr,
4502
+
[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
4503
+
[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
4504
+
[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
4505
+
[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
4506
+
[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
4507
+
[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4508
+
[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4509
+
[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4510
+
[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4511
+
[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4512
+
[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4513
+
[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4514
+
[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4515
+
[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4516
+
[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
4517
+
[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
4518
+
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
4519
+
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
4520
+
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4521
+
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4522
+
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4523
+
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4524
+
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4525
+
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4526
+
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4527
+
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4528
+
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4529
+
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4530
+
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4531
+
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4532
+
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
4533
+
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
4534
+
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
4535
+
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
4536
+
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
4537
+
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
4538
+
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
4539
+
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
4540
+
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
4541
+
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
4542
+
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
4543
+
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
4544
+
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
4545
+
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
4546
+
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
4547
+
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
4548
+
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
4549
+
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
4550
+
[GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
4551
+
[GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
4552
+
[GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr,
4553
+
[GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
4554
+
[GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
4555
+
[GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr,
4556
+
[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4557
+
[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4558
+
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4559
+
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4560
+
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
4561
+
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
4562
+
[GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr,
4563
+
[GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr,
4564
+
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4565
+
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4566
+
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
4567
+
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4568
+
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
4569
+
[GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr,
4570
+
[GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr,
4571
+
[GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr,
4572
+
[GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr,
4573
+
[GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr,
4574
+
[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
4575
+
[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
4576
+
[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
4577
+
[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
4578
+
[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
4579
+
[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
4580
+
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
4581
+
[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
4582
+
[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
4583
+
[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
4584
+
[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
4585
+
[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
4586
+
[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
4587
+
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
4588
+
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
4589
+
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4590
+
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4591
+
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4592
+
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
4593
+
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4594
+
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4595
+
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
4596
+
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4597
+
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4598
+
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
4599
+
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4600
+
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
4601
+
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
4602
+
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
4603
+
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4604
+
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
4605
+
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4606
+
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4607
+
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
4608
+
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
4609
+
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
4610
+
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
4611
+
[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
4612
+
[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
4613
+
[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
4614
+
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4615
+
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4616
+
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4617
+
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
4618
+
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
4619
+
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4620
+
[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
4621
+
[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
4622
+
[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
4623
+
[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
4624
+
[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
4625
+
[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
4626
+
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
4627
+
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4628
+
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4629
+
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4630
+
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
4631
+
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
4632
+
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
4633
+
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
4634
+
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
4635
+
[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
4636
+
[GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr,
4637
+
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4638
+
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
4639
+
};
4640
+
4641
+
static const struct qcom_reset_map gcc_sa8775p_resets[] = {
4642
+
[GCC_CAMERA_BCR] = { 0x32000 },
4643
+
[GCC_DISPLAY1_BCR] = { 0xc7000 },
4644
+
[GCC_DISPLAY_BCR] = { 0x33000 },
4645
+
[GCC_EMAC0_BCR] = { 0xb6000 },
4646
+
[GCC_EMAC1_BCR] = { 0xb4000 },
4647
+
[GCC_GPU_BCR] = { 0x7d000 },
4648
+
[GCC_MMSS_BCR] = { 0x17000 },
4649
+
[GCC_PCIE_0_BCR] = { 0xa9000 },
4650
+
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
4651
+
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
4652
+
[GCC_PCIE_0_PHY_BCR] = { 0xad144 },
4653
+
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
4654
+
[GCC_PCIE_1_BCR] = { 0x77000 },
4655
+
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
4656
+
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
4657
+
[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
4658
+
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
4659
+
[GCC_PDM_BCR] = { 0x3f000 },
4660
+
[GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
4661
+
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
4662
+
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 },
4663
+
[GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 },
4664
+
[GCC_SDCC1_BCR] = { 0x20000 },
4665
+
[GCC_TSCSS_BCR] = { 0x21000 },
4666
+
[GCC_UFS_CARD_BCR] = { 0x81000 },
4667
+
[GCC_UFS_PHY_BCR] = { 0x83000 },
4668
+
[GCC_USB20_PRIM_BCR] = { 0x1c000 },
4669
+
[GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 },
4670
+
[GCC_USB2_PHY_SEC_BCR] = { 0x5c02c },
4671
+
[GCC_USB30_PRIM_BCR] = { 0x1b000 },
4672
+
[GCC_USB30_SEC_BCR] = { 0x2f000 },
4673
+
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
4674
+
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 },
4675
+
[GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
4676
+
[GCC_USB3_PHY_SEC_BCR] = { 0x5c00c },
4677
+
[GCC_USB3_PHY_TERT_BCR] = { 0x5c030 },
4678
+
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 },
4679
+
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c },
4680
+
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
4681
+
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 },
4682
+
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
4683
+
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
4684
+
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
4685
+
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
4686
+
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
4687
+
[GCC_VIDEO_BCR] = { 0x34000 },
4688
+
};
4689
+
4690
+
static struct gdsc *gcc_sa8775p_gdscs[] = {
4691
+
[PCIE_0_GDSC] = &pcie_0_gdsc,
4692
+
[PCIE_1_GDSC] = &pcie_1_gdsc,
4693
+
[UFS_CARD_GDSC] = &ufs_card_gdsc,
4694
+
[UFS_PHY_GDSC] = &ufs_phy_gdsc,
4695
+
[USB20_PRIM_GDSC] = &usb20_prim_gdsc,
4696
+
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
4697
+
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
4698
+
[EMAC0_GDSC] = &emac0_gdsc,
4699
+
[EMAC1_GDSC] = &emac1_gdsc,
4700
+
};
4701
+
4702
+
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
4703
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
4704
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
4705
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
4706
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
4707
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
4708
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
4709
+
DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
4710
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
4711
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
4712
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
4713
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
4714
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
4715
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
4716
+
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
4717
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
4718
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
4719
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
4720
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
4721
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
4722
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
4723
+
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
4724
+
DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src),
4725
+
};
4726
+
4727
+
static const struct regmap_config gcc_sa8775p_regmap_config = {
4728
+
.reg_bits = 32,
4729
+
.reg_stride = 4,
4730
+
.val_bits = 32,
4731
+
.max_register = 0xc7018,
4732
+
.fast_io = true,
4733
+
};
4734
+
4735
+
static const struct qcom_cc_desc gcc_sa8775p_desc = {
4736
+
.config = &gcc_sa8775p_regmap_config,
4737
+
.clks = gcc_sa8775p_clocks,
4738
+
.num_clks = ARRAY_SIZE(gcc_sa8775p_clocks),
4739
+
.resets = gcc_sa8775p_resets,
4740
+
.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
4741
+
.gdscs = gcc_sa8775p_gdscs,
4742
+
.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
4743
+
};
4744
+
4745
+
static const struct of_device_id gcc_sa8775p_match_table[] = {
4746
+
{ .compatible = "qcom,sa8775p-gcc" },
4747
+
{ }
4748
+
};
4749
+
MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table);
4750
+
4751
+
static int gcc_sa8775p_probe(struct platform_device *pdev)
4752
+
{
4753
+
struct regmap *regmap;
4754
+
int ret;
4755
+
4756
+
regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc);
4757
+
if (IS_ERR(regmap))
4758
+
return PTR_ERR(regmap);
4759
+
4760
+
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4761
+
ARRAY_SIZE(gcc_dfs_clocks));
4762
+
if (ret)
4763
+
return ret;
4764
+
4765
+
/*
4766
+
* Keep the clocks always-ON
4767
+
* GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK,
4768
+
* GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
4769
+
* GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK.
4770
+
*/
4771
+
regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0));
4772
+
regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0));
4773
+
regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0));
4774
+
regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0));
4775
+
regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0));
4776
+
regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0));
4777
+
regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0));
4778
+
regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0));
4779
+
regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0));
4780
+
4781
+
return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
4782
+
}
4783
+
4784
+
static struct platform_driver gcc_sa8775p_driver = {
4785
+
.probe = gcc_sa8775p_probe,
4786
+
.driver = {
4787
+
.name = "sa8775p-gcc",
4788
+
.of_match_table = gcc_sa8775p_match_table,
4789
+
},
4790
+
};
4791
+
4792
+
static int __init gcc_sa8775p_init(void)
4793
+
{
4794
+
return platform_driver_register(&gcc_sa8775p_driver);
4795
+
}
4796
+
core_initcall(gcc_sa8775p_init);
4797
+
4798
+
static void __exit gcc_sa8775p_exit(void)
4799
+
{
4800
+
platform_driver_unregister(&gcc_sa8775p_driver);
4801
+
}
4802
+
module_exit(gcc_sa8775p_exit);
4803
+
4804
+
MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver");
4805
+
MODULE_LICENSE("GPL");