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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom: Introduce M31 USB PHY driver
Add the M31 USB2 phy driver for the USB M31 PHY
(https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332
SoCs.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Varadarajan Narayanan
and committed by
Vinod Koul
08e49af5
f444491c
+306
+11
drivers/phy/qualcomm/Kconfig
+11
drivers/phy/qualcomm/Kconfig
···
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PMICs. The repeater is paired with a Synopsys eUSB2 Phy
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on Qualcomm SOCs.
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config PHY_QCOM_M31_USB
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tristate "Qualcomm M31 HS PHY driver support"
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depends on USB && (ARCH_QCOM || COMPILE_TEST)
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select GENERIC_PHY
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help
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Enable this to support M31 HS PHY transceivers on Qualcomm chips
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with DWC3 USB core. It handles PHY initialization, clock
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management required after resetting the hardware and power
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management. This driver is required even for peripheral only or
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host only mode configurations.
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config PHY_QCOM_USB_HS
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tristate "Qualcomm USB HS PHY module"
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depends on USB_ULPI_BUS
+1
drivers/phy/qualcomm/Makefile
+1
drivers/phy/qualcomm/Makefile
···
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obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
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obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
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obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
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obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
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obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
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obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
+294
drivers/phy/qualcomm/phy-qcom-m31.c
+294
drivers/phy/qualcomm/phy-qcom-m31.c
···
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+
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2014-2023, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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+
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#define USB2PHY_PORT_UTMI_CTRL1 0x40
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+
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#define USB2PHY_PORT_UTMI_CTRL2 0x44
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#define UTMI_ULPI_SEL BIT(7)
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#define UTMI_TEST_MUX_SEL BIT(6)
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+
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#define HS_PHY_CTRL_REG 0x10
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#define UTMI_OTG_VBUS_VALID BIT(20)
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#define SW_SESSVLD_SEL BIT(28)
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+
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#define USB_PHY_UTMI_CTRL0 0x3c
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+
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#define USB_PHY_UTMI_CTRL5 0x50
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#define POR_EN BIT(1)
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+
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#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54
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#define COMMONONN BIT(7)
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#define FSEL BIT(4)
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#define RETENABLEN BIT(3)
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#define FREQ_24MHZ (BIT(6) | BIT(4))
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#define USB_PHY_HS_PHY_CTRL2 0x64
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#define USB2_SUSPEND_N_SEL BIT(3)
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#define USB2_SUSPEND_N BIT(2)
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#define USB2_UTMI_CLK_EN BIT(1)
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+
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#define USB_PHY_CFG0 0x94
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#define UTMI_PHY_OVERRIDE_EN BIT(1)
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+
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#define USB_PHY_REFCLK_CTRL 0xa0
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#define CLKCORE BIT(1)
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#define USB2PHY_PORT_POWERDOWN 0xa4
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#define POWER_UP BIT(0)
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#define POWER_DOWN 0
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#define USB_PHY_FSEL_SEL 0xb8
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#define FREQ_SEL BIT(0)
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#define USB2PHY_USB_PHY_M31_XCFGI_1 0xbc
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#define USB2_0_TX_ENABLE BIT(2)
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#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
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#define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
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#define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
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#define ODT_VALUE_38_02_OHM GENMASK(7, 6)
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#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
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#define ODT_VALUE_45_02_OHM BIT(2)
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#define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
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#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
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#define XCFG_COARSE_TUNE_NUM BIT(1)
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#define XCFG_FINE_TUNE_NUM BIT(3)
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struct m31_phy_regs {
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u32 off;
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u32 val;
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u32 delay;
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};
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struct m31_priv_data {
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bool ulpi_mode;
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const struct m31_phy_regs *regs;
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unsigned int nregs;
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};
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struct m31_phy_regs m31_ipq5332_regs[] = {
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{
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USB_PHY_CFG0,
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UTMI_PHY_OVERRIDE_EN,
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0
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},
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{
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USB_PHY_UTMI_CTRL5,
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POR_EN,
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15
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},
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{
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USB_PHY_FSEL_SEL,
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FREQ_SEL,
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0
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},
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{
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USB_PHY_HS_PHY_CTRL_COMMON0,
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COMMONONN | FREQ_24MHZ | RETENABLEN,
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0
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},
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{
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USB_PHY_UTMI_CTRL5,
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POR_EN,
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0
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},
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{
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USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
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0
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},
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{
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USB2PHY_USB_PHY_M31_XCFGI_11,
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XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM,
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0
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},
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{
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USB2PHY_USB_PHY_M31_XCFGI_4,
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HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
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0
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},
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{
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USB2PHY_USB_PHY_M31_XCFGI_1,
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USB2_0_TX_ENABLE,
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0
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},
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{
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USB2PHY_USB_PHY_M31_XCFGI_5,
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ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
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4
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},
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{
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USB_PHY_UTMI_CTRL5,
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0x0,
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0
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},
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{
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USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N | USB2_UTMI_CLK_EN,
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0
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},
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};
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struct m31usb_phy {
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struct phy *phy;
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void __iomem *base;
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const struct m31_phy_regs *regs;
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int nregs;
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struct regulator *vreg;
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struct clk *clk;
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struct reset_control *reset;
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bool ulpi_mode;
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};
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static int m31usb_phy_init(struct phy *phy)
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{
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struct m31usb_phy *qphy = phy_get_drvdata(phy);
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const struct m31_phy_regs *regs = qphy->regs;
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int i, ret;
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ret = regulator_enable(qphy->vreg);
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if (ret) {
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dev_err(&phy->dev, "failed to enable regulator, %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(qphy->clk);
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if (ret) {
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if (qphy->vreg)
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regulator_disable(qphy->vreg);
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dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
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return ret;
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}
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/* Perform phy reset */
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reset_control_assert(qphy->reset);
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udelay(5);
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reset_control_deassert(qphy->reset);
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/* configure for ULPI mode if requested */
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if (qphy->ulpi_mode)
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writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2);
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/* Enable the PHY */
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writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN);
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/* Turn on phy ref clock */
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for (i = 0; i < qphy->nregs; i++) {
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writel(regs[i].val, qphy->base + regs[i].off);
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if (regs[i].delay)
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udelay(regs[i].delay);
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}
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return 0;
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}
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static int m31usb_phy_shutdown(struct phy *phy)
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{
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struct m31usb_phy *qphy = phy_get_drvdata(phy);
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/* Disable the PHY */
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writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN);
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clk_disable_unprepare(qphy->clk);
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regulator_disable(qphy->vreg);
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return 0;
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}
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static const struct phy_ops m31usb_phy_gen_ops = {
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.power_on = m31usb_phy_init,
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.power_off = m31usb_phy_shutdown,
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.owner = THIS_MODULE,
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};
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static int m31usb_phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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const struct m31_priv_data *data;
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struct device *dev = &pdev->dev;
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struct m31usb_phy *qphy;
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qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
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if (!qphy)
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return -ENOMEM;
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qphy->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(qphy->base))
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return PTR_ERR(qphy->base);
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qphy->reset = devm_reset_control_get_exclusive_by_index(dev, 0);
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if (IS_ERR(qphy->reset))
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return PTR_ERR(qphy->reset);
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qphy->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(qphy->clk))
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return dev_err_probe(dev, PTR_ERR(qphy->clk),
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"failed to get clk\n");
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data = of_device_get_match_data(dev);
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qphy->regs = data->regs;
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qphy->nregs = data->nregs;
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qphy->ulpi_mode = data->ulpi_mode;
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qphy->phy = devm_phy_create(dev, NULL, &m31usb_phy_gen_ops);
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if (IS_ERR(qphy->phy))
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return dev_err_probe(dev, PTR_ERR(qphy->phy),
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"failed to create phy\n");
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qphy->vreg = devm_regulator_get(dev, "vdda-phy");
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if (IS_ERR(qphy->vreg))
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return dev_err_probe(dev, PTR_ERR(qphy->phy),
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"failed to get vreg\n");
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phy_set_drvdata(qphy->phy, qphy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (!IS_ERR(phy_provider))
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dev_info(dev, "Registered M31 USB phy\n");
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct m31_priv_data m31_ipq5332_data = {
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.ulpi_mode = false,
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.regs = m31_ipq5332_regs,
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.nregs = ARRAY_SIZE(m31_ipq5332_regs),
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};
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static const struct of_device_id m31usb_phy_id_table[] = {
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{ .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
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{ },
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};
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MODULE_DEVICE_TABLE(of, m31usb_phy_id_table);
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static struct platform_driver m31usb_phy_driver = {
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.probe = m31usb_phy_probe,
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.driver = {
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.name = "qcom-m31usb-phy",
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.of_match_table = m31usb_phy_id_table,
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},
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};
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module_platform_driver(m31usb_phy_driver);
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MODULE_DESCRIPTION("USB2 Qualcomm M31 HSPHY driver");
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MODULE_LICENSE("GPL");