Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add GPU clock controller driver for SM6115
Add support for the GPU clock controller found on SM6115.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-11-konrad.dybcio@linaro.org
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
092209f1
8397e242
+513
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
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Say Y if you want to use peripheral devices such as UART,
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SPI, I2C, USB, SD/UFS, PCIe etc.
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config SM_GPUCC_6115
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tristate "SM6115 Graphics Clock Controller"
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select SM_GCC_6115
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depends on ARM64 || COMPILE_TEST
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help
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Support for the graphics clock controller on SM6115 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config SM_GPUCC_6125
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tristate "SM6125 Graphics Clock Controller"
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select SM_GCC_6125
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drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
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obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
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obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
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obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o
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obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
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obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
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obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o
+503
drivers/clk/qcom/gpucc-sm6115.c
+503
drivers/clk/qcom/gpucc-sm6115.c
···
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+
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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+
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
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+
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "gdsc.h"
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#include "reset.h"
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+
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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};
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+
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_AUX2,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_AUX,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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+
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static struct pll_vco default_vco[] = {
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{ 1000000000, 2000000000, 0 },
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};
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static struct pll_vco pll1_vco[] = {
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{ 500000000, 1000000000, 2 },
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};
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+
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x3e,
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.alpha = 0,
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.alpha_hi = 0x80,
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.vco_val = 0x0 << 20,
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.vco_mask = GENMASK(21, 20),
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.alpha_en_mask = BIT(24),
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.main_output_mask = BIT(0),
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.aux_output_mask = BIT(1),
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.aux2_output_mask = BIT(2),
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.config_ctl_val = 0x4001055b,
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.test_ctl_hi1_val = 0x1,
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};
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+
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/* 1200MHz configuration */
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = default_vco,
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.num_vco = ARRAY_SIZE(default_vco),
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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+
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static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = {
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{ 0x0, 1 },
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{ }
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};
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+
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static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = {
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.offset = 0x0,
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.post_div_shift = 8,
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.post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
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.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll0_out_aux2",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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+
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/* 640MHz configuration */
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static const struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x21,
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.alpha = 0x55555555,
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.alpha_hi = 0x55,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = GENMASK(21, 20),
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.main_output_mask = BIT(0),
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.aux_output_mask = BIT(1),
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.config_ctl_val = 0x4001055b,
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.test_ctl_hi1_val = 0x1,
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};
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+
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = pll1_vco,
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.num_vco = ARRAY_SIZE(pll1_vco),
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.flags = SUPPORTS_DYNAMIC_UPDATE,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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},
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};
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+
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static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = {
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{ 0x0, 1 },
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{ }
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};
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+
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static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = {
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.offset = 0x100,
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.post_div_shift = 15,
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.post_div_table = post_div_table_gpu_cc_pll1_out_aux,
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.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux),
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.width = 3,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1_out_aux",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_pll1.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_ops,
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},
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};
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+
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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+
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
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};
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+
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
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{ P_GPU_CC_PLL1_OUT_AUX, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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+
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
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{ .hw = &gpu_cc_pll1_out_aux.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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+
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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+
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
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F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
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F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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{ }
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};
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+
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_rcg2_ops,
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},
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};
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+
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
262
+
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static struct clk_branch gpu_cc_cx_gfx3d_clk = {
264
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
266
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.clkr = {
267
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.enable_reg = 0x10a4,
268
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.enable_mask = BIT(0),
269
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.hw.init = &(struct clk_init_data){
270
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.name = "gpu_cc_cx_gfx3d_clk",
271
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.parent_data = &(const struct clk_parent_data){
272
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.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
274
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.num_parents = 1,
275
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
277
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},
278
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},
279
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};
280
+
281
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static struct clk_branch gpu_cc_cx_gmu_clk = {
282
+
.halt_reg = 0x1098,
283
+
.halt_check = BRANCH_HALT,
284
+
.clkr = {
285
+
.enable_reg = 0x1098,
286
+
.enable_mask = BIT(0),
287
+
.hw.init = &(struct clk_init_data){
288
+
.name = "gpu_cc_cx_gmu_clk",
289
+
.parent_data = &(const struct clk_parent_data){
290
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
292
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
298
+
299
+
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
300
+
.halt_reg = 0x108c,
301
+
.halt_check = BRANCH_HALT_DELAY,
302
+
.clkr = {
303
+
.enable_reg = 0x108c,
304
+
.enable_mask = BIT(0),
305
+
.hw.init = &(struct clk_init_data){
306
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.name = "gpu_cc_cx_snoc_dvm_clk",
307
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.ops = &clk_branch2_ops,
308
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},
309
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},
310
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};
311
+
312
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static struct clk_branch gpu_cc_cxo_aon_clk = {
313
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.halt_reg = 0x1004,
314
+
.halt_check = BRANCH_HALT_DELAY,
315
+
.clkr = {
316
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.enable_reg = 0x1004,
317
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.enable_mask = BIT(0),
318
+
.hw.init = &(struct clk_init_data){
319
+
.name = "gpu_cc_cxo_aon_clk",
320
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.ops = &clk_branch2_ops,
321
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},
322
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},
323
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};
324
+
325
+
static struct clk_branch gpu_cc_cxo_clk = {
326
+
.halt_reg = 0x109c,
327
+
.halt_check = BRANCH_HALT,
328
+
.clkr = {
329
+
.enable_reg = 0x109c,
330
+
.enable_mask = BIT(0),
331
+
.hw.init = &(struct clk_init_data){
332
+
.name = "gpu_cc_cxo_clk",
333
+
.ops = &clk_branch2_ops,
334
+
},
335
+
},
336
+
};
337
+
338
+
static struct clk_branch gpu_cc_gx_cxo_clk = {
339
+
.halt_reg = 0x1060,
340
+
.halt_check = BRANCH_HALT_DELAY,
341
+
.clkr = {
342
+
.enable_reg = 0x1060,
343
+
.enable_mask = BIT(0),
344
+
.hw.init = &(struct clk_init_data){
345
+
.name = "gpu_cc_gx_cxo_clk",
346
+
.flags = CLK_IS_CRITICAL,
347
+
.ops = &clk_branch2_ops,
348
+
},
349
+
},
350
+
};
351
+
352
+
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
353
+
.halt_reg = 0x1054,
354
+
.halt_check = BRANCH_HALT_SKIP,
355
+
.clkr = {
356
+
.enable_reg = 0x1054,
357
+
.enable_mask = BIT(0),
358
+
.hw.init = &(struct clk_init_data){
359
+
.name = "gpu_cc_gx_gfx3d_clk",
360
+
.parent_data = &(const struct clk_parent_data){
361
+
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
362
+
},
363
+
.num_parents = 1,
364
+
.flags = CLK_SET_RATE_PARENT,
365
+
.ops = &clk_branch2_ops,
366
+
},
367
+
},
368
+
};
369
+
370
+
static struct clk_branch gpu_cc_sleep_clk = {
371
+
.halt_reg = 0x1090,
372
+
.halt_check = BRANCH_HALT_DELAY,
373
+
.clkr = {
374
+
.enable_reg = 0x1090,
375
+
.enable_mask = BIT(0),
376
+
.hw.init = &(struct clk_init_data){
377
+
.name = "gpu_cc_sleep_clk",
378
+
.ops = &clk_branch2_ops,
379
+
},
380
+
},
381
+
};
382
+
383
+
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
384
+
.halt_reg = 0x5000,
385
+
.halt_check = BRANCH_VOTED,
386
+
.clkr = {
387
+
.enable_reg = 0x5000,
388
+
.enable_mask = BIT(0),
389
+
.hw.init = &(struct clk_init_data){
390
+
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
391
+
.ops = &clk_branch2_ops,
392
+
},
393
+
},
394
+
};
395
+
396
+
static struct gdsc gpu_cx_gdsc = {
397
+
.gdscr = 0x106c,
398
+
.gds_hw_ctrl = 0x1540,
399
+
.pd = {
400
+
.name = "gpu_cx_gdsc",
401
+
},
402
+
.pwrsts = PWRSTS_OFF_ON,
403
+
.flags = VOTABLE,
404
+
};
405
+
406
+
static struct gdsc gpu_gx_gdsc = {
407
+
.gdscr = 0x100c,
408
+
.clamp_io_ctrl = 0x1508,
409
+
.resets = (unsigned int []){ GPU_GX_BCR },
410
+
.reset_count = 1,
411
+
.pd = {
412
+
.name = "gpu_gx_gdsc",
413
+
},
414
+
.parent = &gpu_cx_gdsc.pd,
415
+
.pwrsts = PWRSTS_OFF_ON,
416
+
.flags = CLAMP_IO | SW_RESET | VOTABLE,
417
+
};
418
+
419
+
static struct clk_regmap *gpu_cc_sm6115_clocks[] = {
420
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
421
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
422
+
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
423
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
424
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
425
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
426
+
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
427
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
428
+
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
429
+
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
430
+
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
431
+
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
432
+
[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
433
+
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
434
+
[GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr,
435
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
436
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
437
+
};
438
+
439
+
static const struct qcom_reset_map gpu_cc_sm6115_resets[] = {
440
+
[GPU_GX_BCR] = { 0x1008 },
441
+
};
442
+
443
+
static struct gdsc *gpu_cc_sm6115_gdscs[] = {
444
+
[GPU_CX_GDSC] = &gpu_cx_gdsc,
445
+
[GPU_GX_GDSC] = &gpu_gx_gdsc,
446
+
};
447
+
448
+
static const struct regmap_config gpu_cc_sm6115_regmap_config = {
449
+
.reg_bits = 32,
450
+
.reg_stride = 4,
451
+
.val_bits = 32,
452
+
.max_register = 0x9000,
453
+
.fast_io = true,
454
+
};
455
+
456
+
static const struct qcom_cc_desc gpu_cc_sm6115_desc = {
457
+
.config = &gpu_cc_sm6115_regmap_config,
458
+
.clks = gpu_cc_sm6115_clocks,
459
+
.num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks),
460
+
.resets = gpu_cc_sm6115_resets,
461
+
.num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets),
462
+
.gdscs = gpu_cc_sm6115_gdscs,
463
+
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs),
464
+
};
465
+
466
+
static const struct of_device_id gpu_cc_sm6115_match_table[] = {
467
+
{ .compatible = "qcom,sm6115-gpucc" },
468
+
{ }
469
+
};
470
+
MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table);
471
+
472
+
static int gpu_cc_sm6115_probe(struct platform_device *pdev)
473
+
{
474
+
struct regmap *regmap;
475
+
476
+
regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc);
477
+
if (IS_ERR(regmap))
478
+
return PTR_ERR(regmap);
479
+
480
+
clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
481
+
clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
482
+
483
+
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
484
+
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
485
+
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
486
+
487
+
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
488
+
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
489
+
490
+
return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap);
491
+
}
492
+
493
+
static struct platform_driver gpu_cc_sm6115_driver = {
494
+
.probe = gpu_cc_sm6115_probe,
495
+
.driver = {
496
+
.name = "sm6115-gpucc",
497
+
.of_match_table = gpu_cc_sm6115_match_table,
498
+
},
499
+
};
500
+
module_platform_driver(gpu_cc_sm6115_driver);
501
+
502
+
MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver");
503
+
MODULE_LICENSE("GPL");