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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add GPU clock controller driver for SM6375
Add support for the GPU clock controller found on SM6375.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208091340.124641-9-konrad.dybcio@linaro.org
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
8397e242
a6b18286
+479
+9
drivers/clk/qcom/Kconfig
+9
drivers/clk/qcom/Kconfig
···
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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809
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config SM_GPUCC_6375
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tristate "SM6375 Graphics Clock Controller"
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select SM_GCC_6375
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depends on ARM64 || COMPILE_TEST
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help
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Support for the graphics clock controller on SM6375 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config SM_GPUCC_6350
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tristate "SM6350 Graphics Clock Controller"
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select SM_GCC_6350
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
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obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
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obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
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obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
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obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
+469
drivers/clk/qcom/gpucc-sm6375.c
+469
drivers/clk/qcom/gpucc-sm6375.c
···
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+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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+
*/
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+
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
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+
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "gdsc.h"
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#include "reset.h"
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+
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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DT_GCC_GPU_SNOC_DVM_GFX_CLK,
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};
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+
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enum {
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P_BI_TCXO,
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P_GCC_GPU_GPLL0_CLK_SRC,
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P_GCC_GPU_GPLL0_DIV_CLK_SRC,
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P_GPU_CC_PLL0_OUT_EVEN,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL0_OUT_ODD,
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P_GPU_CC_PLL1_OUT_EVEN,
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P_GPU_CC_PLL1_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_ODD,
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};
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+
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static struct pll_vco lucid_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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+
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/* 532MHz Configuration */
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static const struct alpha_pll_config gpucc_pll0_config = {
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.l = 0x1b,
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.alpha = 0xb555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x329a299c,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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+
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static struct clk_alpha_pll gpucc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_pll0",
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+
.parent_data = &(const struct clk_parent_data){
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.index = P_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
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},
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},
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};
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+
76
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/* 514MHz Configuration */
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static const struct alpha_pll_config gpucc_pll1_config = {
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.l = 0x1a,
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.alpha = 0xc555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x329a299c,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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+
88
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static struct clk_alpha_pll gpucc_pll1 = {
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.offset = 0x100,
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.vco_table = lucid_vco,
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.num_vco = ARRAY_SIZE(lucid_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(struct clk_init_data){
95
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.name = "gpucc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.index = P_BI_TCXO,
98
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_ops,
101
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},
102
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},
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};
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+
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static const struct parent_map gpucc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
111
+
};
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+
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static const struct clk_parent_data gpucc_parent_data_0[] = {
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{ .index = P_BI_TCXO },
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{ .hw = &gpucc_pll0.clkr.hw },
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{ .hw = &gpucc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
119
+
};
120
+
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static const struct parent_map gpucc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
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{ P_GPU_CC_PLL0_OUT_ODD, 2 },
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{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
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{ P_GPU_CC_PLL1_OUT_ODD, 4 },
127
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
128
+
};
129
+
130
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static const struct clk_parent_data gpucc_parent_data_1[] = {
131
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{ .index = P_BI_TCXO },
132
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{ .hw = &gpucc_pll0.clkr.hw },
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{ .hw = &gpucc_pll0.clkr.hw },
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{ .hw = &gpucc_pll1.clkr.hw },
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{ .hw = &gpucc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
137
+
};
138
+
139
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static const struct parent_map gpucc_parent_map_2[] = {
140
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{ P_BI_TCXO, 0 },
141
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
142
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
143
+
};
144
+
145
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static const struct clk_parent_data gpucc_parent_data_2[] = {
146
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{ .index = P_BI_TCXO },
147
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
149
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};
150
+
151
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static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = {
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F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
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{ }
154
+
};
155
+
156
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static struct clk_rcg2 gpucc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_0,
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.freq_tbl = ftbl_gpucc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpucc_gmu_clk_src",
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.parent_data = gpucc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpucc_parent_data_0),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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+
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static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = {
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F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
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{ }
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};
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+
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static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_1,
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.freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpucc_gx_gfx3d_clk_src",
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.parent_data = gpucc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpucc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_rcg2_ops,
193
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},
194
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};
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+
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static struct clk_branch gpucc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpucc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpucc_cx_gfx3d_slv_clk = {
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.halt_reg = 0x10a8,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
232
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.enable_reg = 0x10a8,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
235
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.name = "gpucc_cx_gfx3d_slv_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpucc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpucc_cx_gmu_clk = {
247
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.halt_reg = 0x1098,
248
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.halt_check = BRANCH_HALT,
249
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.clkr = {
250
+
.enable_reg = 0x1098,
251
+
.enable_mask = BIT(0),
252
+
.hw.init = &(struct clk_init_data){
253
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.name = "gpucc_cx_gmu_clk",
254
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.parent_hws = (const struct clk_hw*[]) {
255
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&gpucc_gmu_clk_src.clkr.hw,
256
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},
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+
.num_parents = 1,
258
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.flags = CLK_SET_RATE_PARENT,
259
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.ops = &clk_branch2_ops,
260
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},
261
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},
262
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};
263
+
264
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static struct clk_branch gpucc_cx_snoc_dvm_clk = {
265
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.halt_reg = 0x108c,
266
+
.halt_check = BRANCH_HALT_DELAY,
267
+
.clkr = {
268
+
.enable_reg = 0x108c,
269
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.enable_mask = BIT(0),
270
+
.hw.init = &(struct clk_init_data){
271
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.name = "gpucc_cx_snoc_dvm_clk",
272
+
.parent_data = &(const struct clk_parent_data){
273
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.index = DT_GCC_GPU_SNOC_DVM_GFX_CLK,
274
+
},
275
+
.num_parents = 1,
276
+
.ops = &clk_branch2_ops,
277
+
},
278
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},
279
+
};
280
+
281
+
static struct clk_branch gpucc_cxo_aon_clk = {
282
+
.halt_reg = 0x1004,
283
+
.halt_check = BRANCH_HALT_DELAY,
284
+
.clkr = {
285
+
.enable_reg = 0x1004,
286
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.enable_mask = BIT(0),
287
+
.hw.init = &(struct clk_init_data){
288
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.name = "gpucc_cxo_aon_clk",
289
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.ops = &clk_branch2_ops,
290
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},
291
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},
292
+
};
293
+
294
+
static struct clk_branch gpucc_cxo_clk = {
295
+
.halt_reg = 0x109c,
296
+
.halt_check = BRANCH_HALT,
297
+
.clkr = {
298
+
.enable_reg = 0x109c,
299
+
.enable_mask = BIT(0),
300
+
.hw.init = &(struct clk_init_data){
301
+
.name = "gpucc_cxo_clk",
302
+
.ops = &clk_branch2_ops,
303
+
},
304
+
},
305
+
};
306
+
307
+
static struct clk_branch gpucc_gx_cxo_clk = {
308
+
.halt_reg = 0x1060,
309
+
.halt_check = BRANCH_HALT_DELAY,
310
+
.clkr = {
311
+
.enable_reg = 0x1060,
312
+
.enable_mask = BIT(0),
313
+
.hw.init = &(struct clk_init_data){
314
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.name = "gpucc_gx_cxo_clk",
315
+
.flags = CLK_IS_CRITICAL,
316
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.ops = &clk_branch2_ops,
317
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},
318
+
},
319
+
};
320
+
321
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static struct clk_branch gpucc_gx_gfx3d_clk = {
322
+
.halt_reg = 0x1054,
323
+
.halt_check = BRANCH_HALT_DELAY,
324
+
.clkr = {
325
+
.enable_reg = 0x1054,
326
+
.enable_mask = BIT(0),
327
+
.hw.init = &(struct clk_init_data){
328
+
.name = "gpucc_gx_gfx3d_clk",
329
+
.parent_hws = (const struct clk_hw*[]) {
330
+
&gpucc_gx_gfx3d_clk_src.clkr.hw,
331
+
},
332
+
.num_parents = 1,
333
+
.flags = CLK_SET_RATE_PARENT,
334
+
.ops = &clk_branch2_ops,
335
+
},
336
+
},
337
+
};
338
+
339
+
static struct clk_branch gpucc_gx_gmu_clk = {
340
+
.halt_reg = 0x1064,
341
+
.halt_check = BRANCH_HALT,
342
+
.clkr = {
343
+
.enable_reg = 0x1064,
344
+
.enable_mask = BIT(0),
345
+
.hw.init = &(struct clk_init_data){
346
+
.name = "gpucc_gx_gmu_clk",
347
+
.parent_hws = (const struct clk_hw*[]) {
348
+
&gpucc_gmu_clk_src.clkr.hw,
349
+
},
350
+
.num_parents = 1,
351
+
.flags = CLK_SET_RATE_PARENT,
352
+
.ops = &clk_branch2_ops,
353
+
},
354
+
},
355
+
};
356
+
357
+
static struct clk_branch gpucc_sleep_clk = {
358
+
.halt_reg = 0x1090,
359
+
.halt_check = BRANCH_HALT_VOTED,
360
+
.clkr = {
361
+
.enable_reg = 0x1090,
362
+
.enable_mask = BIT(0),
363
+
.hw.init = &(struct clk_init_data){
364
+
.name = "gpucc_sleep_clk",
365
+
.ops = &clk_branch2_ops,
366
+
},
367
+
},
368
+
};
369
+
370
+
static struct gdsc gpu_cx_gdsc = {
371
+
.gdscr = 0x106c,
372
+
.gds_hw_ctrl = 0x1540,
373
+
.pd = {
374
+
.name = "gpu_cx_gdsc",
375
+
},
376
+
.pwrsts = PWRSTS_OFF_ON,
377
+
.flags = VOTABLE,
378
+
};
379
+
380
+
static struct gdsc gpu_gx_gdsc = {
381
+
.gdscr = 0x100c,
382
+
.clamp_io_ctrl = 0x1508,
383
+
.resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR },
384
+
.reset_count = 3,
385
+
.pd = {
386
+
.name = "gpu_gx_gdsc",
387
+
},
388
+
.pwrsts = PWRSTS_OFF_ON,
389
+
.flags = CLAMP_IO | SW_RESET | AON_RESET,
390
+
};
391
+
392
+
static struct clk_regmap *gpucc_sm6375_clocks[] = {
393
+
[GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr,
394
+
[GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr,
395
+
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr,
396
+
[GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr,
397
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr,
398
+
[GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr,
399
+
[GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr,
400
+
[GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr,
401
+
[GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr,
402
+
[GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr,
403
+
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr,
404
+
[GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr,
405
+
[GPU_CC_PLL0] = &gpucc_pll0.clkr,
406
+
[GPU_CC_PLL1] = &gpucc_pll1.clkr,
407
+
[GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr,
408
+
};
409
+
410
+
static const struct qcom_reset_map gpucc_sm6375_resets[] = {
411
+
[GPU_GX_BCR] = { 0x1008 },
412
+
[GPU_ACD_BCR] = { 0x1160 },
413
+
[GPU_GX_ACD_MISC_BCR] = { 0x8004 },
414
+
};
415
+
416
+
static struct gdsc *gpucc_sm6375_gdscs[] = {
417
+
[GPU_CX_GDSC] = &gpu_cx_gdsc,
418
+
[GPU_GX_GDSC] = &gpu_gx_gdsc,
419
+
};
420
+
421
+
static const struct regmap_config gpucc_sm6375_regmap_config = {
422
+
.reg_bits = 32,
423
+
.reg_stride = 4,
424
+
.val_bits = 32,
425
+
.max_register = 0x9000,
426
+
.fast_io = true,
427
+
};
428
+
429
+
static const struct qcom_cc_desc gpucc_sm6375_desc = {
430
+
.config = &gpucc_sm6375_regmap_config,
431
+
.clks = gpucc_sm6375_clocks,
432
+
.num_clks = ARRAY_SIZE(gpucc_sm6375_clocks),
433
+
.resets = gpucc_sm6375_resets,
434
+
.num_resets = ARRAY_SIZE(gpucc_sm6375_resets),
435
+
.gdscs = gpucc_sm6375_gdscs,
436
+
.num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs),
437
+
};
438
+
439
+
static const struct of_device_id gpucc_sm6375_match_table[] = {
440
+
{ .compatible = "qcom,sm6375-gpucc" },
441
+
{ }
442
+
};
443
+
MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table);
444
+
445
+
static int gpucc_sm6375_probe(struct platform_device *pdev)
446
+
{
447
+
struct regmap *regmap;
448
+
449
+
regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc);
450
+
if (IS_ERR(regmap))
451
+
return PTR_ERR(regmap);
452
+
453
+
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
454
+
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
455
+
456
+
return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
457
+
}
458
+
459
+
static struct platform_driver gpucc_sm6375_driver = {
460
+
.probe = gpucc_sm6375_probe,
461
+
.driver = {
462
+
.name = "gpucc-sm6375",
463
+
.of_match_table = gpucc_sm6375_match_table,
464
+
},
465
+
};
466
+
module_platform_driver(gpucc_sm6375_driver);
467
+
468
+
MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver");
469
+
MODULE_LICENSE("GPL");