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arm64: Convert SCTLR_EL2 to sysreg infrastructure

Convert SCTLR_EL2 to the sysreg infrastructure, as per the 2025-12_rel
revision of the Registers.json file.

Note that we slightly deviate from the above, as we stick to the ARM
ARM M.a definition of SCTLR_EL2[9], which is RES0, in order to avoid
dragging the POE2 definitions...

Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Link: https://patch.msgid.link/20260202184329.2724080-2-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

Marc Zyngier 0a35bd28 2eb80a2e

+69 -13
-7
arch/arm64/include/asm/sysreg.h
··· 504 504 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) 505 505 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) 506 506 507 - #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 508 507 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) 509 508 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) 510 509 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) ··· 836 837 #define SCTLR_ELx_A (BIT(1)) 837 838 #define SCTLR_ELx_M (BIT(0)) 838 839 839 - /* SCTLR_EL2 specific flags. */ 840 - #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 841 - (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 842 - (BIT(29))) 843 - 844 - #define SCTLR_EL2_BT (BIT(36)) 845 840 #ifdef CONFIG_CPU_BIG_ENDIAN 846 841 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 847 842 #else
+69
arch/arm64/tools/sysreg
··· 3749 3749 EndEnum 3750 3750 EndSysreg 3751 3751 3752 + Sysreg SCTLR_EL2 3 4 1 0 0 3753 + Field 63 TIDCP 3754 + Field 62 SPINTMASK 3755 + Field 61 NMI 3756 + Field 60 EnTP2 3757 + Field 59 TCSO 3758 + Field 58 TCSO0 3759 + Field 57 EPAN 3760 + Field 56 EnALS 3761 + Field 55 EnAS0 3762 + Field 54 EnASR 3763 + Res0 53:50 3764 + Field 49:46 TWEDEL 3765 + Field 45 TWEDEn 3766 + Field 44 DSSBS 3767 + Field 43 ATA 3768 + Field 42 ATA0 3769 + Enum 41:40 TCF 3770 + 0b00 NONE 3771 + 0b01 SYNC 3772 + 0b10 ASYNC 3773 + 0b11 ASYMM 3774 + EndEnum 3775 + Enum 39:38 TCF0 3776 + 0b00 NONE 3777 + 0b01 SYNC 3778 + 0b10 ASYNC 3779 + 0b11 ASYMM 3780 + EndEnum 3781 + Field 37 ITFSB 3782 + Field 36 BT 3783 + Field 35 BT0 3784 + Field 34 EnFPM 3785 + Field 33 MSCEn 3786 + Field 32 CMOW 3787 + Field 31 EnIA 3788 + Field 30 EnIB 3789 + Field 29 LSMAOE 3790 + Field 28 nTLSMD 3791 + Field 27 EnDA 3792 + Field 26 UCI 3793 + Field 25 EE 3794 + Field 24 E0E 3795 + Field 23 SPAN 3796 + Field 22 EIS 3797 + Field 21 IESB 3798 + Field 20 TSCXT 3799 + Field 19 WXN 3800 + Field 18 nTWE 3801 + Res0 17 3802 + Field 16 nTWI 3803 + Field 15 UCT 3804 + Field 14 DZE 3805 + Field 13 EnDB 3806 + Field 12 I 3807 + Field 11 EOS 3808 + Field 10 EnRCTX 3809 + Res0 9 3810 + Field 8 SED 3811 + Field 7 ITD 3812 + Field 6 nAA 3813 + Field 5 CP15BEN 3814 + Field 4 SA0 3815 + Field 3 SA 3816 + Field 2 C 3817 + Field 1 A 3818 + Field 0 M 3819 + EndSysreg 3820 + 3752 3821 Sysreg HCR_EL2 3 4 1 1 0 3753 3822 Field 63:60 TWEDEL 3754 3823 Field 59 TWEDEn
-6
tools/arch/arm64/include/asm/sysreg.h
··· 847 847 #define SCTLR_ELx_A (BIT(1)) 848 848 #define SCTLR_ELx_M (BIT(0)) 849 849 850 - /* SCTLR_EL2 specific flags. */ 851 - #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 852 - (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 853 - (BIT(29))) 854 - 855 - #define SCTLR_EL2_BT (BIT(36)) 856 850 #ifdef CONFIG_CPU_BIG_ENDIAN 857 851 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 858 852 #else