Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'ti-k3-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v6.20
Generic Fixes/Cleanups:
- Minor whitespace cleanup and lowercase hex formatting for consistency
- Various DT schema warning fixes across multiple boards
SoC Specific Features and Fixes:
AM62P/J722S:
- Add HSM M4F node for hardware security module support
J784S4/J742S2/J721S2:
- Add HSM M4F node for hardware security module support
- Refactor watchdog instances for j784s4
- Move c71_3 node to appropriate order in device tree
Board Specific Fixes:
AM62:
- phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel
AM62A:
- phycore-som: Add bootphase tags to cpsw_mac_syscon and phy_gmii_sel
AM62P:
- Verdin: Fix SD regulator startup delay
AM67A:
- Kontron SA67: Fix CMA node and SD card regulator configuration
AM69:
- Aquila: Change main_spi0/2 chip select to GPIO mode
- Aquila-clover: Change main_spi2 CS0 to GPIO mode
- Aquila-dev/clover: Fix USB-C Sink PDO configuration
* tag 'ti-k3-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix SD card regulator
arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix CMA node
arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node
arm64: dts: ti: k3-{j784s4-j742s2/j721s2}-mcu-wakeup: Add HSM M4F node
arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for j784s4
arm64: dts: ti: k3-j784s4-main.dtsi: Move c71_3 node to appropriate order
arm64: dts: ti: k3-am69-aquila-clover: Change main_spi2 CS0 to GPIO mode
arm64: dts: ti: k3-am69-aquila: Change main_spi0/2 CS to GPIO mode
arm64: dts: ti: Use lowercase hex
arm64: dts: ti: Minor whitespace cleanup
arm64: dts: ti: am62p-verdin: Fix SD regulator startup delay
arm64: dts: ti: k3-am69-aquila-clover: Fix USB-C Sink PDO
arm64: dts: ti: k3-am69-aquila-dev: Fix USB-C Sink PDO
arm64: dts: ti: k3-am62(a)-phycore-som: Add bootphase tag to phy_gmii_sel
arm64: dts: ti: k3-am62a-phycore-som: Add bootphase tag to cpsw_mac_syscon
arm64: dts: ti: k3-am62-phycore-som: Add bootphase tag to cpsw_mac_syscon
arm64: dts: ti: k3-am62-lp-sk-nand: Rename pinctrls to fix schema warnings
arm64: dts: ti: k3-am642-phyboard-electra-x27-gpio1-spi1-uart3: Fix schema warnings
arm64: dts: ti: k3-am642-phyboard-electra-peb-c-010: Fix icssg-prueth schema warning
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+238
-160
+1
-1
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
+1
-1
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
+8
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
+8
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
···
220
220
bootph-all;
221
221
};
222
222
223
+
&cpsw_mac_syscon {
224
+
bootph-all;
225
+
};
226
+
223
227
&cpsw3g_mdio {
224
228
pinctrl-names = "default";
225
229
pinctrl-0 = <&main_mdio1_pins_default>;
···
361
357
cdns,read-delay = <0>;
362
358
bootph-all;
363
359
};
360
+
};
361
+
362
+
&phy_gmii_sel {
363
+
bootph-all;
364
364
};
365
365
366
366
&sdhci0 {
+8
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+8
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
···
197
197
bootph-all;
198
198
};
199
199
200
+
&cpsw_mac_syscon {
201
+
bootph-all;
202
+
};
203
+
200
204
&cpsw3g_mdio {
201
205
pinctrl-names = "default";
202
206
pinctrl-0 = <&main_mdio1_pins_default>;
···
352
348
cdns,read-delay = <0>;
353
349
bootph-all;
354
350
};
351
+
};
352
+
353
+
&phy_gmii_sel {
354
+
bootph-all;
355
355
};
356
356
357
357
&sdhci0 {
+1
-1
arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
+1
-1
arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
+17
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+17
arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
···
1117
1117
clocks = <&k3_clks 204 2>;
1118
1118
power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
1119
1119
};
1120
+
1121
+
hsm: remoteproc@43c00000 {
1122
+
compatible = "ti,hsm-m4fss";
1123
+
/* contiguous regions but instantiated separately in HW */
1124
+
reg = <0x00 0x43c00000 0x00 0x20000>,
1125
+
<0x00 0x43c20000 0x00 0x10000>,
1126
+
<0x00 0x43c30000 0x00 0x10000>;
1127
+
reg-names = "sram0_0", "sram0_1", "sram1";
1128
+
resets = <&k3_reset 225 1>;
1129
+
firmware-name = "am62p-hsm-m4f-fw";
1130
+
bootph-pre-ram;
1131
+
ti,sci = <&dmsc>;
1132
+
ti,sci-dev-id = <225>;
1133
+
ti,sci-proc-ids = <0x80 0xff>;
1134
+
/* reserved for early-stage bootloader */
1135
+
status = "reserved";
1136
+
};
1120
1137
};
+2
-2
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
···
112
112
regulator-max-microvolt = <3300000>;
113
113
regulator-min-microvolt = <3300000>;
114
114
regulator-name = "+V3.3_SD";
115
-
startup-delay-us = <2000>;
115
+
startup-delay-us = <20000>;
116
116
};
117
117
118
118
reg_sd1_vqmmc: regulator-sdhci1-vqmmc {
···
514
514
pinctrl-single,pins = <
515
515
AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */
516
516
AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */
517
-
AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
517
+
AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */
518
518
AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */
519
519
AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */
520
520
AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */
+1
arch/arm64/boot/dts/ti/k3-am62p.dtsi
+1
arch/arm64/boot/dts/ti/k3-am62p.dtsi
···
96
96
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
97
97
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
98
98
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
99
+
<0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
99
100
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
100
101
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
101
102
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
+1
-1
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+1
-1
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
···
283
283
pinctrl-single,pins = <
284
284
AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */
285
285
AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */
286
-
AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
286
+
AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */
287
287
AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */
288
288
AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
289
289
AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
+2
-2
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
+2
-2
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
···
224
224
status = "okay";
225
225
};
226
226
227
-
&main_i2c0{
227
+
&main_i2c0 {
228
228
pinctrl-names = "default";
229
229
pinctrl-0 = <&pinctrl_i2c0>;
230
230
clock-frequency = <400000>;
···
466
466
pinctrl-0 = <&pinctrl_mmc1>;
467
467
disable-wp;
468
468
bootph-all;
469
-
status="okay";
469
+
status = "okay";
470
470
};
471
471
472
472
&ti_csi2rx0 {
+9
-9
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+9
-9
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
···
84
84
#interrupt-cells = <3>;
85
85
interrupt-controller;
86
86
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
87
-
<0x00 0x01840000 0x00 0xC0000>, /* GICR */
87
+
<0x00 0x01840000 0x00 0xc0000>, /* GICR */
88
88
<0x01 0x00000000 0x00 0x2000>, /* GICC */
89
89
<0x01 0x00010000 0x00 0x1000>, /* GICH */
90
90
<0x01 0x00020000 0x00 0x2000>; /* GICV */
···
685
685
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
686
686
status = "disabled";
687
687
688
-
dmas = <&main_pktdma 0xC500 15>,
689
-
<&main_pktdma 0xC501 15>,
690
-
<&main_pktdma 0xC502 15>,
691
-
<&main_pktdma 0xC503 15>,
692
-
<&main_pktdma 0xC504 15>,
693
-
<&main_pktdma 0xC505 15>,
694
-
<&main_pktdma 0xC506 15>,
695
-
<&main_pktdma 0xC507 15>,
688
+
dmas = <&main_pktdma 0xc500 15>,
689
+
<&main_pktdma 0xc501 15>,
690
+
<&main_pktdma 0xc502 15>,
691
+
<&main_pktdma 0xc503 15>,
692
+
<&main_pktdma 0xc504 15>,
693
+
<&main_pktdma 0xc505 15>,
694
+
<&main_pktdma 0xc506 15>,
695
+
<&main_pktdma 0xc507 15>,
696
696
<&main_pktdma 0x4500 15>;
697
697
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
698
698
"tx7", "rx";
+2
-5
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
+2
-5
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
···
30
30
<&main_pktdma 0xc206 15>, /* egress slice 1 */
31
31
<&main_pktdma 0xc207 15>, /* egress slice 1 */
32
32
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
33
-
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
34
-
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
35
-
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
33
+
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
36
34
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
37
35
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
38
-
"rx0", "rx1",
39
-
"rxmgm0", "rxmgm1";
36
+
"rx0", "rx1";
40
37
41
38
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
42
39
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+3
-3
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+3
-3
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
···
206
206
pinctrl-single,pins = <
207
207
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
208
208
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
209
-
AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
210
-
AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
209
+
AM64X_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
210
+
AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
211
211
>;
212
212
};
213
213
···
300
300
main_uart1_pins_default: main-uart1-default-pins {
301
301
pinctrl-single,pins = <
302
302
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
303
-
AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
303
+
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
304
304
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
305
305
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
306
306
>;
+6
-6
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso
+6
-6
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso
···
20
20
};
21
21
22
22
&main_pmx0 {
23
-
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default {
23
+
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-default-pins {
24
24
pinctrl-single,pins = <
25
25
AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
26
26
>;
27
27
};
28
28
29
-
main_spi1_pins_default: main-spi1-pins-default {
29
+
main_spi1_pins_default: main-spi1-default-pins {
30
30
pinctrl-single,pins = <
31
31
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
32
-
AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
32
+
AM64X_IOPAD(0x021c, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
33
33
AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */
34
-
AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */
34
+
AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */
35
35
>;
36
36
};
37
37
38
-
main_uart3_pins_default: main-uart3-pins-default {
38
+
main_uart3_pins_default: main-uart3-default-pins {
39
39
pinctrl-single,pins = <
40
40
AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
41
41
AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
···
52
52
&main_spi1 {
53
53
pinctrl-names = "default";
54
54
pinctrl-0 = <&main_spi1_pins_default>;
55
-
ti,pindir-d0-out-d1-in = <1>;
55
+
ti,pindir-d0-out-d1-in;
56
56
status = "okay";
57
57
};
58
58
+29
-29
arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi
+29
-29
arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi
···
138
138
d2_uart0_ctsn: d2-uart0-ctsn-pins {
139
139
pinctrl-single,pins = <
140
140
/* (P1) MCU_UART0_CTSn */
141
-
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
141
+
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4)
142
142
>;
143
143
};
144
144
145
145
d2_gpio: d2-gpio-pins {
146
146
pinctrl-single,pins = <
147
147
/* (P5) WKUP_GPIO0_31 */
148
-
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
148
+
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7)
149
149
>;
150
150
};
151
151
152
152
d2_gpio_pullup: d2-gpio-pullup-pins {
153
153
pinctrl-single,pins = <
154
154
/* (P5) WKUP_GPIO0_31 */
155
-
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
155
+
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7)
156
156
>;
157
157
};
158
158
159
159
d2_gpio_pulldown: d2-gpio-pulldown-pins {
160
160
pinctrl-single,pins = <
161
161
/* (P5) WKUP_GPIO0_31 */
162
-
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
162
+
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT_PULLDOWN, 7)
163
163
>;
164
164
};
165
165
···
348
348
a2_gpio: a2-gpio-pins {
349
349
pinctrl-single,pins = <
350
350
/* (L5) WKUP_GPIO0_43 */
351
-
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
351
+
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7)
352
352
>;
353
353
};
354
354
355
355
a2_gpio_pullup: a2-gpio-pullup-pins {
356
356
pinctrl-single,pins = <
357
357
/* (L5) WKUP_GPIO0_43 */
358
-
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
358
+
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7)
359
359
>;
360
360
};
361
361
362
362
a2_gpio_pulldown: a2-gpio-pulldown-pins {
363
363
pinctrl-single,pins = <
364
364
/* (L5) WKUP_GPIO0_43 */
365
-
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
365
+
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT_PULLDOWN, 7)
366
366
>;
367
367
};
368
368
369
369
a3_gpio: a3-gpio-pins {
370
370
pinctrl-single,pins = <
371
371
/* (M5) WKUP_GPIO0_39 */
372
-
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
372
+
AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7)
373
373
>;
374
374
};
375
375
376
376
a3_gpio_pullup: a3-gpio-pullup-pins {
377
377
pinctrl-single,pins = <
378
378
/* (M5) WKUP_GPIO0_39 */
379
-
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
379
+
AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7)
380
380
>;
381
381
};
382
382
383
383
a3_gpio_pulldown: a3-gpio-pulldown-pins {
384
384
pinctrl-single,pins = <
385
385
/* (M5) WKUP_GPIO0_39 */
386
-
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
386
+
AM65X_WKUP_IOPAD(0x006c, PIN_INPUT_PULLDOWN, 7)
387
387
>;
388
388
};
389
389
···
411
411
a5_gpio: a5-gpio-pins {
412
412
pinctrl-single,pins = <
413
413
/* (N5) WKUP_GPIO0_35 */
414
-
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
414
+
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 7)
415
415
>;
416
416
};
417
417
418
418
a5_gpio_pullup: a5-gpio-pullup-pins {
419
419
pinctrl-single,pins = <
420
420
/* (N5) WKUP_GPIO0_35 */
421
-
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
421
+
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLUP, 7)
422
422
>;
423
423
};
424
424
425
425
a5_gpio_pulldown: a5-gpio-pulldown-pins {
426
426
pinctrl-single,pins = <
427
427
/* (N5) WKUP_GPIO0_35 */
428
-
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
428
+
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLDOWN, 7)
429
429
>;
430
430
};
431
431
···
533
533
d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
534
534
pinctrl-single,pins = <
535
535
/* (AF17) EHRPWM1_A */
536
-
AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
536
+
AM65X_IOPAD(0x008c, PIN_OUTPUT, 5)
537
537
>;
538
538
};
539
539
540
540
d5_gpio: d5-gpio-pins {
541
541
pinctrl-single,pins = <
542
542
/* (AF17) GPIO0_35 */
543
-
AM65X_IOPAD(0x008C, PIN_INPUT, 7)
543
+
AM65X_IOPAD(0x008c, PIN_INPUT, 7)
544
544
>;
545
545
};
546
546
547
547
d5_gpio_pullup: d5-gpio-pullup-pins {
548
548
pinctrl-single,pins = <
549
549
/* (AF17) GPIO0_35 */
550
-
AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
550
+
AM65X_IOPAD(0x008c, PIN_INPUT_PULLUP, 7)
551
551
>;
552
552
};
553
553
554
554
d5_gpio_pulldown: d5-gpio-pulldown-pins {
555
555
pinctrl-single,pins = <
556
556
/* (AF17) GPIO0_35 */
557
-
AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
557
+
AM65X_IOPAD(0x008c, PIN_INPUT_PULLDOWN, 7)
558
558
>;
559
559
};
560
560
···
589
589
d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
590
590
pinctrl-single,pins = <
591
591
/* (AH15) EHRPWM3_A */
592
-
AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
592
+
AM65X_IOPAD(0x00ac, PIN_OUTPUT, 5)
593
593
>;
594
594
};
595
595
596
596
d7_gpio: d7-gpio-pins {
597
597
pinctrl-single,pins = <
598
598
/* (AH15) GPIO0_43 */
599
-
AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
599
+
AM65X_IOPAD(0x00ac, PIN_INPUT, 7)
600
600
>;
601
601
};
602
602
603
603
d7_gpio_pullup: d7-gpio-pullup-pins {
604
604
pinctrl-single,pins = <
605
605
/* (AH15) GPIO0_43 */
606
-
AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
606
+
AM65X_IOPAD(0x00ac, PIN_INPUT_PULLUP, 7)
607
607
>;
608
608
};
609
609
610
610
d7_gpio_pulldown: d7-gpio-pulldown-pins {
611
611
pinctrl-single,pins = <
612
612
/* (AH15) GPIO0_43 */
613
-
AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
613
+
AM65X_IOPAD(0x00ac, PIN_INPUT_PULLDOWN, 7)
614
614
>;
615
615
};
616
616
617
617
d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
618
618
pinctrl-single,pins = <
619
619
/* (AG15) EHRPWM4_A */
620
-
AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
620
+
AM65X_IOPAD(0x00c0, PIN_OUTPUT, 5)
621
621
>;
622
622
};
623
623
624
624
d8_gpio: d8-gpio-pins {
625
625
pinctrl-single,pins = <
626
626
/* (AG15) GPIO0_48 */
627
-
AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
627
+
AM65X_IOPAD(0x00c0, PIN_INPUT, 7)
628
628
>;
629
629
};
630
630
631
631
d8_gpio_pullup: d8-gpio-pullup-pins {
632
632
pinctrl-single,pins = <
633
633
/* (AG15) GPIO0_48 */
634
-
AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
634
+
AM65X_IOPAD(0x00c0, PIN_INPUT_PULLUP, 7)
635
635
>;
636
636
};
637
637
638
638
d8_gpio_pulldown: d8-gpio-pulldown-pins {
639
639
pinctrl-single,pins = <
640
640
/* (AG15) GPIO0_48 */
641
-
AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
641
+
AM65X_IOPAD(0x00c0, PIN_INPUT_PULLDOWN, 7)
642
642
>;
643
643
};
644
644
645
645
d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
646
646
pinctrl-single,pins = <
647
647
/* (AD15) EHRPWM5_A */
648
-
AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
648
+
AM65X_IOPAD(0x00cc, PIN_OUTPUT, 5)
649
649
>;
650
650
};
651
651
652
652
d9_gpio: d9-gpio-pins {
653
653
pinctrl-single,pins = <
654
654
/* (AD15) GPIO0_51 */
655
-
AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
655
+
AM65X_IOPAD(0x00cc, PIN_INPUT, 7)
656
656
>;
657
657
};
658
658
659
659
d9_gpio_pullup: d9-gpio-pullup-pins {
660
660
pinctrl-single,pins = <
661
661
/* (AD15) GPIO0_51 */
662
-
AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
662
+
AM65X_IOPAD(0x00cc, PIN_INPUT_PULLUP, 7)
663
663
>;
664
664
};
665
665
666
666
d9_gpio_pulldown: d9-gpio-pulldown-pins {
667
667
pinctrl-single,pins = <
668
668
/* (AD15) GPIO0_51 */
669
-
AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
669
+
AM65X_IOPAD(0x00cc, PIN_INPUT_PULLDOWN, 7)
670
670
>;
671
671
};
672
672
};
+1
-1
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+1
-1
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
···
884
884
#address-cells = <3>;
885
885
#size-cells = <2>;
886
886
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
887
-
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
887
+
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07fd0000>;
888
888
ti,syscon-pcie-id = <&scm_conf 0x210>;
889
889
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
890
890
bus-range = <0x0 0xff>;
···
905
905
#address-cells = <3>;
906
906
#size-cells = <2>;
907
907
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
908
-
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
908
+
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07fd0000>;
909
909
ti,syscon-pcie-id = <&scm_conf 0x210>;
910
910
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
911
911
bus-range = <0x0 0xff>;
+1
-1
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+1
-1
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
···
190
190
pinctrl-single,pins = <
191
191
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
192
192
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
193
-
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
193
+
AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
194
194
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
195
195
>;
196
196
bootph-all;
+2
-2
arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
+2
-2
arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts
···
85
85
linux,cma {
86
86
compatible = "shared-dma-pool";
87
87
reusable;
88
-
size = <0x10000000>;
89
-
alignment = <0x2000>;
88
+
size = <0x00 0x10000000>;
90
89
linux,cma-default;
91
90
};
92
91
···
173
174
regulator-max-microvolt = <3300000>;
174
175
vin-supply = <&vcc_3p3_s0>;
175
176
regulator-boot-on;
177
+
enable-active-high;
176
178
enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>;
177
179
gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
178
180
states = <3300000 0x0>,
+7
-7
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+7
-7
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
···
359
359
360
360
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
361
361
pinctrl-single,pins = <
362
-
J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
362
+
J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
363
363
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
364
364
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
365
365
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
366
-
J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
366
+
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
367
367
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
368
368
J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
369
369
J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
370
-
J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
370
+
J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
371
371
J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
372
372
J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
373
373
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
···
392
392
393
393
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
394
394
pinctrl-single,pins = <
395
-
J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
395
+
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
396
396
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
397
397
>;
398
398
};
···
422
422
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
423
423
pinctrl-single,pins = <
424
424
J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
425
-
J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
425
+
J721S2_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
426
426
J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
427
427
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
428
428
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
429
-
J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
429
+
J721S2_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
430
430
J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
431
-
J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
431
+
J721S2_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
432
432
J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
433
433
>;
434
434
};
+4
-3
arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts
+4
-3
arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts
···
208
208
pinctrl-0 = <&pinctrl_main_spi2>,
209
209
<&pinctrl_main_spi2_cs0>,
210
210
<&pinctrl_gpio_05>;
211
-
cs-gpios = <0>, <&wkup_gpio0 29 GPIO_ACTIVE_LOW>;
211
+
cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>,
212
+
<&wkup_gpio0 29 GPIO_ACTIVE_LOW>;
212
213
status = "okay";
213
214
214
215
tpm@1 {
···
281
280
try-power-role = "sink";
282
281
self-powered;
283
282
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
284
-
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
285
-
op-sink-microwatt = <1000000>;
283
+
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
284
+
op-sink-microwatt = <0>;
286
285
287
286
ports {
288
287
#address-cells = <1>;
+2
-2
arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts
+2
-2
arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts
···
399
399
try-power-role = "sink";
400
400
self-powered;
401
401
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
402
-
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
403
-
op-sink-microwatt = <1000000>;
402
+
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
403
+
op-sink-microwatt = <0>;
404
404
405
405
ports {
406
406
#address-cells = <1>;
+4
-2
arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi
+4
-2
arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi
···
479
479
/* Aquila SPI_2 CS */
480
480
pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins {
481
481
pinctrl-single,pins = <
482
-
J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */
482
+
J784S4_IOPAD(0x0cc, PIN_OUTPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ /* AQUILA D16 */
483
483
>;
484
484
};
485
485
···
495
495
/* Aquila SPI_1 CS */
496
496
pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins {
497
497
pinctrl-single,pins = <
498
-
J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */
498
+
J784S4_IOPAD(0x09c, PIN_OUTPUT, 7) /* (AF35) MCASP0_AXR11.GPIO0_39 */ /* AQUILA D9 */
499
499
>;
500
500
};
501
501
···
1204
1204
&main_spi0 {
1205
1205
pinctrl-names = "default";
1206
1206
pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>;
1207
+
cs-gpios = <&main_gpio0 51 GPIO_ACTIVE_LOW>;
1207
1208
status = "disabled";
1208
1209
};
1209
1210
···
1212
1211
&main_spi2 {
1213
1212
pinctrl-names = "default";
1214
1213
pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>;
1214
+
cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>;
1215
1215
status = "disabled";
1216
1216
};
1217
1217
+13
-13
arch/arm64/boot/dts/ti/k3-am69-sk.dts
+13
-13
arch/arm64/boot/dts/ti/k3-am69-sk.dts
···
264
264
265
265
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
266
266
pinctrl-single,pins = <
267
-
J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
267
+
J784S4_IOPAD(0x0c4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
268
268
>;
269
269
};
270
270
271
271
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
272
272
pinctrl-single,pins = <
273
-
J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
274
-
J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
275
-
J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
276
-
J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
277
-
J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
278
-
J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
273
+
J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
274
+
J784S4_IOPAD(0x06c, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
275
+
J784S4_IOPAD(0x0b4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
276
+
J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
277
+
J784S4_IOPAD(0x00c, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
278
+
J784S4_IOPAD(0x0b8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
279
279
J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
280
-
J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
281
-
J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
280
+
J784S4_IOPAD(0x0a8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
281
+
J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
282
282
J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
283
-
J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
284
-
J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
283
+
J784S4_IOPAD(0x0cc, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
284
+
J784S4_IOPAD(0x08c, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
285
285
J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
286
286
J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
287
287
>;
···
347
347
348
348
main_mcan7_pins_default: main-mcan7-default-pins {
349
349
pinctrl-single,pins = <
350
-
J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
351
-
J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
350
+
J784S4_IOPAD(0x0a0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */
351
+
J784S4_IOPAD(0x09c, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */
352
352
>;
353
353
};
354
354
+2
-2
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
···
212
212
reg = <0x0 0x40f04200 0x0 0x28>;
213
213
#pinctrl-cells = <1>;
214
214
pinctrl-single,register-width = <32>;
215
-
pinctrl-single,function-mask = <0x0000000F>;
215
+
pinctrl-single,function-mask = <0x0000000f>;
216
216
status = "reserved";
217
217
};
218
218
···
222
222
reg = <0x0 0x40f04280 0x0 0x28>;
223
223
#pinctrl-cells = <1>;
224
224
pinctrl-single,register-width = <32>;
225
-
pinctrl-single,function-mask = <0x0000000F>;
225
+
pinctrl-single,function-mask = <0x0000000f>;
226
226
status = "reserved";
227
227
};
228
228
+12
-12
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+12
-12
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
···
443
443
444
444
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
445
445
pinctrl-single,pins = <
446
-
J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
446
+
J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
447
447
J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
448
-
J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
449
-
J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
448
+
J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
449
+
J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
450
450
J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
451
-
J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
452
-
J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
451
+
J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
452
+
J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
453
453
J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
454
-
J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
455
-
J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
454
+
J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
455
+
J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
456
456
J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
457
457
J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
458
458
J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
459
459
J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
460
-
J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
461
-
J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
460
+
J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
461
+
J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
462
462
J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
463
-
J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
463
+
J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
464
464
J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
465
465
J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
466
-
J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
466
+
J721E_IOPAD(0x17c, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
467
467
J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
468
-
J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
468
+
J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
469
469
>;
470
470
};
471
471
+2
-2
arch/arm64/boot/dts/ti/k3-j721e.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-j721e.dtsi
···
41
41
reg = <0x000>;
42
42
device_type = "cpu";
43
43
enable-method = "psci";
44
-
i-cache-size = <0xC000>;
44
+
i-cache-size = <0xc000>;
45
45
i-cache-line-size = <64>;
46
46
i-cache-sets = <256>;
47
47
d-cache-size = <0x8000>;
···
55
55
reg = <0x001>;
56
56
device_type = "cpu";
57
57
enable-method = "psci";
58
-
i-cache-size = <0xC000>;
58
+
i-cache-size = <0xc000>;
59
59
i-cache-line-size = <64>;
60
60
i-cache-sets = <256>;
61
61
d-cache-size = <0x8000>;
+18
-1
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+18
-1
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
···
87
87
wkup_pmx1: pinctrl@4301c038 {
88
88
compatible = "pinctrl-single";
89
89
/* Proxy 0 addressing */
90
-
reg = <0x00 0x4301c038 0x00 0x02C>;
90
+
reg = <0x00 0x4301c038 0x00 0x02c>;
91
91
#pinctrl-cells = <1>;
92
92
pinctrl-single,register-width = <32>;
93
93
pinctrl-single,function-mask = <0xffffffff>;
···
764
764
assigned-clocks = <&k3_clks 296 1>;
765
765
assigned-clock-parents = <&k3_clks 296 5>;
766
766
/* reserved for MCU_R5F0_1 */
767
+
status = "reserved";
768
+
};
769
+
770
+
hsm: remoteproc@43c00000 {
771
+
compatible = "ti,hsm-m4fss";
772
+
/* contiguous regions but instantiated separately in HW */
773
+
reg = <0x00 0x43c00000 0x00 0x20000>,
774
+
<0x00 0x43c20000 0x00 0x10000>,
775
+
<0x00 0x43c30000 0x00 0x10000>;
776
+
reg-names = "sram0_0", "sram0_1", "sram1";
777
+
resets = <&k3_reset 304 1>;
778
+
firmware-name = "j721s2-hsm-m4f-fw";
779
+
bootph-pre-ram;
780
+
ti,sci = <&sms>;
781
+
ti,sci-dev-id = <304>;
782
+
ti,sci-proc-ids = <0x80 0xff>;
783
+
/* reserved for early-stage bootloader */
767
784
status = "reserved";
768
785
};
769
786
};
+1
-1
arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+1
-1
arch/arm64/boot/dts/ti/k3-j722s-evm.dts
···
436
436
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
437
437
pinctrl-single,pins = <
438
438
J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */
439
-
J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
439
+
J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */
440
440
>;
441
441
};
442
442
+5
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+5
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+2
-1
arch/arm64/boot/dts/ti/k3-j722s.dtsi
+2
-1
arch/arm64/boot/dts/ti/k3-j722s.dtsi
···
162
162
<0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
163
163
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
164
164
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
165
-
<0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
165
+
<0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */
166
166
<0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
167
167
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
168
168
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
···
173
173
<0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
174
174
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
175
175
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
176
+
<0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */
176
177
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
177
178
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
178
179
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
+4
arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi
+4
arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
+2
-2
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
···
509
509
J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
510
510
J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
511
511
J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
512
-
J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
512
+
J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
513
513
J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
514
514
J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
515
-
J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
515
+
J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
516
516
>;
517
517
};
518
518
};
-36
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
-36
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
···
2378
2378
assigned-clock-parents = <&k3_clks 351 4>;
2379
2379
};
2380
2380
2381
-
watchdog4: watchdog@2240000 {
2382
-
compatible = "ti,j7-rti-wdt";
2383
-
reg = <0x00 0x2240000 0x00 0x100>;
2384
-
clocks = <&k3_clks 352 0>;
2385
-
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
2386
-
assigned-clocks = <&k3_clks 352 0>;
2387
-
assigned-clock-parents = <&k3_clks 352 4>;
2388
-
};
2389
-
2390
-
watchdog5: watchdog@2250000 {
2391
-
compatible = "ti,j7-rti-wdt";
2392
-
reg = <0x00 0x2250000 0x00 0x100>;
2393
-
clocks = <&k3_clks 353 0>;
2394
-
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
2395
-
assigned-clocks = <&k3_clks 353 0>;
2396
-
assigned-clock-parents = <&k3_clks 353 4>;
2397
-
};
2398
-
2399
-
watchdog6: watchdog@2260000 {
2400
-
compatible = "ti,j7-rti-wdt";
2401
-
reg = <0x00 0x2260000 0x00 0x100>;
2402
-
clocks = <&k3_clks 354 0>;
2403
-
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
2404
-
assigned-clocks = <&k3_clks 354 0>;
2405
-
assigned-clock-parents = <&k3_clks 354 4>;
2406
-
};
2407
-
2408
-
watchdog7: watchdog@2270000 {
2409
-
compatible = "ti,j7-rti-wdt";
2410
-
reg = <0x00 0x2270000 0x00 0x100>;
2411
-
clocks = <&k3_clks 355 0>;
2412
-
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
2413
-
assigned-clocks = <&k3_clks 355 0>;
2414
-
assigned-clock-parents = <&k3_clks 355 4>;
2415
-
};
2416
-
2417
2381
/*
2418
2382
* The following RTI instances are coupled with MCU R5Fs, c7x and
2419
2383
* GPU so keeping them reserved as these will be used by their
+17
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
+17
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
···
762
762
/* reserved for MCU_R5F0_1 */
763
763
status = "reserved";
764
764
};
765
+
766
+
hsm: remoteproc@43c00000 {
767
+
compatible = "ti,hsm-m4fss";
768
+
/* contiguous regions but instantiated separately in HW */
769
+
reg = <0x00 0x43c00000 0x00 0x20000>,
770
+
<0x00 0x43c20000 0x00 0x10000>,
771
+
<0x00 0x43c30000 0x00 0x10000>;
772
+
reg-names = "sram0_0", "sram0_1", "sram1";
773
+
resets = <&k3_reset 371 1>;
774
+
firmware-name = "j784s4-hsm-m4f-fw";
775
+
bootph-pre-ram;
776
+
ti,sci = <&sms>;
777
+
ti,sci-dev-id = <371>;
778
+
ti,sci-proc-ids = <0x80 0xff>;
779
+
/* reserved for early-stage bootloader */
780
+
status = "reserved";
781
+
};
765
782
};
+47
-11
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+47
-11
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
···
6
6
*/
7
7
8
8
&cbass_main {
9
-
c71_3: dsp@67800000 {
10
-
compatible = "ti,j721s2-c71-dsp";
11
-
reg = <0x00 0x67800000 0x00 0x00080000>,
12
-
<0x00 0x67e00000 0x00 0x0000c000>;
13
-
reg-names = "l2sram", "l1dram";
14
-
resets = <&k3_reset 40 1>;
15
-
firmware-name = "j784s4-c71_3-fw";
16
-
ti,sci = <&sms>;
17
-
ti,sci-dev-id = <40>;
18
-
ti,sci-proc-ids = <0x33 0xff>;
19
-
status = "disabled";
9
+
watchdog4: watchdog@2240000 {
10
+
compatible = "ti,j7-rti-wdt";
11
+
reg = <0x00 0x2240000 0x00 0x100>;
12
+
clocks = <&k3_clks 352 0>;
13
+
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
14
+
assigned-clocks = <&k3_clks 352 0>;
15
+
assigned-clock-parents = <&k3_clks 352 4>;
16
+
};
17
+
18
+
watchdog5: watchdog@2250000 {
19
+
compatible = "ti,j7-rti-wdt";
20
+
reg = <0x00 0x2250000 0x00 0x100>;
21
+
clocks = <&k3_clks 353 0>;
22
+
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
23
+
assigned-clocks = <&k3_clks 353 0>;
24
+
assigned-clock-parents = <&k3_clks 353 4>;
25
+
};
26
+
27
+
watchdog6: watchdog@2260000 {
28
+
compatible = "ti,j7-rti-wdt";
29
+
reg = <0x00 0x2260000 0x00 0x100>;
30
+
clocks = <&k3_clks 354 0>;
31
+
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
32
+
assigned-clocks = <&k3_clks 354 0>;
33
+
assigned-clock-parents = <&k3_clks 354 4>;
34
+
};
35
+
36
+
watchdog7: watchdog@2270000 {
37
+
compatible = "ti,j7-rti-wdt";
38
+
reg = <0x00 0x2270000 0x00 0x100>;
39
+
clocks = <&k3_clks 355 0>;
40
+
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
41
+
assigned-clocks = <&k3_clks 355 0>;
42
+
assigned-clock-parents = <&k3_clks 355 4>;
20
43
};
21
44
22
45
pcie2_rc: pcie@2920000 {
···
135
112
#clock-cells = <1>;
136
113
status = "disabled";
137
114
};
115
+
};
116
+
117
+
c71_3: dsp@67800000 {
118
+
compatible = "ti,j721s2-c71-dsp";
119
+
reg = <0x00 0x67800000 0x00 0x00080000>,
120
+
<0x00 0x67e00000 0x00 0x0000c000>;
121
+
reg-names = "l2sram", "l1dram";
122
+
resets = <&k3_reset 40 1>;
123
+
firmware-name = "j784s4-c71_3-fw";
124
+
ti,sci = <&sms>;
125
+
ti,sci-dev-id = <40>;
126
+
ti,sci-proc-ids = <0x33 0xff>;
127
+
status = "disabled";
138
128
};
139
129
};
140
130