Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.20 (or v7.0)
Anlogic:
Minor change to the extension information, to add the "b" extension
that's a catch-all for 3 of the extensions already in the dts.
Starfive:
Append the jh7110 compatible to jh7110s devicetrees, as that will enable
OpenSBI etc to run without adding support for this minor variant. The
"s" device differs from the non "s" device only in
thermal limits and voltage/frequency characteristics.
Microchip:
Redo the mpfs clock setup yet again, to something approaching correct.
The original binding conjured up for the platform was wildly inaccurate,
and even with the original improvements, a bigger change to using
syscons was required to support several peripherals that also inhabit
the memory regions that the clocks lie in. The damage to the dts isn't
that bad in the end, and of course the whole thing has been done in a
backwards compatible manner, with the code changes being merged a cycle
or two ago in the kernel and like a year ago in U-Boot (the only other
user that I am aware of).
Generic:
Additions to extensions.yaml, mainly for things in the "rva23" profile
that appear for the first time on the Spacemit K3 SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: anlogic: dr1v90: Add "b" ISA extension
dt-bindings: riscv: extensions: Drop unnecessary select schema
dt-bindings: riscv: Add Sha and its comprised extensions
dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl
dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm
dt-bindings: riscv: Add B ISA extension description
dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt
riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board
riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
riscv: dts: microchip: convert clock and reset to use syscon
riscv: dts: microchip: fix mailbox description
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+210
-28
+180
-14
Documentation/devicetree/bindings/riscv/extensions.yaml
+180
-14
Documentation/devicetree/bindings/riscv/extensions.yaml
···
24
24
ratified states, with the exception of the I, Zicntr & Zihpm extensions.
25
25
See the "i" property for more information.
26
26
27
-
select:
28
-
properties:
29
-
compatible:
30
-
contains:
31
-
const: riscv
32
-
33
27
properties:
34
28
riscv,isa:
35
29
description:
···
103
109
The standard C extension for compressed instructions, as ratified in
104
110
the 20191213 version of the unprivileged ISA specification.
105
111
112
+
- const: b
113
+
description:
114
+
The standard B extension for bit manipulation instructions, as
115
+
ratified in the 20240411 version of the unprivileged ISA
116
+
specification. The B standard extension comprises instructions
117
+
provided by the Zba, Zbb, and Zbs extensions.
118
+
106
119
- const: v
107
120
description:
108
121
The standard V extension for vector operations, as ratified
···
118
117
119
118
- const: h
120
119
description:
121
-
The standard H extension for hypervisors as ratified in the 20191213
122
-
version of the privileged ISA specification.
120
+
The standard H extension for hypervisors as ratified in the RISC-V
121
+
Instruction Set Manual, Volume II Privileged Architecture,
122
+
Document Version 20211203.
123
123
124
124
# multi-letter extensions, sorted alphanumerically
125
+
- const: sha
126
+
description: |
127
+
The standard Sha extension for augmented hypervisor extension as
128
+
ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6
129
+
("rva23/rvb23 ratified").
130
+
131
+
Sha captures the full set of features that are mandated to be
132
+
supported along with the H extension. Sha comprises the following
133
+
extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
134
+
Shvstvecd, and Ssstateen.
135
+
136
+
- const: shcounterenw
137
+
description: |
138
+
The standard Shcounterenw extension for support writable enables
139
+
in hcounteren for any supported counter, as ratified in RISC-V
140
+
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
141
+
ratified state.")
142
+
143
+
- const: shgatpa
144
+
description: |
145
+
The standard Shgatpa extension indicates that for each supported
146
+
virtual memory scheme SvNN supported in satp, the corresponding
147
+
hgatp SvNNx4 mode must be supported. The hgatp mode Bare must
148
+
also be supported. It is ratified in RISC-V Profiles Version 1.0,
149
+
with commit b1d806605f87 ("Updated to ratified state.")
150
+
151
+
- const: shtvala
152
+
description: |
153
+
The standard Shtvala extension for htval be written with the
154
+
faulting guest physical address in all circumstances permitted by
155
+
the ISA. It is ratified in RISC-V Profiles Version 1.0, with
156
+
commit b1d806605f87 ("Updated to ratified state.")
157
+
158
+
- const: shvsatpa
159
+
description: |
160
+
The standard Shvsatpa extension for vsatp supporting all translation
161
+
modes supported in satp, as ratified in RISC-V Profiles Version 1.0,
162
+
with commit b1d806605f87 ("Updated to ratified state.")
163
+
164
+
- const: shvstvala
165
+
description: |
166
+
The standard Shvstvala extension for vstval provides all needed
167
+
values as ratified in RISC-V Profiles Version 1.0, with commit
168
+
b1d806605f87 ("Updated to ratified state.")
169
+
170
+
- const: shvstvecd
171
+
description: |
172
+
The standard Shvstvecd extension for vstvec supporting Direct mode,
173
+
as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
174
+
("Updated to ratified state.")
175
+
125
176
- const: smaia
126
177
description: |
127
178
The standard Smaia supervisor-level extension for the advanced
···
206
153
behavioural changes to interrupts as frozen at commit ccbddab
207
154
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
208
155
156
+
- const: ssccptr
157
+
description: |
158
+
The standard Ssccptr extension for main memory (cacheability and
159
+
coherence) hardware page-table reads, as ratified in RISC-V
160
+
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
161
+
ratified state.")
162
+
209
163
- const: sscofpmf
210
164
description: |
211
165
The standard Sscofpmf supervisor-level extension for count overflow
212
166
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
213
167
to manually trigger workflow. (#2)") of riscv-count-overflow.
168
+
169
+
- const: sscounterenw
170
+
description: |
171
+
The standard Sscounterenw extension for support writable enables
172
+
in scounteren for any supported counter, as ratified in RISC-V
173
+
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
174
+
ratified state.")
214
175
215
176
- const: ssnpm
216
177
description: |
···
232
165
ratified at commit d70011dde6c2 ("Update to ratified state")
233
166
of riscv-j-extension.
234
167
168
+
- const: ssstateen
169
+
description: |
170
+
The standard Ssstateen extension for supervisor-mode view of the
171
+
state-enable extension, as ratified in RISC-V Profiles Version 1.0,
172
+
with commit b1d806605f87 ("Updated to ratified state.")
173
+
235
174
- const: sstc
236
175
description: |
237
176
The standard Sstc supervisor-level extension for time compare as
238
177
ratified at commit 3f9ed34 ("Add ability to manually trigger
239
178
workflow. (#2)") of riscv-time-compare.
179
+
180
+
- const: sstvala
181
+
description: |
182
+
The standard Sstvala extension for stval provides all needed values
183
+
as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
184
+
("Updated to ratified state.")
185
+
186
+
- const: sstvecd
187
+
description: |
188
+
The standard Sstvecd extension for stvec supports Direct mode as
189
+
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
190
+
("Updated to ratified state.")
191
+
192
+
- const: ssu64xl
193
+
description: |
194
+
The standard Ssu64xl extension for UXLEN=64 must be supported, as
195
+
ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
196
+
("Updated to ratified state.")
240
197
241
198
- const: svade
242
199
description: |
···
293
202
- const: svinval
294
203
description:
295
204
The standard Svinval supervisor-level extension for fine-grained
296
-
address-translation cache invalidation as ratified in the 20191213
297
-
version of the privileged ISA specification.
205
+
address-translation cache invalidation as ratified in the RISC-V
206
+
Instruction Set Manual, Volume II Privileged Architecture,
207
+
Document Version 20211203.
298
208
299
209
- const: svnapot
300
210
description:
301
211
The standard Svnapot supervisor-level extensions for napot
302
-
translation contiguity as ratified in the 20191213 version of the
303
-
privileged ISA specification.
212
+
translation contiguity as ratified in the RISC-V Instruction Set
213
+
Manual, Volume II Privileged Architecture, Document Version
214
+
20211203.
304
215
305
216
- const: svpbmt
306
217
description:
307
218
The standard Svpbmt supervisor-level extensions for page-based
308
-
memory types as ratified in the 20191213 version of the privileged
309
-
ISA specification.
219
+
memory types as ratified in the RISC-V Instruction Set Manual,
220
+
Volume II Privileged Architecture, Document Version 20211203.
310
221
311
222
- const: svrsw60t59b
312
223
description:
···
322
229
address-translation cache behaviour with respect to invalid entries
323
230
as ratified at commit 4a69197e5617 ("Update to ratified state") of
324
231
riscv-svvptc.
232
+
233
+
- const: za64rs
234
+
description:
235
+
The standard Za64rs extension for reservation set size of at most
236
+
64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit
237
+
b1d806605f87 ("Updated to ratified state.")
325
238
326
239
- const: zaamo
327
240
description: |
···
469
370
16-bit half-precision binary floating-point instructions, as ratified
470
371
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
471
372
riscv-isa-manual.
373
+
374
+
- const: ziccamoa
375
+
description:
376
+
The standard Ziccamoa extension for main memory (cacheability and
377
+
coherence) must support all atomics in A, as ratified in RISC-V
378
+
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
379
+
ratified state.")
380
+
381
+
- const: ziccif
382
+
description:
383
+
The standard Ziccif extension for main memory (cacheability and
384
+
coherence) instruction fetch atomicity, as ratified in RISC-V
385
+
Profiles Version 1.0, with commit b1d806605f87 ("Updated to
386
+
ratified state.")
387
+
388
+
- const: zicclsm
389
+
description:
390
+
The standard Zicclsm extension for main memory (cacheability and
391
+
coherence) must support misaligned loads and stores, as ratified
392
+
in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated
393
+
to ratified state.")
472
394
473
395
- const: ziccrse
474
396
description:
···
869
749
then:
870
750
contains:
871
751
const: f
752
+
# B comprises Zba, Zbb, and Zbs
753
+
- if:
754
+
contains:
755
+
const: b
756
+
then:
757
+
allOf:
758
+
- contains:
759
+
const: zba
760
+
- contains:
761
+
const: zbb
762
+
- contains:
763
+
const: zbs
764
+
# Zba, Zbb, Zbs together require B
765
+
- if:
766
+
allOf:
767
+
- contains:
768
+
const: zba
769
+
- contains:
770
+
const: zbb
771
+
- contains:
772
+
const: zbs
773
+
then:
774
+
contains:
775
+
const: b
776
+
# Za64rs and Ziccrse depend on Zalrsc or A
777
+
- if:
778
+
contains:
779
+
anyOf:
780
+
- const: za64rs
781
+
- const: ziccrse
782
+
then:
783
+
oneOf:
784
+
- contains:
785
+
const: zalrsc
786
+
- contains:
787
+
const: a
872
788
# Zcb depends on Zca
873
789
- if:
874
790
contains:
···
946
790
then:
947
791
contains:
948
792
const: f
793
+
# Ziccamoa depends on Zaamo or A
794
+
- if:
795
+
contains:
796
+
const: ziccamoa
797
+
then:
798
+
oneOf:
799
+
- contains:
800
+
const: zaamo
801
+
- contains:
802
+
const: a
949
803
# Zvfbfmin depends on V or Zve32f
950
804
- if:
951
805
contains:
+1
Documentation/devicetree/bindings/riscv/starfive.yaml
+1
Documentation/devicetree/bindings/riscv/starfive.yaml
+3
-2
arch/riscv/boot/dts/anlogic/dr1v90.dtsi
+3
-2
arch/riscv/boot/dts/anlogic/dr1v90.dtsi
···
27
27
mmu-type = "riscv,sv39";
28
28
reg = <0>;
29
29
riscv,isa-base = "rv64i";
30
-
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
31
-
"zbkc", "zbs", "zicntr", "zicsr", "zifencei",
30
+
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b",
31
+
"zba", "zbb", "zbc", "zbkc", "zbs",
32
+
"zicntr", "zicsr", "zifencei",
32
33
"zihintpause", "zihpm";
33
34
34
35
cpu0_intc: interrupt-controller {
+24
-10
arch/riscv/boot/dts/microchip/mpfs.dtsi
+24
-10
arch/riscv/boot/dts/microchip/mpfs.dtsi
···
251
251
#dma-cells = <1>;
252
252
};
253
253
254
-
clkcfg: clkcfg@20002000 {
255
-
compatible = "microchip,mpfs-clkcfg";
256
-
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
257
-
clocks = <&refclk>;
258
-
#clock-cells = <1>;
254
+
mss_top_sysreg: syscon@20002000 {
255
+
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
256
+
reg = <0x0 0x20002000 0x0 0x1000>;
259
257
#reset-cells = <1>;
258
+
};
259
+
260
+
sysreg_scb: syscon@20003000 {
261
+
compatible = "microchip,mpfs-sysreg-scb", "syscon";
262
+
reg = <0x0 0x20003000 0x0 0x1000>;
260
263
};
261
264
262
265
ccc_se: clock-controller@38010000 {
···
450
447
local-mac-address = [00 00 00 00 00 00];
451
448
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
452
449
clock-names = "pclk", "hclk";
453
-
resets = <&clkcfg CLK_MAC0>;
450
+
resets = <&mss_top_sysreg CLK_MAC0>;
454
451
status = "disabled";
455
452
};
456
453
···
464
461
local-mac-address = [00 00 00 00 00 00];
465
462
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
466
463
clock-names = "pclk", "hclk";
467
-
resets = <&clkcfg CLK_MAC1>;
464
+
resets = <&mss_top_sysreg CLK_MAC1>;
468
465
status = "disabled";
469
466
};
470
467
···
524
521
status = "disabled";
525
522
};
526
523
527
-
mbox: mailbox@37020000 {
524
+
control_scb: syscon@37020000 {
525
+
compatible = "microchip,mpfs-control-scb", "syscon";
526
+
reg = <0x0 0x37020000 0x0 0x100>;
527
+
};
528
+
529
+
mbox: mailbox@37020800 {
528
530
compatible = "microchip,mpfs-mailbox";
529
-
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
530
-
<0x0 0x37020800 0x0 0x100>;
531
+
reg = <0x0 0x37020800 0x0 0x1000>;
531
532
interrupt-parent = <&plic>;
532
533
interrupts = <96>;
533
534
#mbox-cells = <1>;
···
547
540
interrupts = <110>;
548
541
clocks = <&scbclk>;
549
542
status = "disabled";
543
+
};
544
+
545
+
clkcfg: clkcfg@3e001000 {
546
+
compatible = "microchip,mpfs-clkcfg";
547
+
reg = <0x0 0x3e001000 0x0 0x1000>;
548
+
clocks = <&refclk>;
549
+
#clock-cells = <1>;
550
550
};
551
551
};
552
552
};
+1
-1
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
+1
-1
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
+1
-1
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
+1
-1
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts