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perf/x86/msr: Add Tremont support

Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also
supported.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1580236279-35492-3-git-send-email-kan.liang@linux.intel.com

authored by

Kan Liang and committed by
Ingo Molnar 0aa0e0d6 ecf71fbc

+2 -1
+2 -1
arch/x86/events/msr.c
··· 75 75 76 76 case INTEL_FAM6_ATOM_GOLDMONT: 77 77 case INTEL_FAM6_ATOM_GOLDMONT_D: 78 - 79 78 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 79 + case INTEL_FAM6_ATOM_TREMONT_D: 80 + case INTEL_FAM6_ATOM_TREMONT: 80 81 81 82 case INTEL_FAM6_XEON_PHI_KNL: 82 83 case INTEL_FAM6_XEON_PHI_KNM: