Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sc8280xp: convert to dynamic IDs
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-rework-icc-v3-4-0575304c9624@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Georgi Djakov
0ab0f87d
ddf2ef52
+416
-630
+416
-421
drivers/interconnect/qcom/sc8280xp.c
+416
-421
drivers/interconnect/qcom/sc8280xp.c
···
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#include "bcm-voter.h"
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#include "icc-rpmh.h"
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-
#include "sc8280xp.h"
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static struct qcom_icc_node qhm_qspi;
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static struct qcom_icc_node qhm_qup1;
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static struct qcom_icc_node qhm_qup2;
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static struct qcom_icc_node qnm_a1noc_cfg;
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static struct qcom_icc_node qxm_ipa;
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static struct qcom_icc_node xm_emac_1;
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static struct qcom_icc_node xm_sdc4;
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static struct qcom_icc_node xm_ufs_mem;
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static struct qcom_icc_node xm_usb3_0;
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static struct qcom_icc_node xm_usb3_1;
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static struct qcom_icc_node xm_usb3_mp;
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static struct qcom_icc_node xm_usb4_host0;
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static struct qcom_icc_node xm_usb4_host1;
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static struct qcom_icc_node qhm_qdss_bam;
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static struct qcom_icc_node qhm_qup0;
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static struct qcom_icc_node qnm_a2noc_cfg;
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static struct qcom_icc_node qxm_crypto;
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static struct qcom_icc_node qxm_sensorss_q6;
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static struct qcom_icc_node qxm_sp;
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static struct qcom_icc_node xm_emac_0;
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static struct qcom_icc_node xm_pcie3_0;
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static struct qcom_icc_node xm_pcie3_1;
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static struct qcom_icc_node xm_pcie3_2a;
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static struct qcom_icc_node xm_pcie3_2b;
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static struct qcom_icc_node xm_pcie3_3a;
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static struct qcom_icc_node xm_pcie3_3b;
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static struct qcom_icc_node xm_pcie3_4;
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static struct qcom_icc_node xm_qdss_etr;
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static struct qcom_icc_node xm_sdc2;
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static struct qcom_icc_node xm_ufs_card;
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static struct qcom_icc_node qup0_core_master;
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static struct qcom_icc_node qup1_core_master;
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static struct qcom_icc_node qup2_core_master;
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static struct qcom_icc_node qnm_gemnoc_cnoc;
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static struct qcom_icc_node qnm_gemnoc_pcie;
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static struct qcom_icc_node qnm_cnoc_dc_noc;
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static struct qcom_icc_node alm_gpu_tcu;
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static struct qcom_icc_node alm_pcie_tcu;
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static struct qcom_icc_node alm_sys_tcu;
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static struct qcom_icc_node chm_apps;
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static struct qcom_icc_node qnm_cmpnoc0;
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static struct qcom_icc_node qnm_cmpnoc1;
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static struct qcom_icc_node qnm_gemnoc_cfg;
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static struct qcom_icc_node qnm_gpu;
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static struct qcom_icc_node qnm_mnoc_hf;
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static struct qcom_icc_node qnm_mnoc_sf;
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static struct qcom_icc_node qnm_pcie;
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static struct qcom_icc_node qnm_snoc_gc;
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static struct qcom_icc_node qnm_snoc_sf;
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static struct qcom_icc_node qhm_config_noc;
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static struct qcom_icc_node qxm_lpass_dsp;
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static struct qcom_icc_node llcc_mc;
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static struct qcom_icc_node qnm_camnoc_hf;
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static struct qcom_icc_node qnm_mdp0_0;
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static struct qcom_icc_node qnm_mdp0_1;
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static struct qcom_icc_node qnm_mdp1_0;
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static struct qcom_icc_node qnm_mdp1_1;
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static struct qcom_icc_node qnm_mnoc_cfg;
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static struct qcom_icc_node qnm_rot_0;
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static struct qcom_icc_node qnm_rot_1;
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static struct qcom_icc_node qnm_video0;
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static struct qcom_icc_node qnm_video1;
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static struct qcom_icc_node qnm_video_cvp;
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static struct qcom_icc_node qxm_camnoc_icp;
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static struct qcom_icc_node qxm_camnoc_sf;
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static struct qcom_icc_node qhm_nsp_noc_config;
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static struct qcom_icc_node qxm_nsp;
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static struct qcom_icc_node qhm_nspb_noc_config;
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static struct qcom_icc_node qxm_nspb;
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static struct qcom_icc_node qnm_aggre1_noc;
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static struct qcom_icc_node qnm_aggre2_noc;
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static struct qcom_icc_node qnm_aggre_usb_noc;
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static struct qcom_icc_node qnm_lpass_noc;
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static struct qcom_icc_node qnm_snoc_cfg;
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static struct qcom_icc_node qxm_pimem;
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static struct qcom_icc_node xm_gic;
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static struct qcom_icc_node qns_a1noc_snoc;
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static struct qcom_icc_node qns_aggre_usb_snoc;
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static struct qcom_icc_node srvc_aggre1_noc;
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static struct qcom_icc_node qns_a2noc_snoc;
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static struct qcom_icc_node qns_pcie_gem_noc;
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static struct qcom_icc_node srvc_aggre2_noc;
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static struct qcom_icc_node qup0_core_slave;
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static struct qcom_icc_node qup1_core_slave;
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static struct qcom_icc_node qup2_core_slave;
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static struct qcom_icc_node qhs_ahb2phy0;
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static struct qcom_icc_node qhs_ahb2phy1;
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static struct qcom_icc_node qhs_ahb2phy2;
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static struct qcom_icc_node qhs_aoss;
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static struct qcom_icc_node qhs_apss;
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static struct qcom_icc_node qhs_camera_cfg;
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static struct qcom_icc_node qhs_clk_ctl;
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static struct qcom_icc_node qhs_compute0_cfg;
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static struct qcom_icc_node qhs_compute1_cfg;
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static struct qcom_icc_node qhs_cpr_cx;
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static struct qcom_icc_node qhs_cpr_mmcx;
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static struct qcom_icc_node qhs_cpr_mx;
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static struct qcom_icc_node qhs_cpr_nspcx;
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static struct qcom_icc_node qhs_crypto0_cfg;
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static struct qcom_icc_node qhs_cx_rdpm;
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static struct qcom_icc_node qhs_dcc_cfg;
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static struct qcom_icc_node qhs_display0_cfg;
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static struct qcom_icc_node qhs_display1_cfg;
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static struct qcom_icc_node qhs_emac0_cfg;
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static struct qcom_icc_node qhs_emac1_cfg;
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static struct qcom_icc_node qhs_gpuss_cfg;
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static struct qcom_icc_node qhs_hwkm;
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static struct qcom_icc_node qhs_imem_cfg;
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static struct qcom_icc_node qhs_ipa;
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static struct qcom_icc_node qhs_ipc_router;
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static struct qcom_icc_node qhs_lpass_cfg;
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static struct qcom_icc_node qhs_mx_rdpm;
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static struct qcom_icc_node qhs_mxc_rdpm;
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static struct qcom_icc_node qhs_pcie0_cfg;
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static struct qcom_icc_node qhs_pcie1_cfg;
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static struct qcom_icc_node qhs_pcie2a_cfg;
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static struct qcom_icc_node qhs_pcie2b_cfg;
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static struct qcom_icc_node qhs_pcie3a_cfg;
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static struct qcom_icc_node qhs_pcie3b_cfg;
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static struct qcom_icc_node qhs_pcie4_cfg;
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static struct qcom_icc_node qhs_pcie_rsc_cfg;
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static struct qcom_icc_node qhs_pdm;
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static struct qcom_icc_node qhs_pimem_cfg;
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static struct qcom_icc_node qhs_pka_wrapper_cfg;
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static struct qcom_icc_node qhs_pmu_wrapper_cfg;
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static struct qcom_icc_node qhs_qdss_cfg;
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static struct qcom_icc_node qhs_qspi;
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static struct qcom_icc_node qhs_qup0;
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static struct qcom_icc_node qhs_qup1;
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static struct qcom_icc_node qhs_qup2;
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static struct qcom_icc_node qhs_sdc2;
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static struct qcom_icc_node qhs_sdc4;
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static struct qcom_icc_node qhs_security;
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static struct qcom_icc_node qhs_smmuv3_cfg;
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static struct qcom_icc_node qhs_smss_cfg;
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static struct qcom_icc_node qhs_spss_cfg;
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static struct qcom_icc_node qhs_tcsr;
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static struct qcom_icc_node qhs_tlmm;
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static struct qcom_icc_node qhs_ufs_card_cfg;
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static struct qcom_icc_node qhs_ufs_mem_cfg;
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static struct qcom_icc_node qhs_usb3_0;
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static struct qcom_icc_node qhs_usb3_1;
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static struct qcom_icc_node qhs_usb3_mp;
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static struct qcom_icc_node qhs_usb4_host_0;
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static struct qcom_icc_node qhs_usb4_host_1;
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static struct qcom_icc_node qhs_venus_cfg;
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static struct qcom_icc_node qhs_vsense_ctrl_cfg;
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static struct qcom_icc_node qhs_vsense_ctrl_r_cfg;
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static struct qcom_icc_node qns_a1_noc_cfg;
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static struct qcom_icc_node qns_a2_noc_cfg;
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static struct qcom_icc_node qns_anoc_pcie_bridge_cfg;
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static struct qcom_icc_node qns_ddrss_cfg;
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static struct qcom_icc_node qns_mnoc_cfg;
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static struct qcom_icc_node qns_snoc_cfg;
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static struct qcom_icc_node qns_snoc_sf_bridge_cfg;
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static struct qcom_icc_node qxs_imem;
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static struct qcom_icc_node qxs_pimem;
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static struct qcom_icc_node srvc_cnoc;
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static struct qcom_icc_node xs_pcie_0;
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static struct qcom_icc_node xs_pcie_1;
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static struct qcom_icc_node xs_pcie_2a;
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static struct qcom_icc_node xs_pcie_2b;
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static struct qcom_icc_node xs_pcie_3a;
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static struct qcom_icc_node xs_pcie_3b;
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static struct qcom_icc_node xs_pcie_4;
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static struct qcom_icc_node xs_qdss_stm;
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static struct qcom_icc_node xs_smss;
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static struct qcom_icc_node xs_sys_tcu_cfg;
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static struct qcom_icc_node qhs_llcc;
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static struct qcom_icc_node qns_gemnoc;
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static struct qcom_icc_node qns_gem_noc_cnoc;
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static struct qcom_icc_node qns_llcc;
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static struct qcom_icc_node qns_pcie;
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static struct qcom_icc_node srvc_even_gemnoc;
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static struct qcom_icc_node srvc_odd_gemnoc;
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static struct qcom_icc_node srvc_sys_gemnoc;
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static struct qcom_icc_node qhs_lpass_core;
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static struct qcom_icc_node qhs_lpass_lpi;
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static struct qcom_icc_node qhs_lpass_mpu;
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static struct qcom_icc_node qhs_lpass_top;
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static struct qcom_icc_node qns_sysnoc;
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static struct qcom_icc_node srvc_niu_aml_noc;
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static struct qcom_icc_node srvc_niu_lpass_agnoc;
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static struct qcom_icc_node ebi;
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static struct qcom_icc_node qns_mem_noc_hf;
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static struct qcom_icc_node qns_mem_noc_sf;
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static struct qcom_icc_node srvc_mnoc;
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static struct qcom_icc_node qns_nsp_gemnoc;
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static struct qcom_icc_node qxs_nsp_xfr;
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static struct qcom_icc_node service_nsp_noc;
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static struct qcom_icc_node qns_nspb_gemnoc;
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static struct qcom_icc_node qxs_nspb_xfr;
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static struct qcom_icc_node service_nspb_noc;
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static struct qcom_icc_node qns_gemnoc_gc;
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static struct qcom_icc_node qns_gemnoc_sf;
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static struct qcom_icc_node srvc_snoc;
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static struct qcom_icc_node qhm_qspi = {
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.name = "qhm_qspi",
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.id = SC8280XP_MASTER_QSPI_0,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_qup1 = {
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.name = "qhm_qup1",
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.id = SC8280XP_MASTER_QUP_1,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qhm_qup2 = {
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.name = "qhm_qup2",
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.id = SC8280XP_MASTER_QUP_2,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node qnm_a1noc_cfg = {
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.name = "qnm_a1noc_cfg",
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.id = SC8280XP_MASTER_A1NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_SERVICE_A1NOC },
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.link_nodes = { &srvc_aggre1_noc },
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};
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static struct qcom_icc_node qxm_ipa = {
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.name = "qxm_ipa",
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.id = SC8280XP_MASTER_IPA,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_emac_1 = {
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.name = "xm_emac_1",
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.id = SC8280XP_MASTER_EMAC_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_sdc4 = {
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.name = "xm_sdc4",
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.id = SC8280XP_MASTER_SDCC_4,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_ufs_mem = {
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.name = "xm_ufs_mem",
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.id = SC8280XP_MASTER_UFS_MEM,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A1NOC_SNOC },
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.link_nodes = { &qns_a1noc_snoc },
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};
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static struct qcom_icc_node xm_usb3_0 = {
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.name = "xm_usb3_0",
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.id = SC8280XP_MASTER_USB3_0,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_USB_NOC_SNOC },
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.link_nodes = { &qns_aggre_usb_snoc },
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};
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static struct qcom_icc_node xm_usb3_1 = {
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.name = "xm_usb3_1",
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.id = SC8280XP_MASTER_USB3_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_USB_NOC_SNOC },
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.link_nodes = { &qns_aggre_usb_snoc },
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};
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static struct qcom_icc_node xm_usb3_mp = {
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.name = "xm_usb3_mp",
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.id = SC8280XP_MASTER_USB3_MP,
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.channels = 1,
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.buswidth = 16,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_USB_NOC_SNOC },
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.link_nodes = { &qns_aggre_usb_snoc },
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};
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static struct qcom_icc_node xm_usb4_host0 = {
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.name = "xm_usb4_host0",
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.id = SC8280XP_MASTER_USB4_0,
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.channels = 1,
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.buswidth = 16,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_USB_NOC_SNOC },
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.link_nodes = { &qns_aggre_usb_snoc },
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};
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static struct qcom_icc_node xm_usb4_host1 = {
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.name = "xm_usb4_host1",
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.id = SC8280XP_MASTER_USB4_1,
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.channels = 1,
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.buswidth = 16,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_USB_NOC_SNOC },
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.link_nodes = { &qns_aggre_usb_snoc },
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};
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static struct qcom_icc_node qhm_qdss_bam = {
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.name = "qhm_qdss_bam",
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.id = SC8280XP_MASTER_QDSS_BAM,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qhm_qup0 = {
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.name = "qhm_qup0",
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.id = SC8280XP_MASTER_QUP_0,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8280XP_SLAVE_A2NOC_SNOC },
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.link_nodes = { &qns_a2noc_snoc },
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};
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static struct qcom_icc_node qnm_a2noc_cfg = {
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.name = "qnm_a2noc_cfg",
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.id = SC8280XP_MASTER_A2NOC_CFG,
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337
.channels = 1,
158
338
.buswidth = 4,
159
339
.num_links = 1,
160
-
.links = { SC8280XP_SLAVE_SERVICE_A2NOC },
340
+
.link_nodes = { &srvc_aggre2_noc },
161
341
};
162
342
163
343
static struct qcom_icc_node qxm_crypto = {
164
344
.name = "qxm_crypto",
165
-
.id = SC8280XP_MASTER_CRYPTO,
166
345
.channels = 1,
167
346
.buswidth = 8,
168
347
.num_links = 1,
169
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
348
+
.link_nodes = { &qns_a2noc_snoc },
170
349
};
171
350
172
351
static struct qcom_icc_node qxm_sensorss_q6 = {
173
352
.name = "qxm_sensorss_q6",
174
-
.id = SC8280XP_MASTER_SENSORS_PROC,
175
353
.channels = 1,
176
354
.buswidth = 8,
177
355
.num_links = 1,
178
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
356
+
.link_nodes = { &qns_a2noc_snoc },
179
357
};
180
358
181
359
static struct qcom_icc_node qxm_sp = {
182
360
.name = "qxm_sp",
183
-
.id = SC8280XP_MASTER_SP,
184
361
.channels = 1,
185
362
.buswidth = 8,
186
363
.num_links = 1,
187
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
364
+
.link_nodes = { &qns_a2noc_snoc },
188
365
};
189
366
190
367
static struct qcom_icc_node xm_emac_0 = {
191
368
.name = "xm_emac_0",
192
-
.id = SC8280XP_MASTER_EMAC,
193
369
.channels = 1,
194
370
.buswidth = 8,
195
371
.num_links = 1,
196
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
372
+
.link_nodes = { &qns_a2noc_snoc },
197
373
};
198
374
199
375
static struct qcom_icc_node xm_pcie3_0 = {
200
376
.name = "xm_pcie3_0",
201
-
.id = SC8280XP_MASTER_PCIE_0,
202
377
.channels = 1,
203
378
.buswidth = 16,
204
379
.num_links = 1,
205
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
380
+
.link_nodes = { &qns_pcie_gem_noc },
206
381
};
207
382
208
383
static struct qcom_icc_node xm_pcie3_1 = {
209
384
.name = "xm_pcie3_1",
210
-
.id = SC8280XP_MASTER_PCIE_1,
211
385
.channels = 1,
212
386
.buswidth = 16,
213
387
.num_links = 1,
214
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
388
+
.link_nodes = { &qns_pcie_gem_noc },
215
389
};
216
390
217
391
static struct qcom_icc_node xm_pcie3_2a = {
218
392
.name = "xm_pcie3_2a",
219
-
.id = SC8280XP_MASTER_PCIE_2A,
220
393
.channels = 1,
221
394
.buswidth = 16,
222
395
.num_links = 1,
223
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
396
+
.link_nodes = { &qns_pcie_gem_noc },
224
397
};
225
398
226
399
static struct qcom_icc_node xm_pcie3_2b = {
227
400
.name = "xm_pcie3_2b",
228
-
.id = SC8280XP_MASTER_PCIE_2B,
229
401
.channels = 1,
230
402
.buswidth = 8,
231
403
.num_links = 1,
232
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
404
+
.link_nodes = { &qns_pcie_gem_noc },
233
405
};
234
406
235
407
static struct qcom_icc_node xm_pcie3_3a = {
236
408
.name = "xm_pcie3_3a",
237
-
.id = SC8280XP_MASTER_PCIE_3A,
238
409
.channels = 1,
239
410
.buswidth = 16,
240
411
.num_links = 1,
241
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
412
+
.link_nodes = { &qns_pcie_gem_noc },
242
413
};
243
414
244
415
static struct qcom_icc_node xm_pcie3_3b = {
245
416
.name = "xm_pcie3_3b",
246
-
.id = SC8280XP_MASTER_PCIE_3B,
247
417
.channels = 1,
248
418
.buswidth = 8,
249
419
.num_links = 1,
250
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
420
+
.link_nodes = { &qns_pcie_gem_noc },
251
421
};
252
422
253
423
static struct qcom_icc_node xm_pcie3_4 = {
254
424
.name = "xm_pcie3_4",
255
-
.id = SC8280XP_MASTER_PCIE_4,
256
425
.channels = 1,
257
426
.buswidth = 8,
258
427
.num_links = 1,
259
-
.links = { SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC },
428
+
.link_nodes = { &qns_pcie_gem_noc },
260
429
};
261
430
262
431
static struct qcom_icc_node xm_qdss_etr = {
263
432
.name = "xm_qdss_etr",
264
-
.id = SC8280XP_MASTER_QDSS_ETR,
265
433
.channels = 1,
266
434
.buswidth = 8,
267
435
.num_links = 1,
268
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
436
+
.link_nodes = { &qns_a2noc_snoc },
269
437
};
270
438
271
439
static struct qcom_icc_node xm_sdc2 = {
272
440
.name = "xm_sdc2",
273
-
.id = SC8280XP_MASTER_SDCC_2,
274
441
.channels = 1,
275
442
.buswidth = 8,
276
443
.num_links = 1,
277
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
444
+
.link_nodes = { &qns_a2noc_snoc },
278
445
};
279
446
280
447
static struct qcom_icc_node xm_ufs_card = {
281
448
.name = "xm_ufs_card",
282
-
.id = SC8280XP_MASTER_UFS_CARD,
283
449
.channels = 1,
284
450
.buswidth = 8,
285
451
.num_links = 1,
286
-
.links = { SC8280XP_SLAVE_A2NOC_SNOC },
452
+
.link_nodes = { &qns_a2noc_snoc },
287
453
};
288
454
289
455
static struct qcom_icc_node qup0_core_master = {
290
456
.name = "qup0_core_master",
291
-
.id = SC8280XP_MASTER_QUP_CORE_0,
292
457
.channels = 1,
293
458
.buswidth = 4,
294
459
.num_links = 1,
295
-
.links = { SC8280XP_SLAVE_QUP_CORE_0 },
460
+
.link_nodes = { &qup0_core_slave },
296
461
};
297
462
298
463
static struct qcom_icc_node qup1_core_master = {
299
464
.name = "qup1_core_master",
300
-
.id = SC8280XP_MASTER_QUP_CORE_1,
301
465
.channels = 1,
302
466
.buswidth = 4,
303
467
.num_links = 1,
304
-
.links = { SC8280XP_SLAVE_QUP_CORE_1 },
468
+
.link_nodes = { &qup1_core_slave },
305
469
};
306
470
307
471
static struct qcom_icc_node qup2_core_master = {
308
472
.name = "qup2_core_master",
309
-
.id = SC8280XP_MASTER_QUP_CORE_2,
310
473
.channels = 1,
311
474
.buswidth = 4,
312
475
.num_links = 1,
313
-
.links = { SC8280XP_SLAVE_QUP_CORE_2 },
476
+
.link_nodes = { &qup2_core_slave },
314
477
};
315
478
316
479
static struct qcom_icc_node qnm_gemnoc_cnoc = {
317
480
.name = "qnm_gemnoc_cnoc",
318
-
.id = SC8280XP_MASTER_GEM_NOC_CNOC,
319
481
.channels = 1,
320
482
.buswidth = 16,
321
483
.num_links = 76,
322
-
.links = { SC8280XP_SLAVE_AHB2PHY_0,
323
-
SC8280XP_SLAVE_AHB2PHY_1,
324
-
SC8280XP_SLAVE_AHB2PHY_2,
325
-
SC8280XP_SLAVE_AOSS,
326
-
SC8280XP_SLAVE_APPSS,
327
-
SC8280XP_SLAVE_CAMERA_CFG,
328
-
SC8280XP_SLAVE_CLK_CTL,
329
-
SC8280XP_SLAVE_CDSP_CFG,
330
-
SC8280XP_SLAVE_CDSP1_CFG,
331
-
SC8280XP_SLAVE_RBCPR_CX_CFG,
332
-
SC8280XP_SLAVE_RBCPR_MMCX_CFG,
333
-
SC8280XP_SLAVE_RBCPR_MX_CFG,
334
-
SC8280XP_SLAVE_CPR_NSPCX,
335
-
SC8280XP_SLAVE_CRYPTO_0_CFG,
336
-
SC8280XP_SLAVE_CX_RDPM,
337
-
SC8280XP_SLAVE_DCC_CFG,
338
-
SC8280XP_SLAVE_DISPLAY_CFG,
339
-
SC8280XP_SLAVE_DISPLAY1_CFG,
340
-
SC8280XP_SLAVE_EMAC_CFG,
341
-
SC8280XP_SLAVE_EMAC1_CFG,
342
-
SC8280XP_SLAVE_GFX3D_CFG,
343
-
SC8280XP_SLAVE_HWKM,
344
-
SC8280XP_SLAVE_IMEM_CFG,
345
-
SC8280XP_SLAVE_IPA_CFG,
346
-
SC8280XP_SLAVE_IPC_ROUTER_CFG,
347
-
SC8280XP_SLAVE_LPASS,
348
-
SC8280XP_SLAVE_MX_RDPM,
349
-
SC8280XP_SLAVE_MXC_RDPM,
350
-
SC8280XP_SLAVE_PCIE_0_CFG,
351
-
SC8280XP_SLAVE_PCIE_1_CFG,
352
-
SC8280XP_SLAVE_PCIE_2A_CFG,
353
-
SC8280XP_SLAVE_PCIE_2B_CFG,
354
-
SC8280XP_SLAVE_PCIE_3A_CFG,
355
-
SC8280XP_SLAVE_PCIE_3B_CFG,
356
-
SC8280XP_SLAVE_PCIE_4_CFG,
357
-
SC8280XP_SLAVE_PCIE_RSC_CFG,
358
-
SC8280XP_SLAVE_PDM,
359
-
SC8280XP_SLAVE_PIMEM_CFG,
360
-
SC8280XP_SLAVE_PKA_WRAPPER_CFG,
361
-
SC8280XP_SLAVE_PMU_WRAPPER_CFG,
362
-
SC8280XP_SLAVE_QDSS_CFG,
363
-
SC8280XP_SLAVE_QSPI_0,
364
-
SC8280XP_SLAVE_QUP_0,
365
-
SC8280XP_SLAVE_QUP_1,
366
-
SC8280XP_SLAVE_QUP_2,
367
-
SC8280XP_SLAVE_SDCC_2,
368
-
SC8280XP_SLAVE_SDCC_4,
369
-
SC8280XP_SLAVE_SECURITY,
370
-
SC8280XP_SLAVE_SMMUV3_CFG,
371
-
SC8280XP_SLAVE_SMSS_CFG,
372
-
SC8280XP_SLAVE_SPSS_CFG,
373
-
SC8280XP_SLAVE_TCSR,
374
-
SC8280XP_SLAVE_TLMM,
375
-
SC8280XP_SLAVE_UFS_CARD_CFG,
376
-
SC8280XP_SLAVE_UFS_MEM_CFG,
377
-
SC8280XP_SLAVE_USB3_0,
378
-
SC8280XP_SLAVE_USB3_1,
379
-
SC8280XP_SLAVE_USB3_MP,
380
-
SC8280XP_SLAVE_USB4_0,
381
-
SC8280XP_SLAVE_USB4_1,
382
-
SC8280XP_SLAVE_VENUS_CFG,
383
-
SC8280XP_SLAVE_VSENSE_CTRL_CFG,
384
-
SC8280XP_SLAVE_VSENSE_CTRL_R_CFG,
385
-
SC8280XP_SLAVE_A1NOC_CFG,
386
-
SC8280XP_SLAVE_A2NOC_CFG,
387
-
SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG,
388
-
SC8280XP_SLAVE_DDRSS_CFG,
389
-
SC8280XP_SLAVE_CNOC_MNOC_CFG,
390
-
SC8280XP_SLAVE_SNOC_CFG,
391
-
SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG,
392
-
SC8280XP_SLAVE_IMEM,
393
-
SC8280XP_SLAVE_PIMEM,
394
-
SC8280XP_SLAVE_SERVICE_CNOC,
395
-
SC8280XP_SLAVE_QDSS_STM,
396
-
SC8280XP_SLAVE_SMSS,
397
-
SC8280XP_SLAVE_TCU
398
-
},
484
+
.link_nodes = { &qhs_ahb2phy0,
485
+
&qhs_ahb2phy1,
486
+
&qhs_ahb2phy2,
487
+
&qhs_aoss,
488
+
&qhs_apss,
489
+
&qhs_camera_cfg,
490
+
&qhs_clk_ctl,
491
+
&qhs_compute0_cfg,
492
+
&qhs_compute1_cfg,
493
+
&qhs_cpr_cx,
494
+
&qhs_cpr_mmcx,
495
+
&qhs_cpr_mx,
496
+
&qhs_cpr_nspcx,
497
+
&qhs_crypto0_cfg,
498
+
&qhs_cx_rdpm,
499
+
&qhs_dcc_cfg,
500
+
&qhs_display0_cfg,
501
+
&qhs_display1_cfg,
502
+
&qhs_emac0_cfg,
503
+
&qhs_emac1_cfg,
504
+
&qhs_gpuss_cfg,
505
+
&qhs_hwkm,
506
+
&qhs_imem_cfg,
507
+
&qhs_ipa,
508
+
&qhs_ipc_router,
509
+
&qhs_lpass_cfg,
510
+
&qhs_mx_rdpm,
511
+
&qhs_mxc_rdpm,
512
+
&qhs_pcie0_cfg,
513
+
&qhs_pcie1_cfg,
514
+
&qhs_pcie2a_cfg,
515
+
&qhs_pcie2b_cfg,
516
+
&qhs_pcie3a_cfg,
517
+
&qhs_pcie3b_cfg,
518
+
&qhs_pcie4_cfg,
519
+
&qhs_pcie_rsc_cfg,
520
+
&qhs_pdm,
521
+
&qhs_pimem_cfg,
522
+
&qhs_pka_wrapper_cfg,
523
+
&qhs_pmu_wrapper_cfg,
524
+
&qhs_qdss_cfg,
525
+
&qhs_qspi,
526
+
&qhs_qup0,
527
+
&qhs_qup1,
528
+
&qhs_qup2,
529
+
&qhs_sdc2,
530
+
&qhs_sdc4,
531
+
&qhs_security,
532
+
&qhs_smmuv3_cfg,
533
+
&qhs_smss_cfg,
534
+
&qhs_spss_cfg,
535
+
&qhs_tcsr,
536
+
&qhs_tlmm,
537
+
&qhs_ufs_card_cfg,
538
+
&qhs_ufs_mem_cfg,
539
+
&qhs_usb3_0,
540
+
&qhs_usb3_1,
541
+
&qhs_usb3_mp,
542
+
&qhs_usb4_host_0,
543
+
&qhs_usb4_host_1,
544
+
&qhs_venus_cfg,
545
+
&qhs_vsense_ctrl_cfg,
546
+
&qhs_vsense_ctrl_r_cfg,
547
+
&qns_a1_noc_cfg,
548
+
&qns_a2_noc_cfg,
549
+
&qns_anoc_pcie_bridge_cfg,
550
+
&qns_ddrss_cfg,
551
+
&qns_mnoc_cfg,
552
+
&qns_snoc_cfg,
553
+
&qns_snoc_sf_bridge_cfg,
554
+
&qxs_imem,
555
+
&qxs_pimem,
556
+
&srvc_cnoc,
557
+
&xs_qdss_stm,
558
+
&xs_smss,
559
+
&xs_sys_tcu_cfg,
560
+
NULL },
399
561
};
400
562
401
563
static struct qcom_icc_node qnm_gemnoc_pcie = {
402
564
.name = "qnm_gemnoc_pcie",
403
-
.id = SC8280XP_MASTER_GEM_NOC_PCIE_SNOC,
404
565
.channels = 1,
405
566
.buswidth = 16,
406
567
.num_links = 7,
407
-
.links = { SC8280XP_SLAVE_PCIE_0,
408
-
SC8280XP_SLAVE_PCIE_1,
409
-
SC8280XP_SLAVE_PCIE_2A,
410
-
SC8280XP_SLAVE_PCIE_2B,
411
-
SC8280XP_SLAVE_PCIE_3A,
412
-
SC8280XP_SLAVE_PCIE_3B,
413
-
SC8280XP_SLAVE_PCIE_4
414
-
},
568
+
.link_nodes = { &xs_pcie_0,
569
+
&xs_pcie_1,
570
+
&xs_pcie_2a,
571
+
&xs_pcie_2b,
572
+
&xs_pcie_3a,
573
+
&xs_pcie_3b,
574
+
&xs_pcie_4 },
415
575
};
416
576
417
577
static struct qcom_icc_node qnm_cnoc_dc_noc = {
418
578
.name = "qnm_cnoc_dc_noc",
419
-
.id = SC8280XP_MASTER_CNOC_DC_NOC,
420
579
.channels = 1,
421
580
.buswidth = 4,
422
581
.num_links = 2,
423
-
.links = { SC8280XP_SLAVE_LLCC_CFG,
424
-
SC8280XP_SLAVE_GEM_NOC_CFG
425
-
},
582
+
.link_nodes = { &qhs_llcc,
583
+
&qns_gemnoc },
426
584
};
427
585
428
586
static struct qcom_icc_node alm_gpu_tcu = {
429
587
.name = "alm_gpu_tcu",
430
-
.id = SC8280XP_MASTER_GPU_TCU,
431
588
.channels = 1,
432
589
.buswidth = 8,
433
590
.num_links = 2,
434
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
435
-
SC8280XP_SLAVE_LLCC
436
-
},
591
+
.link_nodes = { &qns_gem_noc_cnoc,
592
+
&qns_llcc },
437
593
};
438
594
439
595
static struct qcom_icc_node alm_pcie_tcu = {
440
596
.name = "alm_pcie_tcu",
441
-
.id = SC8280XP_MASTER_PCIE_TCU,
442
597
.channels = 1,
443
598
.buswidth = 8,
444
599
.num_links = 2,
445
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
446
-
SC8280XP_SLAVE_LLCC
447
-
},
600
+
.link_nodes = { &qns_gem_noc_cnoc,
601
+
&qns_llcc },
448
602
};
449
603
450
604
static struct qcom_icc_node alm_sys_tcu = {
451
605
.name = "alm_sys_tcu",
452
-
.id = SC8280XP_MASTER_SYS_TCU,
453
606
.channels = 1,
454
607
.buswidth = 8,
455
608
.num_links = 2,
456
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
457
-
SC8280XP_SLAVE_LLCC
458
-
},
609
+
.link_nodes = { &qns_gem_noc_cnoc,
610
+
&qns_llcc },
459
611
};
460
612
461
613
static struct qcom_icc_node chm_apps = {
462
614
.name = "chm_apps",
463
-
.id = SC8280XP_MASTER_APPSS_PROC,
464
615
.channels = 2,
465
616
.buswidth = 32,
466
617
.num_links = 3,
467
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
468
-
SC8280XP_SLAVE_LLCC,
469
-
SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC
470
-
},
618
+
.link_nodes = { &qns_gem_noc_cnoc,
619
+
&qns_llcc,
620
+
&qns_pcie },
471
621
};
472
622
473
623
static struct qcom_icc_node qnm_cmpnoc0 = {
474
624
.name = "qnm_cmpnoc0",
475
-
.id = SC8280XP_MASTER_COMPUTE_NOC,
476
625
.channels = 2,
477
626
.buswidth = 32,
478
627
.num_links = 2,
479
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
480
-
SC8280XP_SLAVE_LLCC
481
-
},
628
+
.link_nodes = { &qns_gem_noc_cnoc,
629
+
&qns_llcc },
482
630
};
483
631
484
632
static struct qcom_icc_node qnm_cmpnoc1 = {
485
633
.name = "qnm_cmpnoc1",
486
-
.id = SC8280XP_MASTER_COMPUTE_NOC_1,
487
634
.channels = 2,
488
635
.buswidth = 32,
489
636
.num_links = 2,
490
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
491
-
SC8280XP_SLAVE_LLCC
492
-
},
637
+
.link_nodes = { &qns_gem_noc_cnoc,
638
+
&qns_llcc },
493
639
};
494
640
495
641
static struct qcom_icc_node qnm_gemnoc_cfg = {
496
642
.name = "qnm_gemnoc_cfg",
497
-
.id = SC8280XP_MASTER_GEM_NOC_CFG,
498
643
.channels = 1,
499
644
.buswidth = 4,
500
645
.num_links = 3,
501
-
.links = { SC8280XP_SLAVE_SERVICE_GEM_NOC_1,
502
-
SC8280XP_SLAVE_SERVICE_GEM_NOC_2,
503
-
SC8280XP_SLAVE_SERVICE_GEM_NOC
504
-
},
646
+
.link_nodes = { &srvc_even_gemnoc,
647
+
&srvc_odd_gemnoc,
648
+
&srvc_sys_gemnoc },
505
649
};
506
650
507
651
static struct qcom_icc_node qnm_gpu = {
508
652
.name = "qnm_gpu",
509
-
.id = SC8280XP_MASTER_GFX3D,
510
653
.channels = 4,
511
654
.buswidth = 32,
512
655
.num_links = 2,
513
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
514
-
SC8280XP_SLAVE_LLCC
515
-
},
656
+
.link_nodes = { &qns_gem_noc_cnoc,
657
+
&qns_llcc },
516
658
};
517
659
518
660
static struct qcom_icc_node qnm_mnoc_hf = {
519
661
.name = "qnm_mnoc_hf",
520
-
.id = SC8280XP_MASTER_MNOC_HF_MEM_NOC,
521
662
.channels = 2,
522
663
.buswidth = 32,
523
664
.num_links = 2,
524
-
.links = { SC8280XP_SLAVE_LLCC,
525
-
SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC
526
-
},
665
+
.link_nodes = { &qns_llcc,
666
+
&qns_pcie },
527
667
};
528
668
529
669
static struct qcom_icc_node qnm_mnoc_sf = {
530
670
.name = "qnm_mnoc_sf",
531
-
.id = SC8280XP_MASTER_MNOC_SF_MEM_NOC,
532
671
.channels = 2,
533
672
.buswidth = 32,
534
673
.num_links = 2,
535
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
536
-
SC8280XP_SLAVE_LLCC
537
-
},
674
+
.link_nodes = { &qns_gem_noc_cnoc,
675
+
&qns_llcc },
538
676
};
539
677
540
678
static struct qcom_icc_node qnm_pcie = {
541
679
.name = "qnm_pcie",
542
-
.id = SC8280XP_MASTER_ANOC_PCIE_GEM_NOC,
543
680
.channels = 1,
544
681
.buswidth = 32,
545
682
.num_links = 2,
546
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
547
-
SC8280XP_SLAVE_LLCC
548
-
},
683
+
.link_nodes = { &qns_gem_noc_cnoc,
684
+
&qns_llcc },
549
685
};
550
686
551
687
static struct qcom_icc_node qnm_snoc_gc = {
552
688
.name = "qnm_snoc_gc",
553
-
.id = SC8280XP_MASTER_SNOC_GC_MEM_NOC,
554
689
.channels = 1,
555
690
.buswidth = 8,
556
691
.num_links = 1,
557
-
.links = { SC8280XP_SLAVE_LLCC },
692
+
.link_nodes = { &qns_llcc },
558
693
};
559
694
560
695
static struct qcom_icc_node qnm_snoc_sf = {
561
696
.name = "qnm_snoc_sf",
562
-
.id = SC8280XP_MASTER_SNOC_SF_MEM_NOC,
563
697
.channels = 1,
564
698
.buswidth = 16,
565
699
.num_links = 3,
566
-
.links = { SC8280XP_SLAVE_GEM_NOC_CNOC,
567
-
SC8280XP_SLAVE_LLCC,
568
-
SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC },
700
+
.link_nodes = { &qns_gem_noc_cnoc,
701
+
&qns_llcc,
702
+
&qns_pcie },
569
703
};
570
704
571
705
static struct qcom_icc_node qhm_config_noc = {
572
706
.name = "qhm_config_noc",
573
-
.id = SC8280XP_MASTER_CNOC_LPASS_AG_NOC,
574
707
.channels = 1,
575
708
.buswidth = 4,
576
709
.num_links = 6,
577
-
.links = { SC8280XP_SLAVE_LPASS_CORE_CFG,
578
-
SC8280XP_SLAVE_LPASS_LPI_CFG,
579
-
SC8280XP_SLAVE_LPASS_MPU_CFG,
580
-
SC8280XP_SLAVE_LPASS_TOP_CFG,
581
-
SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
582
-
SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC
583
-
},
710
+
.link_nodes = { &qhs_lpass_core,
711
+
&qhs_lpass_lpi,
712
+
&qhs_lpass_mpu,
713
+
&qhs_lpass_top,
714
+
&srvc_niu_aml_noc,
715
+
&srvc_niu_lpass_agnoc },
584
716
};
585
717
586
718
static struct qcom_icc_node qxm_lpass_dsp = {
587
719
.name = "qxm_lpass_dsp",
588
-
.id = SC8280XP_MASTER_LPASS_PROC,
589
720
.channels = 1,
590
721
.buswidth = 8,
591
722
.num_links = 4,
592
-
.links = { SC8280XP_SLAVE_LPASS_TOP_CFG,
593
-
SC8280XP_SLAVE_LPASS_SNOC,
594
-
SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
595
-
SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC
596
-
},
723
+
.link_nodes = { &qhs_lpass_top,
724
+
&qns_sysnoc,
725
+
&srvc_niu_aml_noc,
726
+
&srvc_niu_lpass_agnoc },
597
727
};
598
728
599
729
static struct qcom_icc_node llcc_mc = {
600
730
.name = "llcc_mc",
601
-
.id = SC8280XP_MASTER_LLCC,
602
731
.channels = 8,
603
732
.buswidth = 4,
604
733
.num_links = 1,
605
-
.links = { SC8280XP_SLAVE_EBI1 },
734
+
.link_nodes = { &ebi },
606
735
};
607
736
608
737
static struct qcom_icc_node qnm_camnoc_hf = {
609
738
.name = "qnm_camnoc_hf",
610
-
.id = SC8280XP_MASTER_CAMNOC_HF,
611
739
.channels = 2,
612
740
.buswidth = 32,
613
741
.num_links = 1,
614
-
.links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
742
+
.link_nodes = { &qns_mem_noc_hf },
615
743
};
616
744
617
745
static struct qcom_icc_node qnm_mdp0_0 = {
618
746
.name = "qnm_mdp0_0",
619
-
.id = SC8280XP_MASTER_MDP0,
620
747
.channels = 1,
621
748
.buswidth = 32,
622
749
.num_links = 1,
623
-
.links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
750
+
.link_nodes = { &qns_mem_noc_hf },
624
751
};
625
752
626
753
static struct qcom_icc_node qnm_mdp0_1 = {
627
754
.name = "qnm_mdp0_1",
628
-
.id = SC8280XP_MASTER_MDP1,
629
755
.channels = 1,
630
756
.buswidth = 32,
631
757
.num_links = 1,
632
-
.links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
758
+
.link_nodes = { &qns_mem_noc_hf },
633
759
};
634
760
635
761
static struct qcom_icc_node qnm_mdp1_0 = {
636
762
.name = "qnm_mdp1_0",
637
-
.id = SC8280XP_MASTER_MDP_CORE1_0,
638
763
.channels = 1,
639
764
.buswidth = 32,
640
765
.num_links = 1,
641
-
.links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
766
+
.link_nodes = { &qns_mem_noc_hf },
642
767
};
643
768
644
769
static struct qcom_icc_node qnm_mdp1_1 = {
645
770
.name = "qnm_mdp1_1",
646
-
.id = SC8280XP_MASTER_MDP_CORE1_1,
647
771
.channels = 1,
648
772
.buswidth = 32,
649
773
.num_links = 1,
650
-
.links = { SC8280XP_SLAVE_MNOC_HF_MEM_NOC },
774
+
.link_nodes = { &qns_mem_noc_hf },
651
775
};
652
776
653
777
static struct qcom_icc_node qnm_mnoc_cfg = {
654
778
.name = "qnm_mnoc_cfg",
655
-
.id = SC8280XP_MASTER_CNOC_MNOC_CFG,
656
779
.channels = 1,
657
780
.buswidth = 4,
658
781
.num_links = 1,
659
-
.links = { SC8280XP_SLAVE_SERVICE_MNOC },
782
+
.link_nodes = { &srvc_mnoc },
660
783
};
661
784
662
785
static struct qcom_icc_node qnm_rot_0 = {
663
786
.name = "qnm_rot_0",
664
-
.id = SC8280XP_MASTER_ROTATOR,
665
787
.channels = 1,
666
788
.buswidth = 32,
667
789
.num_links = 1,
668
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
790
+
.link_nodes = { &qns_mem_noc_sf },
669
791
};
670
792
671
793
static struct qcom_icc_node qnm_rot_1 = {
672
794
.name = "qnm_rot_1",
673
-
.id = SC8280XP_MASTER_ROTATOR_1,
674
795
.channels = 1,
675
796
.buswidth = 32,
676
797
.num_links = 1,
677
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
798
+
.link_nodes = { &qns_mem_noc_sf },
678
799
};
679
800
680
801
static struct qcom_icc_node qnm_video0 = {
681
802
.name = "qnm_video0",
682
-
.id = SC8280XP_MASTER_VIDEO_P0,
683
803
.channels = 1,
684
804
.buswidth = 32,
685
805
.num_links = 1,
686
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
806
+
.link_nodes = { &qns_mem_noc_sf },
687
807
};
688
808
689
809
static struct qcom_icc_node qnm_video1 = {
690
810
.name = "qnm_video1",
691
-
.id = SC8280XP_MASTER_VIDEO_P1,
692
811
.channels = 1,
693
812
.buswidth = 32,
694
813
.num_links = 1,
695
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
814
+
.link_nodes = { &qns_mem_noc_sf },
696
815
};
697
816
698
817
static struct qcom_icc_node qnm_video_cvp = {
699
818
.name = "qnm_video_cvp",
700
-
.id = SC8280XP_MASTER_VIDEO_PROC,
701
819
.channels = 1,
702
820
.buswidth = 32,
703
821
.num_links = 1,
704
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
822
+
.link_nodes = { &qns_mem_noc_sf },
705
823
};
706
824
707
825
static struct qcom_icc_node qxm_camnoc_icp = {
708
826
.name = "qxm_camnoc_icp",
709
-
.id = SC8280XP_MASTER_CAMNOC_ICP,
710
827
.channels = 1,
711
828
.buswidth = 8,
712
829
.num_links = 1,
713
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
830
+
.link_nodes = { &qns_mem_noc_sf },
714
831
};
715
832
716
833
static struct qcom_icc_node qxm_camnoc_sf = {
717
834
.name = "qxm_camnoc_sf",
718
-
.id = SC8280XP_MASTER_CAMNOC_SF,
719
835
.channels = 1,
720
836
.buswidth = 32,
721
837
.num_links = 1,
722
-
.links = { SC8280XP_SLAVE_MNOC_SF_MEM_NOC },
838
+
.link_nodes = { &qns_mem_noc_sf },
723
839
};
724
840
725
841
static struct qcom_icc_node qhm_nsp_noc_config = {
726
842
.name = "qhm_nsp_noc_config",
727
-
.id = SC8280XP_MASTER_CDSP_NOC_CFG,
728
843
.channels = 1,
729
844
.buswidth = 4,
730
845
.num_links = 1,
731
-
.links = { SC8280XP_SLAVE_SERVICE_NSP_NOC },
846
+
.link_nodes = { &service_nsp_noc },
732
847
};
733
848
734
849
static struct qcom_icc_node qxm_nsp = {
735
850
.name = "qxm_nsp",
736
-
.id = SC8280XP_MASTER_CDSP_PROC,
737
851
.channels = 2,
738
852
.buswidth = 32,
739
853
.num_links = 2,
740
-
.links = { SC8280XP_SLAVE_CDSP_MEM_NOC,
741
-
SC8280XP_SLAVE_NSP_XFR
742
-
},
854
+
.link_nodes = { &qns_nsp_gemnoc,
855
+
&qxs_nsp_xfr },
743
856
};
744
857
745
858
static struct qcom_icc_node qhm_nspb_noc_config = {
746
859
.name = "qhm_nspb_noc_config",
747
-
.id = SC8280XP_MASTER_CDSPB_NOC_CFG,
748
860
.channels = 1,
749
861
.buswidth = 4,
750
862
.num_links = 1,
751
-
.links = { SC8280XP_SLAVE_SERVICE_NSPB_NOC },
863
+
.link_nodes = { &service_nspb_noc },
752
864
};
753
865
754
866
static struct qcom_icc_node qxm_nspb = {
755
867
.name = "qxm_nspb",
756
-
.id = SC8280XP_MASTER_CDSP_PROC_B,
757
868
.channels = 2,
758
869
.buswidth = 32,
759
870
.num_links = 2,
760
-
.links = { SC8280XP_SLAVE_CDSPB_MEM_NOC,
761
-
SC8280XP_SLAVE_NSPB_XFR
762
-
},
871
+
.link_nodes = { &qns_nspb_gemnoc,
872
+
&qxs_nspb_xfr },
763
873
};
764
874
765
875
static struct qcom_icc_node qnm_aggre1_noc = {
766
876
.name = "qnm_aggre1_noc",
767
-
.id = SC8280XP_MASTER_A1NOC_SNOC,
768
877
.channels = 1,
769
878
.buswidth = 16,
770
879
.num_links = 1,
771
-
.links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
880
+
.link_nodes = { &qns_gemnoc_sf },
772
881
};
773
882
774
883
static struct qcom_icc_node qnm_aggre2_noc = {
775
884
.name = "qnm_aggre2_noc",
776
-
.id = SC8280XP_MASTER_A2NOC_SNOC,
777
885
.channels = 1,
778
886
.buswidth = 16,
779
887
.num_links = 1,
780
-
.links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
888
+
.link_nodes = { &qns_gemnoc_sf },
781
889
};
782
890
783
891
static struct qcom_icc_node qnm_aggre_usb_noc = {
784
892
.name = "qnm_aggre_usb_noc",
785
-
.id = SC8280XP_MASTER_USB_NOC_SNOC,
786
893
.channels = 1,
787
894
.buswidth = 16,
788
895
.num_links = 1,
789
-
.links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
896
+
.link_nodes = { &qns_gemnoc_sf },
790
897
};
791
898
792
899
static struct qcom_icc_node qnm_lpass_noc = {
793
900
.name = "qnm_lpass_noc",
794
-
.id = SC8280XP_MASTER_LPASS_ANOC,
795
901
.channels = 1,
796
902
.buswidth = 16,
797
903
.num_links = 1,
798
-
.links = { SC8280XP_SLAVE_SNOC_GEM_NOC_SF },
904
+
.link_nodes = { &qns_gemnoc_sf },
799
905
};
800
906
801
907
static struct qcom_icc_node qnm_snoc_cfg = {
802
908
.name = "qnm_snoc_cfg",
803
-
.id = SC8280XP_MASTER_SNOC_CFG,
804
909
.channels = 1,
805
910
.buswidth = 4,
806
911
.num_links = 1,
807
-
.links = { SC8280XP_SLAVE_SERVICE_SNOC },
912
+
.link_nodes = { &srvc_snoc },
808
913
};
809
914
810
915
static struct qcom_icc_node qxm_pimem = {
811
916
.name = "qxm_pimem",
812
-
.id = SC8280XP_MASTER_PIMEM,
813
917
.channels = 1,
814
918
.buswidth = 8,
815
919
.num_links = 1,
816
-
.links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC },
920
+
.link_nodes = { &qns_gemnoc_gc },
817
921
};
818
922
819
923
static struct qcom_icc_node xm_gic = {
820
924
.name = "xm_gic",
821
-
.id = SC8280XP_MASTER_GIC,
822
925
.channels = 1,
823
926
.buswidth = 8,
824
927
.num_links = 1,
825
-
.links = { SC8280XP_SLAVE_SNOC_GEM_NOC_GC },
928
+
.link_nodes = { &qns_gemnoc_gc },
826
929
};
827
930
828
931
static struct qcom_icc_node qns_a1noc_snoc = {
829
932
.name = "qns_a1noc_snoc",
830
-
.id = SC8280XP_SLAVE_A1NOC_SNOC,
831
933
.channels = 1,
832
934
.buswidth = 16,
833
935
.num_links = 1,
834
-
.links = { SC8280XP_MASTER_A1NOC_SNOC },
936
+
.link_nodes = { &qnm_aggre1_noc },
835
937
};
836
938
837
939
static struct qcom_icc_node qns_aggre_usb_snoc = {
838
940
.name = "qns_aggre_usb_snoc",
839
-
.id = SC8280XP_SLAVE_USB_NOC_SNOC,
840
941
.channels = 1,
841
942
.buswidth = 16,
842
943
.num_links = 1,
843
-
.links = { SC8280XP_MASTER_USB_NOC_SNOC },
944
+
.link_nodes = { &qnm_aggre_usb_noc },
844
945
};
845
946
846
947
static struct qcom_icc_node srvc_aggre1_noc = {
847
948
.name = "srvc_aggre1_noc",
848
-
.id = SC8280XP_SLAVE_SERVICE_A1NOC,
849
949
.channels = 1,
850
950
.buswidth = 4,
851
951
};
852
952
853
953
static struct qcom_icc_node qns_a2noc_snoc = {
854
954
.name = "qns_a2noc_snoc",
855
-
.id = SC8280XP_SLAVE_A2NOC_SNOC,
856
955
.channels = 1,
857
956
.buswidth = 16,
858
957
.num_links = 1,
859
-
.links = { SC8280XP_MASTER_A2NOC_SNOC },
958
+
.link_nodes = { &qnm_aggre2_noc },
860
959
};
861
960
862
961
static struct qcom_icc_node qns_pcie_gem_noc = {
863
962
.name = "qns_pcie_gem_noc",
864
-
.id = SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC,
865
963
.channels = 1,
866
964
.buswidth = 32,
867
965
.num_links = 1,
868
-
.links = { SC8280XP_MASTER_ANOC_PCIE_GEM_NOC },
966
+
.link_nodes = { &qnm_pcie },
869
967
};
870
968
871
969
static struct qcom_icc_node srvc_aggre2_noc = {
872
970
.name = "srvc_aggre2_noc",
873
-
.id = SC8280XP_SLAVE_SERVICE_A2NOC,
874
971
.channels = 1,
875
972
.buswidth = 4,
876
973
};
877
974
878
975
static struct qcom_icc_node qup0_core_slave = {
879
976
.name = "qup0_core_slave",
880
-
.id = SC8280XP_SLAVE_QUP_CORE_0,
881
977
.channels = 1,
882
978
.buswidth = 4,
883
979
};
884
980
885
981
static struct qcom_icc_node qup1_core_slave = {
886
982
.name = "qup1_core_slave",
887
-
.id = SC8280XP_SLAVE_QUP_CORE_1,
888
983
.channels = 1,
889
984
.buswidth = 4,
890
985
};
891
986
892
987
static struct qcom_icc_node qup2_core_slave = {
893
988
.name = "qup2_core_slave",
894
-
.id = SC8280XP_SLAVE_QUP_CORE_2,
895
989
.channels = 1,
896
990
.buswidth = 4,
897
991
};
898
992
899
993
static struct qcom_icc_node qhs_ahb2phy0 = {
900
994
.name = "qhs_ahb2phy0",
901
-
.id = SC8280XP_SLAVE_AHB2PHY_0,
902
995
.channels = 1,
903
996
.buswidth = 4,
904
997
};
905
998
906
999
static struct qcom_icc_node qhs_ahb2phy1 = {
907
1000
.name = "qhs_ahb2phy1",
908
-
.id = SC8280XP_SLAVE_AHB2PHY_1,
909
1001
.channels = 1,
910
1002
.buswidth = 4,
911
1003
};
912
1004
913
1005
static struct qcom_icc_node qhs_ahb2phy2 = {
914
1006
.name = "qhs_ahb2phy2",
915
-
.id = SC8280XP_SLAVE_AHB2PHY_2,
916
1007
.channels = 1,
917
1008
.buswidth = 4,
918
1009
};
919
1010
920
1011
static struct qcom_icc_node qhs_aoss = {
921
1012
.name = "qhs_aoss",
922
-
.id = SC8280XP_SLAVE_AOSS,
923
1013
.channels = 1,
924
1014
.buswidth = 4,
925
1015
};
926
1016
927
1017
static struct qcom_icc_node qhs_apss = {
928
1018
.name = "qhs_apss",
929
-
.id = SC8280XP_SLAVE_APPSS,
930
1019
.channels = 1,
931
1020
.buswidth = 8,
932
1021
};
933
1022
934
1023
static struct qcom_icc_node qhs_camera_cfg = {
935
1024
.name = "qhs_camera_cfg",
936
-
.id = SC8280XP_SLAVE_CAMERA_CFG,
937
1025
.channels = 1,
938
1026
.buswidth = 4,
939
1027
};
940
1028
941
1029
static struct qcom_icc_node qhs_clk_ctl = {
942
1030
.name = "qhs_clk_ctl",
943
-
.id = SC8280XP_SLAVE_CLK_CTL,
944
1031
.channels = 1,
945
1032
.buswidth = 4,
946
1033
};
947
1034
948
1035
static struct qcom_icc_node qhs_compute0_cfg = {
949
1036
.name = "qhs_compute0_cfg",
950
-
.id = SC8280XP_SLAVE_CDSP_CFG,
951
1037
.channels = 1,
952
1038
.buswidth = 4,
953
1039
.num_links = 1,
954
-
.links = { SC8280XP_MASTER_CDSP_NOC_CFG },
1040
+
.link_nodes = { &qhm_nsp_noc_config },
955
1041
};
956
1042
957
1043
static struct qcom_icc_node qhs_compute1_cfg = {
958
1044
.name = "qhs_compute1_cfg",
959
-
.id = SC8280XP_SLAVE_CDSP1_CFG,
960
1045
.channels = 1,
961
1046
.buswidth = 4,
962
1047
.num_links = 1,
963
-
.links = { SC8280XP_MASTER_CDSPB_NOC_CFG },
1048
+
.link_nodes = { &qhm_nspb_noc_config },
964
1049
};
965
1050
966
1051
static struct qcom_icc_node qhs_cpr_cx = {
967
1052
.name = "qhs_cpr_cx",
968
-
.id = SC8280XP_SLAVE_RBCPR_CX_CFG,
969
1053
.channels = 1,
970
1054
.buswidth = 4,
971
1055
};
972
1056
973
1057
static struct qcom_icc_node qhs_cpr_mmcx = {
974
1058
.name = "qhs_cpr_mmcx",
975
-
.id = SC8280XP_SLAVE_RBCPR_MMCX_CFG,
976
1059
.channels = 1,
977
1060
.buswidth = 4,
978
1061
};
979
1062
980
1063
static struct qcom_icc_node qhs_cpr_mx = {
981
1064
.name = "qhs_cpr_mx",
982
-
.id = SC8280XP_SLAVE_RBCPR_MX_CFG,
983
1065
.channels = 1,
984
1066
.buswidth = 4,
985
1067
};
986
1068
987
1069
static struct qcom_icc_node qhs_cpr_nspcx = {
988
1070
.name = "qhs_cpr_nspcx",
989
-
.id = SC8280XP_SLAVE_CPR_NSPCX,
990
1071
.channels = 1,
991
1072
.buswidth = 4,
992
1073
};
993
1074
994
1075
static struct qcom_icc_node qhs_crypto0_cfg = {
995
1076
.name = "qhs_crypto0_cfg",
996
-
.id = SC8280XP_SLAVE_CRYPTO_0_CFG,
997
1077
.channels = 1,
998
1078
.buswidth = 4,
999
1079
};
1000
1080
1001
1081
static struct qcom_icc_node qhs_cx_rdpm = {
1002
1082
.name = "qhs_cx_rdpm",
1003
-
.id = SC8280XP_SLAVE_CX_RDPM,
1004
1083
.channels = 1,
1005
1084
.buswidth = 4,
1006
1085
};
1007
1086
1008
1087
static struct qcom_icc_node qhs_dcc_cfg = {
1009
1088
.name = "qhs_dcc_cfg",
1010
-
.id = SC8280XP_SLAVE_DCC_CFG,
1011
1089
.channels = 1,
1012
1090
.buswidth = 4,
1013
1091
};
1014
1092
1015
1093
static struct qcom_icc_node qhs_display0_cfg = {
1016
1094
.name = "qhs_display0_cfg",
1017
-
.id = SC8280XP_SLAVE_DISPLAY_CFG,
1018
1095
.channels = 1,
1019
1096
.buswidth = 4,
1020
1097
};
1021
1098
1022
1099
static struct qcom_icc_node qhs_display1_cfg = {
1023
1100
.name = "qhs_display1_cfg",
1024
-
.id = SC8280XP_SLAVE_DISPLAY1_CFG,
1025
1101
.channels = 1,
1026
1102
.buswidth = 4,
1027
1103
};
1028
1104
1029
1105
static struct qcom_icc_node qhs_emac0_cfg = {
1030
1106
.name = "qhs_emac0_cfg",
1031
-
.id = SC8280XP_SLAVE_EMAC_CFG,
1032
1107
.channels = 1,
1033
1108
.buswidth = 4,
1034
1109
};
1035
1110
1036
1111
static struct qcom_icc_node qhs_emac1_cfg = {
1037
1112
.name = "qhs_emac1_cfg",
1038
-
.id = SC8280XP_SLAVE_EMAC1_CFG,
1039
1113
.channels = 1,
1040
1114
.buswidth = 4,
1041
1115
};
1042
1116
1043
1117
static struct qcom_icc_node qhs_gpuss_cfg = {
1044
1118
.name = "qhs_gpuss_cfg",
1045
-
.id = SC8280XP_SLAVE_GFX3D_CFG,
1046
1119
.channels = 1,
1047
1120
.buswidth = 8,
1048
1121
};
1049
1122
1050
1123
static struct qcom_icc_node qhs_hwkm = {
1051
1124
.name = "qhs_hwkm",
1052
-
.id = SC8280XP_SLAVE_HWKM,
1053
1125
.channels = 1,
1054
1126
.buswidth = 4,
1055
1127
};
1056
1128
1057
1129
static struct qcom_icc_node qhs_imem_cfg = {
1058
1130
.name = "qhs_imem_cfg",
1059
-
.id = SC8280XP_SLAVE_IMEM_CFG,
1060
1131
.channels = 1,
1061
1132
.buswidth = 4,
1062
1133
};
1063
1134
1064
1135
static struct qcom_icc_node qhs_ipa = {
1065
1136
.name = "qhs_ipa",
1066
-
.id = SC8280XP_SLAVE_IPA_CFG,
1067
1137
.channels = 1,
1068
1138
.buswidth = 4,
1069
1139
};
1070
1140
1071
1141
static struct qcom_icc_node qhs_ipc_router = {
1072
1142
.name = "qhs_ipc_router",
1073
-
.id = SC8280XP_SLAVE_IPC_ROUTER_CFG,
1074
1143
.channels = 1,
1075
1144
.buswidth = 4,
1076
1145
};
1077
1146
1078
1147
static struct qcom_icc_node qhs_lpass_cfg = {
1079
1148
.name = "qhs_lpass_cfg",
1080
-
.id = SC8280XP_SLAVE_LPASS,
1081
1149
.channels = 1,
1082
1150
.buswidth = 4,
1083
1151
.num_links = 1,
1084
-
.links = { SC8280XP_MASTER_CNOC_LPASS_AG_NOC },
1152
+
.link_nodes = { &qhm_config_noc },
1085
1153
};
1086
1154
1087
1155
static struct qcom_icc_node qhs_mx_rdpm = {
1088
1156
.name = "qhs_mx_rdpm",
1089
-
.id = SC8280XP_SLAVE_MX_RDPM,
1090
1157
.channels = 1,
1091
1158
.buswidth = 4,
1092
1159
};
1093
1160
1094
1161
static struct qcom_icc_node qhs_mxc_rdpm = {
1095
1162
.name = "qhs_mxc_rdpm",
1096
-
.id = SC8280XP_SLAVE_MXC_RDPM,
1097
1163
.channels = 1,
1098
1164
.buswidth = 4,
1099
1165
};
1100
1166
1101
1167
static struct qcom_icc_node qhs_pcie0_cfg = {
1102
1168
.name = "qhs_pcie0_cfg",
1103
-
.id = SC8280XP_SLAVE_PCIE_0_CFG,
1104
1169
.channels = 1,
1105
1170
.buswidth = 4,
1106
1171
};
1107
1172
1108
1173
static struct qcom_icc_node qhs_pcie1_cfg = {
1109
1174
.name = "qhs_pcie1_cfg",
1110
-
.id = SC8280XP_SLAVE_PCIE_1_CFG,
1111
1175
.channels = 1,
1112
1176
.buswidth = 4,
1113
1177
};
1114
1178
1115
1179
static struct qcom_icc_node qhs_pcie2a_cfg = {
1116
1180
.name = "qhs_pcie2a_cfg",
1117
-
.id = SC8280XP_SLAVE_PCIE_2A_CFG,
1118
1181
.channels = 1,
1119
1182
.buswidth = 4,
1120
1183
};
1121
1184
1122
1185
static struct qcom_icc_node qhs_pcie2b_cfg = {
1123
1186
.name = "qhs_pcie2b_cfg",
1124
-
.id = SC8280XP_SLAVE_PCIE_2B_CFG,
1125
1187
.channels = 1,
1126
1188
.buswidth = 4,
1127
1189
};
1128
1190
1129
1191
static struct qcom_icc_node qhs_pcie3a_cfg = {
1130
1192
.name = "qhs_pcie3a_cfg",
1131
-
.id = SC8280XP_SLAVE_PCIE_3A_CFG,
1132
1193
.channels = 1,
1133
1194
.buswidth = 4,
1134
1195
};
1135
1196
1136
1197
static struct qcom_icc_node qhs_pcie3b_cfg = {
1137
1198
.name = "qhs_pcie3b_cfg",
1138
-
.id = SC8280XP_SLAVE_PCIE_3B_CFG,
1139
1199
.channels = 1,
1140
1200
.buswidth = 4,
1141
1201
};
1142
1202
1143
1203
static struct qcom_icc_node qhs_pcie4_cfg = {
1144
1204
.name = "qhs_pcie4_cfg",
1145
-
.id = SC8280XP_SLAVE_PCIE_4_CFG,
1146
1205
.channels = 1,
1147
1206
.buswidth = 4,
1148
1207
};
1149
1208
1150
1209
static struct qcom_icc_node qhs_pcie_rsc_cfg = {
1151
1210
.name = "qhs_pcie_rsc_cfg",
1152
-
.id = SC8280XP_SLAVE_PCIE_RSC_CFG,
1153
1211
.channels = 1,
1154
1212
.buswidth = 4,
1155
1213
};
1156
1214
1157
1215
static struct qcom_icc_node qhs_pdm = {
1158
1216
.name = "qhs_pdm",
1159
-
.id = SC8280XP_SLAVE_PDM,
1160
1217
.channels = 1,
1161
1218
.buswidth = 4,
1162
1219
};
1163
1220
1164
1221
static struct qcom_icc_node qhs_pimem_cfg = {
1165
1222
.name = "qhs_pimem_cfg",
1166
-
.id = SC8280XP_SLAVE_PIMEM_CFG,
1167
1223
.channels = 1,
1168
1224
.buswidth = 4,
1169
1225
};
1170
1226
1171
1227
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
1172
1228
.name = "qhs_pka_wrapper_cfg",
1173
-
.id = SC8280XP_SLAVE_PKA_WRAPPER_CFG,
1174
1229
.channels = 1,
1175
1230
.buswidth = 4,
1176
1231
};
1177
1232
1178
1233
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
1179
1234
.name = "qhs_pmu_wrapper_cfg",
1180
-
.id = SC8280XP_SLAVE_PMU_WRAPPER_CFG,
1181
1235
.channels = 1,
1182
1236
.buswidth = 4,
1183
1237
};
1184
1238
1185
1239
static struct qcom_icc_node qhs_qdss_cfg = {
1186
1240
.name = "qhs_qdss_cfg",
1187
-
.id = SC8280XP_SLAVE_QDSS_CFG,
1188
1241
.channels = 1,
1189
1242
.buswidth = 4,
1190
1243
};
1191
1244
1192
1245
static struct qcom_icc_node qhs_qspi = {
1193
1246
.name = "qhs_qspi",
1194
-
.id = SC8280XP_SLAVE_QSPI_0,
1195
1247
.channels = 1,
1196
1248
.buswidth = 4,
1197
1249
};
1198
1250
1199
1251
static struct qcom_icc_node qhs_qup0 = {
1200
1252
.name = "qhs_qup0",
1201
-
.id = SC8280XP_SLAVE_QUP_0,
1202
1253
.channels = 1,
1203
1254
.buswidth = 4,
1204
1255
};
1205
1256
1206
1257
static struct qcom_icc_node qhs_qup1 = {
1207
1258
.name = "qhs_qup1",
1208
-
.id = SC8280XP_SLAVE_QUP_1,
1209
1259
.channels = 1,
1210
1260
.buswidth = 4,
1211
1261
};
1212
1262
1213
1263
static struct qcom_icc_node qhs_qup2 = {
1214
1264
.name = "qhs_qup2",
1215
-
.id = SC8280XP_SLAVE_QUP_2,
1216
1265
.channels = 1,
1217
1266
.buswidth = 4,
1218
1267
};
1219
1268
1220
1269
static struct qcom_icc_node qhs_sdc2 = {
1221
1270
.name = "qhs_sdc2",
1222
-
.id = SC8280XP_SLAVE_SDCC_2,
1223
1271
.channels = 1,
1224
1272
.buswidth = 4,
1225
1273
};
1226
1274
1227
1275
static struct qcom_icc_node qhs_sdc4 = {
1228
1276
.name = "qhs_sdc4",
1229
-
.id = SC8280XP_SLAVE_SDCC_4,
1230
1277
.channels = 1,
1231
1278
.buswidth = 4,
1232
1279
};
1233
1280
1234
1281
static struct qcom_icc_node qhs_security = {
1235
1282
.name = "qhs_security",
1236
-
.id = SC8280XP_SLAVE_SECURITY,
1237
1283
.channels = 1,
1238
1284
.buswidth = 4,
1239
1285
};
1240
1286
1241
1287
static struct qcom_icc_node qhs_smmuv3_cfg = {
1242
1288
.name = "qhs_smmuv3_cfg",
1243
-
.id = SC8280XP_SLAVE_SMMUV3_CFG,
1244
1289
.channels = 1,
1245
1290
.buswidth = 8,
1246
1291
};
1247
1292
1248
1293
static struct qcom_icc_node qhs_smss_cfg = {
1249
1294
.name = "qhs_smss_cfg",
1250
-
.id = SC8280XP_SLAVE_SMSS_CFG,
1251
1295
.channels = 1,
1252
1296
.buswidth = 4,
1253
1297
};
1254
1298
1255
1299
static struct qcom_icc_node qhs_spss_cfg = {
1256
1300
.name = "qhs_spss_cfg",
1257
-
.id = SC8280XP_SLAVE_SPSS_CFG,
1258
1301
.channels = 1,
1259
1302
.buswidth = 4,
1260
1303
};
1261
1304
1262
1305
static struct qcom_icc_node qhs_tcsr = {
1263
1306
.name = "qhs_tcsr",
1264
-
.id = SC8280XP_SLAVE_TCSR,
1265
1307
.channels = 1,
1266
1308
.buswidth = 4,
1267
1309
};
1268
1310
1269
1311
static struct qcom_icc_node qhs_tlmm = {
1270
1312
.name = "qhs_tlmm",
1271
-
.id = SC8280XP_SLAVE_TLMM,
1272
1313
.channels = 1,
1273
1314
.buswidth = 4,
1274
1315
};
1275
1316
1276
1317
static struct qcom_icc_node qhs_ufs_card_cfg = {
1277
1318
.name = "qhs_ufs_card_cfg",
1278
-
.id = SC8280XP_SLAVE_UFS_CARD_CFG,
1279
1319
.channels = 1,
1280
1320
.buswidth = 4,
1281
1321
};
1282
1322
1283
1323
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1284
1324
.name = "qhs_ufs_mem_cfg",
1285
-
.id = SC8280XP_SLAVE_UFS_MEM_CFG,
1286
1325
.channels = 1,
1287
1326
.buswidth = 4,
1288
1327
};
1289
1328
1290
1329
static struct qcom_icc_node qhs_usb3_0 = {
1291
1330
.name = "qhs_usb3_0",
1292
-
.id = SC8280XP_SLAVE_USB3_0,
1293
1331
.channels = 1,
1294
1332
.buswidth = 4,
1295
1333
};
1296
1334
1297
1335
static struct qcom_icc_node qhs_usb3_1 = {
1298
1336
.name = "qhs_usb3_1",
1299
-
.id = SC8280XP_SLAVE_USB3_1,
1300
1337
.channels = 1,
1301
1338
.buswidth = 4,
1302
1339
};
1303
1340
1304
1341
static struct qcom_icc_node qhs_usb3_mp = {
1305
1342
.name = "qhs_usb3_mp",
1306
-
.id = SC8280XP_SLAVE_USB3_MP,
1307
1343
.channels = 1,
1308
1344
.buswidth = 4,
1309
1345
};
1310
1346
1311
1347
static struct qcom_icc_node qhs_usb4_host_0 = {
1312
1348
.name = "qhs_usb4_host_0",
1313
-
.id = SC8280XP_SLAVE_USB4_0,
1314
1349
.channels = 1,
1315
1350
.buswidth = 4,
1316
1351
};
1317
1352
1318
1353
static struct qcom_icc_node qhs_usb4_host_1 = {
1319
1354
.name = "qhs_usb4_host_1",
1320
-
.id = SC8280XP_SLAVE_USB4_1,
1321
1355
.channels = 1,
1322
1356
.buswidth = 4,
1323
1357
};
1324
1358
1325
1359
static struct qcom_icc_node qhs_venus_cfg = {
1326
1360
.name = "qhs_venus_cfg",
1327
-
.id = SC8280XP_SLAVE_VENUS_CFG,
1328
1361
.channels = 1,
1329
1362
.buswidth = 4,
1330
1363
};
1331
1364
1332
1365
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1333
1366
.name = "qhs_vsense_ctrl_cfg",
1334
-
.id = SC8280XP_SLAVE_VSENSE_CTRL_CFG,
1335
1367
.channels = 1,
1336
1368
.buswidth = 4,
1337
1369
};
1338
1370
1339
1371
static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = {
1340
1372
.name = "qhs_vsense_ctrl_r_cfg",
1341
-
.id = SC8280XP_SLAVE_VSENSE_CTRL_R_CFG,
1342
1373
.channels = 1,
1343
1374
.buswidth = 4,
1344
1375
};
1345
1376
1346
1377
static struct qcom_icc_node qns_a1_noc_cfg = {
1347
1378
.name = "qns_a1_noc_cfg",
1348
-
.id = SC8280XP_SLAVE_A1NOC_CFG,
1349
1379
.channels = 1,
1350
1380
.buswidth = 4,
1351
1381
.num_links = 1,
1352
-
.links = { SC8280XP_MASTER_A1NOC_CFG },
1382
+
.link_nodes = { &qnm_a1noc_cfg },
1353
1383
};
1354
1384
1355
1385
static struct qcom_icc_node qns_a2_noc_cfg = {
1356
1386
.name = "qns_a2_noc_cfg",
1357
-
.id = SC8280XP_SLAVE_A2NOC_CFG,
1358
1387
.channels = 1,
1359
1388
.buswidth = 4,
1360
1389
.num_links = 1,
1361
-
.links = { SC8280XP_MASTER_A2NOC_CFG },
1390
+
.link_nodes = { &qnm_a2noc_cfg },
1362
1391
};
1363
1392
1364
1393
static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = {
1365
1394
.name = "qns_anoc_pcie_bridge_cfg",
1366
-
.id = SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG,
1367
1395
.channels = 1,
1368
1396
.buswidth = 4,
1369
1397
};
1370
1398
1371
1399
static struct qcom_icc_node qns_ddrss_cfg = {
1372
1400
.name = "qns_ddrss_cfg",
1373
-
.id = SC8280XP_SLAVE_DDRSS_CFG,
1374
1401
.channels = 1,
1375
1402
.buswidth = 4,
1376
1403
.num_links = 1,
1377
-
.links = { SC8280XP_MASTER_CNOC_DC_NOC },
1404
+
.link_nodes = { &qnm_cnoc_dc_noc },
1378
1405
};
1379
1406
1380
1407
static struct qcom_icc_node qns_mnoc_cfg = {
1381
1408
.name = "qns_mnoc_cfg",
1382
-
.id = SC8280XP_SLAVE_CNOC_MNOC_CFG,
1383
1409
.channels = 1,
1384
1410
.buswidth = 4,
1385
1411
.num_links = 1,
1386
-
.links = { SC8280XP_MASTER_CNOC_MNOC_CFG },
1412
+
.link_nodes = { &qnm_mnoc_cfg },
1387
1413
};
1388
1414
1389
1415
static struct qcom_icc_node qns_snoc_cfg = {
1390
1416
.name = "qns_snoc_cfg",
1391
-
.id = SC8280XP_SLAVE_SNOC_CFG,
1392
1417
.channels = 1,
1393
1418
.buswidth = 4,
1394
1419
.num_links = 1,
1395
-
.links = { SC8280XP_MASTER_SNOC_CFG },
1420
+
.link_nodes = { &qnm_snoc_cfg },
1396
1421
};
1397
1422
1398
1423
static struct qcom_icc_node qns_snoc_sf_bridge_cfg = {
1399
1424
.name = "qns_snoc_sf_bridge_cfg",
1400
-
.id = SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG,
1401
1425
.channels = 1,
1402
1426
.buswidth = 4,
1403
1427
};
1404
1428
1405
1429
static struct qcom_icc_node qxs_imem = {
1406
1430
.name = "qxs_imem",
1407
-
.id = SC8280XP_SLAVE_IMEM,
1408
1431
.channels = 1,
1409
1432
.buswidth = 8,
1410
1433
};
1411
1434
1412
1435
static struct qcom_icc_node qxs_pimem = {
1413
1436
.name = "qxs_pimem",
1414
-
.id = SC8280XP_SLAVE_PIMEM,
1415
1437
.channels = 1,
1416
1438
.buswidth = 8,
1417
1439
};
1418
1440
1419
1441
static struct qcom_icc_node srvc_cnoc = {
1420
1442
.name = "srvc_cnoc",
1421
-
.id = SC8280XP_SLAVE_SERVICE_CNOC,
1422
1443
.channels = 1,
1423
1444
.buswidth = 4,
1424
1445
};
1425
1446
1426
1447
static struct qcom_icc_node xs_pcie_0 = {
1427
1448
.name = "xs_pcie_0",
1428
-
.id = SC8280XP_SLAVE_PCIE_0,
1429
1449
.channels = 1,
1430
1450
.buswidth = 16,
1431
1451
};
1432
1452
1433
1453
static struct qcom_icc_node xs_pcie_1 = {
1434
1454
.name = "xs_pcie_1",
1435
-
.id = SC8280XP_SLAVE_PCIE_1,
1436
1455
.channels = 1,
1437
1456
.buswidth = 16,
1438
1457
};
1439
1458
1440
1459
static struct qcom_icc_node xs_pcie_2a = {
1441
1460
.name = "xs_pcie_2a",
1442
-
.id = SC8280XP_SLAVE_PCIE_2A,
1443
1461
.channels = 1,
1444
1462
.buswidth = 16,
1445
1463
};
1446
1464
1447
1465
static struct qcom_icc_node xs_pcie_2b = {
1448
1466
.name = "xs_pcie_2b",
1449
-
.id = SC8280XP_SLAVE_PCIE_2B,
1450
1467
.channels = 1,
1451
1468
.buswidth = 8,
1452
1469
};
1453
1470
1454
1471
static struct qcom_icc_node xs_pcie_3a = {
1455
1472
.name = "xs_pcie_3a",
1456
-
.id = SC8280XP_SLAVE_PCIE_3A,
1457
1473
.channels = 1,
1458
1474
.buswidth = 16,
1459
1475
};
1460
1476
1461
1477
static struct qcom_icc_node xs_pcie_3b = {
1462
1478
.name = "xs_pcie_3b",
1463
-
.id = SC8280XP_SLAVE_PCIE_3B,
1464
1479
.channels = 1,
1465
1480
.buswidth = 8,
1466
1481
};
1467
1482
1468
1483
static struct qcom_icc_node xs_pcie_4 = {
1469
1484
.name = "xs_pcie_4",
1470
-
.id = SC8280XP_SLAVE_PCIE_4,
1471
1485
.channels = 1,
1472
1486
.buswidth = 8,
1473
1487
};
1474
1488
1475
1489
static struct qcom_icc_node xs_qdss_stm = {
1476
1490
.name = "xs_qdss_stm",
1477
-
.id = SC8280XP_SLAVE_QDSS_STM,
1478
1491
.channels = 1,
1479
1492
.buswidth = 4,
1480
1493
};
1481
1494
1482
1495
static struct qcom_icc_node xs_smss = {
1483
1496
.name = "xs_smss",
1484
-
.id = SC8280XP_SLAVE_SMSS,
1485
1497
.channels = 1,
1486
1498
.buswidth = 8,
1487
1499
};
1488
1500
1489
1501
static struct qcom_icc_node xs_sys_tcu_cfg = {
1490
1502
.name = "xs_sys_tcu_cfg",
1491
-
.id = SC8280XP_SLAVE_TCU,
1492
1503
.channels = 1,
1493
1504
.buswidth = 8,
1494
1505
};
1495
1506
1496
1507
static struct qcom_icc_node qhs_llcc = {
1497
1508
.name = "qhs_llcc",
1498
-
.id = SC8280XP_SLAVE_LLCC_CFG,
1499
1509
.channels = 1,
1500
1510
.buswidth = 4,
1501
1511
};
1502
1512
1503
1513
static struct qcom_icc_node qns_gemnoc = {
1504
1514
.name = "qns_gemnoc",
1505
-
.id = SC8280XP_SLAVE_GEM_NOC_CFG,
1506
1515
.channels = 1,
1507
1516
.buswidth = 4,
1508
1517
.num_links = 1,
1509
-
.links = { SC8280XP_MASTER_GEM_NOC_CFG },
1518
+
.link_nodes = { &qnm_gemnoc_cfg },
1510
1519
};
1511
1520
1512
1521
static struct qcom_icc_node qns_gem_noc_cnoc = {
1513
1522
.name = "qns_gem_noc_cnoc",
1514
-
.id = SC8280XP_SLAVE_GEM_NOC_CNOC,
1515
1523
.channels = 1,
1516
1524
.buswidth = 16,
1517
1525
.num_links = 1,
1518
-
.links = { SC8280XP_MASTER_GEM_NOC_CNOC },
1526
+
.link_nodes = { &qnm_gemnoc_cnoc },
1519
1527
};
1520
1528
1521
1529
static struct qcom_icc_node qns_llcc = {
1522
1530
.name = "qns_llcc",
1523
-
.id = SC8280XP_SLAVE_LLCC,
1524
1531
.channels = 8,
1525
1532
.buswidth = 16,
1526
1533
.num_links = 1,
1527
-
.links = { SC8280XP_MASTER_LLCC },
1534
+
.link_nodes = { &llcc_mc },
1528
1535
};
1529
1536
1530
1537
static struct qcom_icc_node qns_pcie = {
1531
1538
.name = "qns_pcie",
1532
-
.id = SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC,
1533
1539
.channels = 1,
1534
1540
.buswidth = 16,
1535
1541
.num_links = 1,
1536
-
.links = { SC8280XP_MASTER_GEM_NOC_PCIE_SNOC },
1542
+
.link_nodes = { &qnm_gemnoc_pcie },
1537
1543
};
1538
1544
1539
1545
static struct qcom_icc_node srvc_even_gemnoc = {
1540
1546
.name = "srvc_even_gemnoc",
1541
-
.id = SC8280XP_SLAVE_SERVICE_GEM_NOC_1,
1542
1547
.channels = 1,
1543
1548
.buswidth = 4,
1544
1549
};
1545
1550
1546
1551
static struct qcom_icc_node srvc_odd_gemnoc = {
1547
1552
.name = "srvc_odd_gemnoc",
1548
-
.id = SC8280XP_SLAVE_SERVICE_GEM_NOC_2,
1549
1553
.channels = 1,
1550
1554
.buswidth = 4,
1551
1555
};
1552
1556
1553
1557
static struct qcom_icc_node srvc_sys_gemnoc = {
1554
1558
.name = "srvc_sys_gemnoc",
1555
-
.id = SC8280XP_SLAVE_SERVICE_GEM_NOC,
1556
1559
.channels = 1,
1557
1560
.buswidth = 4,
1558
1561
};
1559
1562
1560
1563
static struct qcom_icc_node qhs_lpass_core = {
1561
1564
.name = "qhs_lpass_core",
1562
-
.id = SC8280XP_SLAVE_LPASS_CORE_CFG,
1563
1565
.channels = 1,
1564
1566
.buswidth = 4,
1565
1567
};
1566
1568
1567
1569
static struct qcom_icc_node qhs_lpass_lpi = {
1568
1570
.name = "qhs_lpass_lpi",
1569
-
.id = SC8280XP_SLAVE_LPASS_LPI_CFG,
1570
1571
.channels = 1,
1571
1572
.buswidth = 4,
1572
1573
};
1573
1574
1574
1575
static struct qcom_icc_node qhs_lpass_mpu = {
1575
1576
.name = "qhs_lpass_mpu",
1576
-
.id = SC8280XP_SLAVE_LPASS_MPU_CFG,
1577
1577
.channels = 1,
1578
1578
.buswidth = 4,
1579
1579
};
1580
1580
1581
1581
static struct qcom_icc_node qhs_lpass_top = {
1582
1582
.name = "qhs_lpass_top",
1583
-
.id = SC8280XP_SLAVE_LPASS_TOP_CFG,
1584
1583
.channels = 1,
1585
1584
.buswidth = 4,
1586
1585
};
1587
1586
1588
1587
static struct qcom_icc_node qns_sysnoc = {
1589
1588
.name = "qns_sysnoc",
1590
-
.id = SC8280XP_SLAVE_LPASS_SNOC,
1591
1589
.channels = 1,
1592
1590
.buswidth = 16,
1593
1591
.num_links = 1,
1594
-
.links = { SC8280XP_MASTER_LPASS_ANOC },
1592
+
.link_nodes = { &qnm_lpass_noc },
1595
1593
};
1596
1594
1597
1595
static struct qcom_icc_node srvc_niu_aml_noc = {
1598
1596
.name = "srvc_niu_aml_noc",
1599
-
.id = SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC,
1600
1597
.channels = 1,
1601
1598
.buswidth = 4,
1602
1599
};
1603
1600
1604
1601
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1605
1602
.name = "srvc_niu_lpass_agnoc",
1606
-
.id = SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC,
1607
1603
.channels = 1,
1608
1604
.buswidth = 4,
1609
1605
};
1610
1606
1611
1607
static struct qcom_icc_node ebi = {
1612
1608
.name = "ebi",
1613
-
.id = SC8280XP_SLAVE_EBI1,
1614
1609
.channels = 8,
1615
1610
.buswidth = 4,
1616
1611
};
1617
1612
1618
1613
static struct qcom_icc_node qns_mem_noc_hf = {
1619
1614
.name = "qns_mem_noc_hf",
1620
-
.id = SC8280XP_SLAVE_MNOC_HF_MEM_NOC,
1621
1615
.channels = 2,
1622
1616
.buswidth = 32,
1623
1617
.num_links = 1,
1624
-
.links = { SC8280XP_MASTER_MNOC_HF_MEM_NOC },
1618
+
.link_nodes = { &qnm_mnoc_hf },
1625
1619
};
1626
1620
1627
1621
static struct qcom_icc_node qns_mem_noc_sf = {
1628
1622
.name = "qns_mem_noc_sf",
1629
-
.id = SC8280XP_SLAVE_MNOC_SF_MEM_NOC,
1630
1623
.channels = 2,
1631
1624
.buswidth = 32,
1632
1625
.num_links = 1,
1633
-
.links = { SC8280XP_MASTER_MNOC_SF_MEM_NOC },
1626
+
.link_nodes = { &qnm_mnoc_sf },
1634
1627
};
1635
1628
1636
1629
static struct qcom_icc_node srvc_mnoc = {
1637
1630
.name = "srvc_mnoc",
1638
-
.id = SC8280XP_SLAVE_SERVICE_MNOC,
1639
1631
.channels = 1,
1640
1632
.buswidth = 4,
1641
1633
};
1642
1634
1643
1635
static struct qcom_icc_node qns_nsp_gemnoc = {
1644
1636
.name = "qns_nsp_gemnoc",
1645
-
.id = SC8280XP_SLAVE_CDSP_MEM_NOC,
1646
1637
.channels = 2,
1647
1638
.buswidth = 32,
1648
1639
.num_links = 1,
1649
-
.links = { SC8280XP_MASTER_COMPUTE_NOC },
1640
+
.link_nodes = { &qnm_cmpnoc0 },
1650
1641
};
1651
1642
1652
1643
static struct qcom_icc_node qxs_nsp_xfr = {
1653
1644
.name = "qxs_nsp_xfr",
1654
-
.id = SC8280XP_SLAVE_NSP_XFR,
1655
1645
.channels = 1,
1656
1646
.buswidth = 32,
1657
1647
};
1658
1648
1659
1649
static struct qcom_icc_node service_nsp_noc = {
1660
1650
.name = "service_nsp_noc",
1661
-
.id = SC8280XP_SLAVE_SERVICE_NSP_NOC,
1662
1651
.channels = 1,
1663
1652
.buswidth = 4,
1664
1653
};
1665
1654
1666
1655
static struct qcom_icc_node qns_nspb_gemnoc = {
1667
1656
.name = "qns_nspb_gemnoc",
1668
-
.id = SC8280XP_SLAVE_CDSPB_MEM_NOC,
1669
1657
.channels = 2,
1670
1658
.buswidth = 32,
1671
1659
.num_links = 1,
1672
-
.links = { SC8280XP_MASTER_COMPUTE_NOC_1 },
1660
+
.link_nodes = { &qnm_cmpnoc1 },
1673
1661
};
1674
1662
1675
1663
static struct qcom_icc_node qxs_nspb_xfr = {
1676
1664
.name = "qxs_nspb_xfr",
1677
-
.id = SC8280XP_SLAVE_NSPB_XFR,
1678
1665
.channels = 1,
1679
1666
.buswidth = 32,
1680
1667
};
1681
1668
1682
1669
static struct qcom_icc_node service_nspb_noc = {
1683
1670
.name = "service_nspb_noc",
1684
-
.id = SC8280XP_SLAVE_SERVICE_NSPB_NOC,
1685
1671
.channels = 1,
1686
1672
.buswidth = 4,
1687
1673
};
1688
1674
1689
1675
static struct qcom_icc_node qns_gemnoc_gc = {
1690
1676
.name = "qns_gemnoc_gc",
1691
-
.id = SC8280XP_SLAVE_SNOC_GEM_NOC_GC,
1692
1677
.channels = 1,
1693
1678
.buswidth = 8,
1694
1679
.num_links = 1,
1695
-
.links = { SC8280XP_MASTER_SNOC_GC_MEM_NOC },
1680
+
.link_nodes = { &qnm_snoc_gc },
1696
1681
};
1697
1682
1698
1683
static struct qcom_icc_node qns_gemnoc_sf = {
1699
1684
.name = "qns_gemnoc_sf",
1700
-
.id = SC8280XP_SLAVE_SNOC_GEM_NOC_SF,
1701
1685
.channels = 1,
1702
1686
.buswidth = 16,
1703
1687
.num_links = 1,
1704
-
.links = { SC8280XP_MASTER_SNOC_SF_MEM_NOC },
1688
+
.link_nodes = { &qnm_snoc_sf },
1705
1689
};
1706
1690
1707
1691
static struct qcom_icc_node srvc_snoc = {
1708
1692
.name = "srvc_snoc",
1709
-
.id = SC8280XP_SLAVE_SERVICE_SNOC,
1710
1693
.channels = 1,
1711
1694
.buswidth = 4,
1712
1695
};
···
1998
2015
};
1999
2016
2000
2017
static const struct qcom_icc_desc sc8280xp_aggre1_noc = {
2018
+
.alloc_dyn_id = true,
2001
2019
.nodes = aggre1_noc_nodes,
2002
2020
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
2003
2021
.bcms = aggre1_noc_bcms,
···
2035
2051
};
2036
2052
2037
2053
static const struct qcom_icc_desc sc8280xp_aggre2_noc = {
2054
+
.alloc_dyn_id = true,
2038
2055
.nodes = aggre2_noc_nodes,
2039
2056
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
2040
2057
.bcms = aggre2_noc_bcms,
···
2058
2073
};
2059
2074
2060
2075
static const struct qcom_icc_desc sc8280xp_clk_virt = {
2076
+
.alloc_dyn_id = true,
2061
2077
.nodes = clk_virt_nodes,
2062
2078
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
2063
2079
.bcms = clk_virt_bcms,
···
2163
2177
};
2164
2178
2165
2179
static const struct qcom_icc_desc sc8280xp_config_noc = {
2180
+
.alloc_dyn_id = true,
2166
2181
.nodes = config_noc_nodes,
2167
2182
.num_nodes = ARRAY_SIZE(config_noc_nodes),
2168
2183
.bcms = config_noc_bcms,
···
2180
2193
};
2181
2194
2182
2195
static const struct qcom_icc_desc sc8280xp_dc_noc = {
2196
+
.alloc_dyn_id = true,
2183
2197
.nodes = dc_noc_nodes,
2184
2198
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
2185
2199
.bcms = dc_noc_bcms,
···
2215
2227
};
2216
2228
2217
2229
static const struct qcom_icc_desc sc8280xp_gem_noc = {
2230
+
.alloc_dyn_id = true,
2218
2231
.nodes = gem_noc_nodes,
2219
2232
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
2220
2233
.bcms = gem_noc_bcms,
···
2239
2250
};
2240
2251
2241
2252
static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = {
2253
+
.alloc_dyn_id = true,
2242
2254
.nodes = lpass_ag_noc_nodes,
2243
2255
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2244
2256
.bcms = lpass_ag_noc_bcms,
···
2257
2267
};
2258
2268
2259
2269
static const struct qcom_icc_desc sc8280xp_mc_virt = {
2270
+
.alloc_dyn_id = true,
2260
2271
.nodes = mc_virt_nodes,
2261
2272
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
2262
2273
.bcms = mc_virt_bcms,
···
2289
2298
};
2290
2299
2291
2300
static const struct qcom_icc_desc sc8280xp_mmss_noc = {
2301
+
.alloc_dyn_id = true,
2292
2302
.nodes = mmss_noc_nodes,
2293
2303
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2294
2304
.bcms = mmss_noc_bcms,
···
2310
2318
};
2311
2319
2312
2320
static const struct qcom_icc_desc sc8280xp_nspa_noc = {
2321
+
.alloc_dyn_id = true,
2313
2322
.nodes = nspa_noc_nodes,
2314
2323
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2315
2324
.bcms = nspa_noc_bcms,
···
2331
2338
};
2332
2339
2333
2340
static const struct qcom_icc_desc sc8280xp_nspb_noc = {
2341
+
.alloc_dyn_id = true,
2334
2342
.nodes = nspb_noc_nodes,
2335
2343
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
2336
2344
.bcms = nspb_noc_bcms,
···
2361
2367
};
2362
2368
2363
2369
static const struct qcom_icc_desc sc8280xp_system_noc_main = {
2370
+
.alloc_dyn_id = true,
2364
2371
.nodes = system_noc_main_nodes,
2365
2372
.num_nodes = ARRAY_SIZE(system_noc_main_nodes),
2366
2373
.bcms = system_noc_main_bcms,
-209
drivers/interconnect/qcom/sc8280xp.h
-209
drivers/interconnect/qcom/sc8280xp.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
-
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
-
*/
5
-
6
-
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H
7
-
#define __DRIVERS_INTERCONNECT_QCOM_SC8280XP_H
8
-
9
-
#define SC8280XP_MASTER_GPU_TCU 0
10
-
#define SC8280XP_MASTER_PCIE_TCU 1
11
-
#define SC8280XP_MASTER_SYS_TCU 2
12
-
#define SC8280XP_MASTER_APPSS_PROC 3
13
-
/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
14
-
#define SC8280XP_MASTER_LLCC 5
15
-
#define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6
16
-
#define SC8280XP_MASTER_CDSP_NOC_CFG 7
17
-
#define SC8280XP_MASTER_CDSPB_NOC_CFG 8
18
-
#define SC8280XP_MASTER_QDSS_BAM 9
19
-
#define SC8280XP_MASTER_QSPI_0 10
20
-
#define SC8280XP_MASTER_QUP_0 11
21
-
#define SC8280XP_MASTER_QUP_1 12
22
-
#define SC8280XP_MASTER_QUP_2 13
23
-
#define SC8280XP_MASTER_A1NOC_CFG 14
24
-
#define SC8280XP_MASTER_A2NOC_CFG 15
25
-
#define SC8280XP_MASTER_A1NOC_SNOC 16
26
-
#define SC8280XP_MASTER_A2NOC_SNOC 17
27
-
#define SC8280XP_MASTER_USB_NOC_SNOC 18
28
-
#define SC8280XP_MASTER_CAMNOC_HF 19
29
-
#define SC8280XP_MASTER_COMPUTE_NOC 20
30
-
#define SC8280XP_MASTER_COMPUTE_NOC_1 21
31
-
#define SC8280XP_MASTER_CNOC_DC_NOC 22
32
-
#define SC8280XP_MASTER_GEM_NOC_CFG 23
33
-
#define SC8280XP_MASTER_GEM_NOC_CNOC 24
34
-
#define SC8280XP_MASTER_GEM_NOC_PCIE_SNOC 25
35
-
#define SC8280XP_MASTER_GFX3D 26
36
-
#define SC8280XP_MASTER_LPASS_ANOC 27
37
-
#define SC8280XP_MASTER_MDP0 28
38
-
#define SC8280XP_MASTER_MDP1 29
39
-
#define SC8280XP_MASTER_MDP_CORE1_0 30
40
-
#define SC8280XP_MASTER_MDP_CORE1_1 31
41
-
#define SC8280XP_MASTER_CNOC_MNOC_CFG 32
42
-
#define SC8280XP_MASTER_MNOC_HF_MEM_NOC 33
43
-
#define SC8280XP_MASTER_MNOC_SF_MEM_NOC 34
44
-
#define SC8280XP_MASTER_ANOC_PCIE_GEM_NOC 35
45
-
#define SC8280XP_MASTER_ROTATOR 36
46
-
#define SC8280XP_MASTER_ROTATOR_1 37
47
-
#define SC8280XP_MASTER_SNOC_CFG 38
48
-
#define SC8280XP_MASTER_SNOC_GC_MEM_NOC 39
49
-
#define SC8280XP_MASTER_SNOC_SF_MEM_NOC 40
50
-
#define SC8280XP_MASTER_VIDEO_P0 41
51
-
#define SC8280XP_MASTER_VIDEO_P1 42
52
-
#define SC8280XP_MASTER_VIDEO_PROC 43
53
-
#define SC8280XP_MASTER_QUP_CORE_0 44
54
-
#define SC8280XP_MASTER_QUP_CORE_1 45
55
-
#define SC8280XP_MASTER_QUP_CORE_2 46
56
-
#define SC8280XP_MASTER_CAMNOC_ICP 47
57
-
#define SC8280XP_MASTER_CAMNOC_SF 48
58
-
#define SC8280XP_MASTER_CRYPTO 49
59
-
#define SC8280XP_MASTER_IPA 50
60
-
#define SC8280XP_MASTER_LPASS_PROC 51
61
-
#define SC8280XP_MASTER_CDSP_PROC 52
62
-
#define SC8280XP_MASTER_CDSP_PROC_B 53
63
-
#define SC8280XP_MASTER_PIMEM 54
64
-
#define SC8280XP_MASTER_SENSORS_PROC 55
65
-
#define SC8280XP_MASTER_SP 56
66
-
#define SC8280XP_MASTER_EMAC 57
67
-
#define SC8280XP_MASTER_EMAC_1 58
68
-
#define SC8280XP_MASTER_GIC 59
69
-
#define SC8280XP_MASTER_PCIE_0 60
70
-
#define SC8280XP_MASTER_PCIE_1 61
71
-
#define SC8280XP_MASTER_PCIE_2A 62
72
-
#define SC8280XP_MASTER_PCIE_2B 63
73
-
#define SC8280XP_MASTER_PCIE_3A 64
74
-
#define SC8280XP_MASTER_PCIE_3B 65
75
-
#define SC8280XP_MASTER_PCIE_4 66
76
-
#define SC8280XP_MASTER_QDSS_ETR 67
77
-
#define SC8280XP_MASTER_SDCC_2 68
78
-
#define SC8280XP_MASTER_SDCC_4 69
79
-
#define SC8280XP_MASTER_UFS_CARD 70
80
-
#define SC8280XP_MASTER_UFS_MEM 71
81
-
#define SC8280XP_MASTER_USB3_0 72
82
-
#define SC8280XP_MASTER_USB3_1 73
83
-
#define SC8280XP_MASTER_USB3_MP 74
84
-
#define SC8280XP_MASTER_USB4_0 75
85
-
#define SC8280XP_MASTER_USB4_1 76
86
-
#define SC8280XP_SLAVE_EBI1 512
87
-
/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
88
-
#define SC8280XP_SLAVE_AHB2PHY_0 514
89
-
#define SC8280XP_SLAVE_AHB2PHY_1 515
90
-
#define SC8280XP_SLAVE_AHB2PHY_2 516
91
-
#define SC8280XP_SLAVE_AOSS 517
92
-
#define SC8280XP_SLAVE_APPSS 518
93
-
#define SC8280XP_SLAVE_CAMERA_CFG 519
94
-
#define SC8280XP_SLAVE_CLK_CTL 520
95
-
#define SC8280XP_SLAVE_CDSP_CFG 521
96
-
#define SC8280XP_SLAVE_CDSP1_CFG 522
97
-
#define SC8280XP_SLAVE_RBCPR_CX_CFG 523
98
-
#define SC8280XP_SLAVE_RBCPR_MMCX_CFG 524
99
-
#define SC8280XP_SLAVE_RBCPR_MX_CFG 525
100
-
#define SC8280XP_SLAVE_CPR_NSPCX 526
101
-
#define SC8280XP_SLAVE_CRYPTO_0_CFG 527
102
-
#define SC8280XP_SLAVE_CX_RDPM 528
103
-
#define SC8280XP_SLAVE_DCC_CFG 529
104
-
#define SC8280XP_SLAVE_DISPLAY_CFG 530
105
-
#define SC8280XP_SLAVE_DISPLAY1_CFG 531
106
-
#define SC8280XP_SLAVE_EMAC_CFG 532
107
-
#define SC8280XP_SLAVE_EMAC1_CFG 533
108
-
#define SC8280XP_SLAVE_GFX3D_CFG 534
109
-
#define SC8280XP_SLAVE_HWKM 535
110
-
#define SC8280XP_SLAVE_IMEM_CFG 536
111
-
#define SC8280XP_SLAVE_IPA_CFG 537
112
-
#define SC8280XP_SLAVE_IPC_ROUTER_CFG 538
113
-
#define SC8280XP_SLAVE_LLCC_CFG 539
114
-
#define SC8280XP_SLAVE_LPASS 540
115
-
#define SC8280XP_SLAVE_LPASS_CORE_CFG 541
116
-
#define SC8280XP_SLAVE_LPASS_LPI_CFG 542
117
-
#define SC8280XP_SLAVE_LPASS_MPU_CFG 543
118
-
#define SC8280XP_SLAVE_LPASS_TOP_CFG 544
119
-
#define SC8280XP_SLAVE_MX_RDPM 545
120
-
#define SC8280XP_SLAVE_MXC_RDPM 546
121
-
#define SC8280XP_SLAVE_PCIE_0_CFG 547
122
-
#define SC8280XP_SLAVE_PCIE_1_CFG 548
123
-
#define SC8280XP_SLAVE_PCIE_2A_CFG 549
124
-
#define SC8280XP_SLAVE_PCIE_2B_CFG 550
125
-
#define SC8280XP_SLAVE_PCIE_3A_CFG 551
126
-
#define SC8280XP_SLAVE_PCIE_3B_CFG 552
127
-
#define SC8280XP_SLAVE_PCIE_4_CFG 553
128
-
#define SC8280XP_SLAVE_PCIE_RSC_CFG 554
129
-
#define SC8280XP_SLAVE_PDM 555
130
-
#define SC8280XP_SLAVE_PIMEM_CFG 556
131
-
#define SC8280XP_SLAVE_PKA_WRAPPER_CFG 557
132
-
#define SC8280XP_SLAVE_PMU_WRAPPER_CFG 558
133
-
#define SC8280XP_SLAVE_QDSS_CFG 559
134
-
#define SC8280XP_SLAVE_QSPI_0 560
135
-
#define SC8280XP_SLAVE_QUP_0 561
136
-
#define SC8280XP_SLAVE_QUP_1 562
137
-
#define SC8280XP_SLAVE_QUP_2 563
138
-
#define SC8280XP_SLAVE_SDCC_2 564
139
-
#define SC8280XP_SLAVE_SDCC_4 565
140
-
#define SC8280XP_SLAVE_SECURITY 566
141
-
#define SC8280XP_SLAVE_SMMUV3_CFG 567
142
-
#define SC8280XP_SLAVE_SMSS_CFG 568
143
-
#define SC8280XP_SLAVE_SPSS_CFG 569
144
-
#define SC8280XP_SLAVE_TCSR 570
145
-
#define SC8280XP_SLAVE_TLMM 571
146
-
#define SC8280XP_SLAVE_UFS_CARD_CFG 572
147
-
#define SC8280XP_SLAVE_UFS_MEM_CFG 573
148
-
#define SC8280XP_SLAVE_USB3_0 574
149
-
#define SC8280XP_SLAVE_USB3_1 575
150
-
#define SC8280XP_SLAVE_USB3_MP 576
151
-
#define SC8280XP_SLAVE_USB4_0 577
152
-
#define SC8280XP_SLAVE_USB4_1 578
153
-
#define SC8280XP_SLAVE_VENUS_CFG 579
154
-
#define SC8280XP_SLAVE_VSENSE_CTRL_CFG 580
155
-
#define SC8280XP_SLAVE_VSENSE_CTRL_R_CFG 581
156
-
#define SC8280XP_SLAVE_A1NOC_CFG 582
157
-
#define SC8280XP_SLAVE_A1NOC_SNOC 583
158
-
#define SC8280XP_SLAVE_A2NOC_CFG 584
159
-
#define SC8280XP_SLAVE_A2NOC_SNOC 585
160
-
#define SC8280XP_SLAVE_USB_NOC_SNOC 586
161
-
#define SC8280XP_SLAVE_ANOC_PCIE_BRIDGE_CFG 587
162
-
#define SC8280XP_SLAVE_DDRSS_CFG 588
163
-
#define SC8280XP_SLAVE_GEM_NOC_CNOC 589
164
-
#define SC8280XP_SLAVE_GEM_NOC_CFG 590
165
-
#define SC8280XP_SLAVE_SNOC_GEM_NOC_GC 591
166
-
#define SC8280XP_SLAVE_SNOC_GEM_NOC_SF 592
167
-
#define SC8280XP_SLAVE_LLCC 593
168
-
#define SC8280XP_SLAVE_MNOC_HF_MEM_NOC 594
169
-
#define SC8280XP_SLAVE_MNOC_SF_MEM_NOC 595
170
-
#define SC8280XP_SLAVE_CNOC_MNOC_CFG 596
171
-
#define SC8280XP_SLAVE_CDSP_MEM_NOC 597
172
-
#define SC8280XP_SLAVE_CDSPB_MEM_NOC 598
173
-
#define SC8280XP_SLAVE_GEM_NOC_PCIE_CNOC 599
174
-
#define SC8280XP_SLAVE_ANOC_PCIE_GEM_NOC 600
175
-
#define SC8280XP_SLAVE_SNOC_CFG 601
176
-
#define SC8280XP_SLAVE_SNOC_SF_BRIDGE_CFG 602
177
-
#define SC8280XP_SLAVE_LPASS_SNOC 603
178
-
#define SC8280XP_SLAVE_QUP_CORE_0 604
179
-
#define SC8280XP_SLAVE_QUP_CORE_1 605
180
-
#define SC8280XP_SLAVE_QUP_CORE_2 606
181
-
#define SC8280XP_SLAVE_IMEM 607
182
-
#define SC8280XP_SLAVE_NSP_XFR 608
183
-
#define SC8280XP_SLAVE_NSPB_XFR 609
184
-
#define SC8280XP_SLAVE_PIMEM 610
185
-
#define SC8280XP_SLAVE_SERVICE_NSP_NOC 611
186
-
#define SC8280XP_SLAVE_SERVICE_NSPB_NOC 612
187
-
#define SC8280XP_SLAVE_SERVICE_A1NOC 613
188
-
#define SC8280XP_SLAVE_SERVICE_A2NOC 614
189
-
#define SC8280XP_SLAVE_SERVICE_CNOC 615
190
-
#define SC8280XP_SLAVE_SERVICE_GEM_NOC_1 616
191
-
#define SC8280XP_SLAVE_SERVICE_MNOC 617
192
-
#define SC8280XP_SLAVE_SERVICES_LPASS_AML_NOC 618
193
-
#define SC8280XP_SLAVE_SERVICE_LPASS_AG_NOC 619
194
-
#define SC8280XP_SLAVE_SERVICE_GEM_NOC_2 620
195
-
#define SC8280XP_SLAVE_SERVICE_SNOC 621
196
-
#define SC8280XP_SLAVE_SERVICE_GEM_NOC 622
197
-
#define SC8280XP_SLAVE_PCIE_0 623
198
-
#define SC8280XP_SLAVE_PCIE_1 624
199
-
#define SC8280XP_SLAVE_PCIE_2A 625
200
-
#define SC8280XP_SLAVE_PCIE_2B 626
201
-
#define SC8280XP_SLAVE_PCIE_3A 627
202
-
#define SC8280XP_SLAVE_PCIE_3B 628
203
-
#define SC8280XP_SLAVE_PCIE_4 629
204
-
#define SC8280XP_SLAVE_QDSS_STM 630
205
-
#define SC8280XP_SLAVE_SMSS 631
206
-
#define SC8280XP_SLAVE_TCU 632
207
-
208
-
#endif
209
-