Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sc8180x: convert to dynamic IDs
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-rework-icc-v3-3-0575304c9624@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Georgi Djakov
ddf2ef52
93938e0c
+335
-503
+335
-324
drivers/interconnect/qcom/sc8180x.c
+335
-324
drivers/interconnect/qcom/sc8180x.c
···
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#include "bcm-voter.h"
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#include "icc-rpmh.h"
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#include "sc8180x.h"
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static struct qcom_icc_node mas_qhm_a1noc_cfg;
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static struct qcom_icc_node mas_xm_ufs_card;
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static struct qcom_icc_node mas_xm_ufs_g4;
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static struct qcom_icc_node mas_xm_ufs_mem;
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static struct qcom_icc_node mas_xm_usb3_0;
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static struct qcom_icc_node mas_xm_usb3_1;
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static struct qcom_icc_node mas_xm_usb3_2;
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static struct qcom_icc_node mas_qhm_a2noc_cfg;
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static struct qcom_icc_node mas_qhm_qdss_bam;
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static struct qcom_icc_node mas_qhm_qspi;
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static struct qcom_icc_node mas_qhm_qspi1;
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static struct qcom_icc_node mas_qhm_qup0;
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static struct qcom_icc_node mas_qhm_qup1;
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static struct qcom_icc_node mas_qhm_qup2;
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static struct qcom_icc_node mas_qhm_sensorss_ahb;
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static struct qcom_icc_node mas_qxm_crypto;
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static struct qcom_icc_node mas_qxm_ipa;
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static struct qcom_icc_node mas_xm_emac;
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static struct qcom_icc_node mas_xm_pcie3_0;
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static struct qcom_icc_node mas_xm_pcie3_1;
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static struct qcom_icc_node mas_xm_pcie3_2;
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static struct qcom_icc_node mas_xm_pcie3_3;
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static struct qcom_icc_node mas_xm_qdss_etr;
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static struct qcom_icc_node mas_xm_sdc2;
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static struct qcom_icc_node mas_xm_sdc4;
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static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp;
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static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp;
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static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp;
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static struct qcom_icc_node mas_qnm_npu;
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static struct qcom_icc_node mas_qnm_snoc;
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static struct qcom_icc_node mas_qhm_cnoc_dc_noc;
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static struct qcom_icc_node mas_acm_apps;
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static struct qcom_icc_node mas_acm_gpu_tcu;
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static struct qcom_icc_node mas_acm_sys_tcu;
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static struct qcom_icc_node mas_qhm_gemnoc_cfg;
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static struct qcom_icc_node mas_qnm_cmpnoc;
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static struct qcom_icc_node mas_qnm_gpu;
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static struct qcom_icc_node mas_qnm_mnoc_hf;
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static struct qcom_icc_node mas_qnm_mnoc_sf;
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static struct qcom_icc_node mas_qnm_pcie;
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static struct qcom_icc_node mas_qnm_snoc_gc;
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static struct qcom_icc_node mas_qnm_snoc_sf;
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static struct qcom_icc_node mas_qxm_ecc;
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static struct qcom_icc_node mas_llcc_mc;
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static struct qcom_icc_node mas_qhm_mnoc_cfg;
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static struct qcom_icc_node mas_qxm_camnoc_hf0;
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static struct qcom_icc_node mas_qxm_camnoc_hf1;
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static struct qcom_icc_node mas_qxm_camnoc_sf;
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static struct qcom_icc_node mas_qxm_mdp0;
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static struct qcom_icc_node mas_qxm_mdp1;
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static struct qcom_icc_node mas_qxm_rot;
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static struct qcom_icc_node mas_qxm_venus0;
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static struct qcom_icc_node mas_qxm_venus1;
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static struct qcom_icc_node mas_qxm_venus_arm9;
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static struct qcom_icc_node mas_qhm_snoc_cfg;
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static struct qcom_icc_node mas_qnm_aggre1_noc;
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static struct qcom_icc_node mas_qnm_aggre2_noc;
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static struct qcom_icc_node mas_qnm_gemnoc;
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static struct qcom_icc_node mas_qxm_pimem;
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static struct qcom_icc_node mas_xm_gic;
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static struct qcom_icc_node mas_qup_core_0;
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static struct qcom_icc_node mas_qup_core_1;
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static struct qcom_icc_node mas_qup_core_2;
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static struct qcom_icc_node slv_qns_a1noc_snoc;
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static struct qcom_icc_node slv_srvc_aggre1_noc;
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static struct qcom_icc_node slv_qns_a2noc_snoc;
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static struct qcom_icc_node slv_qns_pcie_mem_noc;
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static struct qcom_icc_node slv_srvc_aggre2_noc;
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static struct qcom_icc_node slv_qns_camnoc_uncomp;
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static struct qcom_icc_node slv_qns_cdsp_mem_noc;
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static struct qcom_icc_node slv_qhs_a1_noc_cfg;
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static struct qcom_icc_node slv_qhs_a2_noc_cfg;
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static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center;
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static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east;
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static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west;
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static struct qcom_icc_node slv_qhs_ahb2phy_south;
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static struct qcom_icc_node slv_qhs_aop;
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static struct qcom_icc_node slv_qhs_aoss;
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static struct qcom_icc_node slv_qhs_camera_cfg;
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static struct qcom_icc_node slv_qhs_clk_ctl;
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static struct qcom_icc_node slv_qhs_compute_dsp;
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static struct qcom_icc_node slv_qhs_cpr_cx;
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static struct qcom_icc_node slv_qhs_cpr_mmcx;
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static struct qcom_icc_node slv_qhs_cpr_mx;
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static struct qcom_icc_node slv_qhs_crypto0_cfg;
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static struct qcom_icc_node slv_qhs_ddrss_cfg;
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static struct qcom_icc_node slv_qhs_display_cfg;
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static struct qcom_icc_node slv_qhs_emac_cfg;
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static struct qcom_icc_node slv_qhs_glm;
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static struct qcom_icc_node slv_qhs_gpuss_cfg;
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static struct qcom_icc_node slv_qhs_imem_cfg;
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static struct qcom_icc_node slv_qhs_ipa;
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static struct qcom_icc_node slv_qhs_mnoc_cfg;
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static struct qcom_icc_node slv_qhs_npu_cfg;
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static struct qcom_icc_node slv_qhs_pcie0_cfg;
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static struct qcom_icc_node slv_qhs_pcie1_cfg;
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static struct qcom_icc_node slv_qhs_pcie2_cfg;
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static struct qcom_icc_node slv_qhs_pcie3_cfg;
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static struct qcom_icc_node slv_qhs_pdm;
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static struct qcom_icc_node slv_qhs_pimem_cfg;
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static struct qcom_icc_node slv_qhs_prng;
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static struct qcom_icc_node slv_qhs_qdss_cfg;
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static struct qcom_icc_node slv_qhs_qspi_0;
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static struct qcom_icc_node slv_qhs_qspi_1;
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static struct qcom_icc_node slv_qhs_qupv3_east0;
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static struct qcom_icc_node slv_qhs_qupv3_east1;
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static struct qcom_icc_node slv_qhs_qupv3_west;
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static struct qcom_icc_node slv_qhs_sdc2;
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static struct qcom_icc_node slv_qhs_sdc4;
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static struct qcom_icc_node slv_qhs_security;
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static struct qcom_icc_node slv_qhs_snoc_cfg;
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static struct qcom_icc_node slv_qhs_spss_cfg;
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static struct qcom_icc_node slv_qhs_tcsr;
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static struct qcom_icc_node slv_qhs_tlmm_east;
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static struct qcom_icc_node slv_qhs_tlmm_south;
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static struct qcom_icc_node slv_qhs_tlmm_west;
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static struct qcom_icc_node slv_qhs_tsif;
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static struct qcom_icc_node slv_qhs_ufs_card_cfg;
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static struct qcom_icc_node slv_qhs_ufs_mem0_cfg;
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static struct qcom_icc_node slv_qhs_ufs_mem1_cfg;
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static struct qcom_icc_node slv_qhs_usb3_0;
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static struct qcom_icc_node slv_qhs_usb3_1;
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static struct qcom_icc_node slv_qhs_usb3_2;
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static struct qcom_icc_node slv_qhs_venus_cfg;
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static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg;
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static struct qcom_icc_node slv_srvc_cnoc;
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static struct qcom_icc_node slv_qhs_gemnoc;
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static struct qcom_icc_node slv_qhs_llcc;
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static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg;
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static struct qcom_icc_node slv_qns_ecc;
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static struct qcom_icc_node slv_qns_gem_noc_snoc;
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static struct qcom_icc_node slv_qns_llcc;
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static struct qcom_icc_node slv_srvc_gemnoc;
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static struct qcom_icc_node slv_srvc_gemnoc1;
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static struct qcom_icc_node slv_ebi;
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static struct qcom_icc_node slv_qns2_mem_noc;
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static struct qcom_icc_node slv_qns_mem_noc_hf;
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static struct qcom_icc_node slv_srvc_mnoc;
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static struct qcom_icc_node slv_qhs_apss;
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static struct qcom_icc_node slv_qns_cnoc;
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static struct qcom_icc_node slv_qns_gemnoc_gc;
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static struct qcom_icc_node slv_qns_gemnoc_sf;
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static struct qcom_icc_node slv_qxs_imem;
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static struct qcom_icc_node slv_qxs_pimem;
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static struct qcom_icc_node slv_srvc_snoc;
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static struct qcom_icc_node slv_xs_pcie_0;
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static struct qcom_icc_node slv_xs_pcie_1;
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static struct qcom_icc_node slv_xs_pcie_2;
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static struct qcom_icc_node slv_xs_pcie_3;
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static struct qcom_icc_node slv_xs_qdss_stm;
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static struct qcom_icc_node slv_xs_sys_tcu_cfg;
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static struct qcom_icc_node slv_qup_core_0;
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static struct qcom_icc_node slv_qup_core_1;
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static struct qcom_icc_node slv_qup_core_2;
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static struct qcom_icc_node mas_qhm_a1noc_cfg = {
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.name = "mas_qhm_a1noc_cfg",
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.id = SC8180X_MASTER_A1NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_SLAVE_SERVICE_A1NOC }
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.link_nodes = { &slv_srvc_aggre1_noc },
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};
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static struct qcom_icc_node mas_xm_ufs_card = {
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.name = "mas_xm_ufs_card",
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.id = SC8180X_MASTER_UFS_CARD,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A1NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a1noc_snoc },
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};
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static struct qcom_icc_node mas_xm_ufs_g4 = {
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.name = "mas_xm_ufs_g4",
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.id = SC8180X_MASTER_UFS_GEN4,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A1NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a1noc_snoc },
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};
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static struct qcom_icc_node mas_xm_ufs_mem = {
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.name = "mas_xm_ufs_mem",
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.id = SC8180X_MASTER_UFS_MEM,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A1NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a1noc_snoc },
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};
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static struct qcom_icc_node mas_xm_usb3_0 = {
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.name = "mas_xm_usb3_0",
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.id = SC8180X_MASTER_USB3,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A1NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a1noc_snoc },
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};
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static struct qcom_icc_node mas_xm_usb3_1 = {
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.name = "mas_xm_usb3_1",
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.id = SC8180X_MASTER_USB3_1,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A1NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a1noc_snoc },
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};
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static struct qcom_icc_node mas_xm_usb3_2 = {
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.name = "mas_xm_usb3_2",
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.id = SC8180X_MASTER_USB3_2,
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.channels = 1,
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.buswidth = 16,
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.num_links = 1,
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.links = { SC8180X_A1NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a1noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_a2noc_cfg = {
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.name = "mas_qhm_a2noc_cfg",
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.id = SC8180X_MASTER_A2NOC_CFG,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_SLAVE_SERVICE_A2NOC }
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.link_nodes = { &slv_srvc_aggre2_noc },
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};
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static struct qcom_icc_node mas_qhm_qdss_bam = {
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.name = "mas_qhm_qdss_bam",
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.id = SC8180X_MASTER_QDSS_BAM,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_qspi = {
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.name = "mas_qhm_qspi",
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.id = SC8180X_MASTER_QSPI_0,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_qspi1 = {
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.name = "mas_qhm_qspi1",
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.id = SC8180X_MASTER_QSPI_1,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_qup0 = {
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.name = "mas_qhm_qup0",
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.id = SC8180X_MASTER_QUP_0,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_qup1 = {
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.name = "mas_qhm_qup1",
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.id = SC8180X_MASTER_QUP_1,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_qup2 = {
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.name = "mas_qhm_qup2",
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.id = SC8180X_MASTER_QUP_2,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qhm_sensorss_ahb = {
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.name = "mas_qhm_sensorss_ahb",
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.id = SC8180X_MASTER_SENSORS_AHB,
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.channels = 1,
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.buswidth = 4,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qxm_crypto = {
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.name = "mas_qxm_crypto",
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.id = SC8180X_MASTER_CRYPTO_CORE_0,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_qxm_ipa = {
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.name = "mas_qxm_ipa",
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.id = SC8180X_MASTER_IPA,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_xm_emac = {
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.name = "mas_xm_emac",
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.id = SC8180X_MASTER_EMAC,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
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.links = { SC8180X_A2NOC_SNOC_SLV }
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.link_nodes = { &slv_qns_a2noc_snoc },
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};
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static struct qcom_icc_node mas_xm_pcie3_0 = {
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.name = "mas_xm_pcie3_0",
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.id = SC8180X_MASTER_PCIE,
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.channels = 1,
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.buswidth = 8,
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.num_links = 1,
187
-
.links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
322
+
.link_nodes = { &slv_qns_pcie_mem_noc },
188
323
};
189
324
190
325
static struct qcom_icc_node mas_xm_pcie3_1 = {
191
326
.name = "mas_xm_pcie3_1",
192
-
.id = SC8180X_MASTER_PCIE_1,
193
327
.channels = 1,
194
328
.buswidth = 16,
195
329
.num_links = 1,
196
-
.links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
330
+
.link_nodes = { &slv_qns_pcie_mem_noc },
197
331
};
198
332
199
333
static struct qcom_icc_node mas_xm_pcie3_2 = {
200
334
.name = "mas_xm_pcie3_2",
201
-
.id = SC8180X_MASTER_PCIE_2,
202
335
.channels = 1,
203
336
.buswidth = 8,
204
337
.num_links = 1,
205
-
.links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
338
+
.link_nodes = { &slv_qns_pcie_mem_noc },
206
339
};
207
340
208
341
static struct qcom_icc_node mas_xm_pcie3_3 = {
209
342
.name = "mas_xm_pcie3_3",
210
-
.id = SC8180X_MASTER_PCIE_3,
211
343
.channels = 1,
212
344
.buswidth = 16,
213
345
.num_links = 1,
214
-
.links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC }
346
+
.link_nodes = { &slv_qns_pcie_mem_noc },
215
347
};
216
348
217
349
static struct qcom_icc_node mas_xm_qdss_etr = {
218
350
.name = "mas_xm_qdss_etr",
219
-
.id = SC8180X_MASTER_QDSS_ETR,
220
351
.channels = 1,
221
352
.buswidth = 8,
222
353
.num_links = 1,
223
-
.links = { SC8180X_A2NOC_SNOC_SLV }
354
+
.link_nodes = { &slv_qns_a2noc_snoc },
224
355
};
225
356
226
357
static struct qcom_icc_node mas_xm_sdc2 = {
227
358
.name = "mas_xm_sdc2",
228
-
.id = SC8180X_MASTER_SDCC_2,
229
359
.channels = 1,
230
360
.buswidth = 8,
231
361
.num_links = 1,
232
-
.links = { SC8180X_A2NOC_SNOC_SLV }
362
+
.link_nodes = { &slv_qns_a2noc_snoc },
233
363
};
234
364
235
365
static struct qcom_icc_node mas_xm_sdc4 = {
236
366
.name = "mas_xm_sdc4",
237
-
.id = SC8180X_MASTER_SDCC_4,
238
367
.channels = 1,
239
368
.buswidth = 8,
240
369
.num_links = 1,
241
-
.links = { SC8180X_A2NOC_SNOC_SLV }
370
+
.link_nodes = { &slv_qns_a2noc_snoc },
242
371
};
243
372
244
373
static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = {
245
374
.name = "mas_qxm_camnoc_hf0_uncomp",
246
-
.id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP,
247
375
.channels = 1,
248
376
.buswidth = 32,
249
377
.num_links = 1,
250
-
.links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
378
+
.link_nodes = { &slv_qns_camnoc_uncomp },
251
379
};
252
380
253
381
static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = {
254
382
.name = "mas_qxm_camnoc_hf1_uncomp",
255
-
.id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP,
256
383
.channels = 1,
257
384
.buswidth = 32,
258
385
.num_links = 1,
259
-
.links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
386
+
.link_nodes = { &slv_qns_camnoc_uncomp },
260
387
};
261
388
262
389
static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = {
263
390
.name = "mas_qxm_camnoc_sf_uncomp",
264
-
.id = SC8180X_MASTER_CAMNOC_SF_UNCOMP,
265
391
.channels = 1,
266
392
.buswidth = 32,
267
393
.num_links = 1,
268
-
.links = { SC8180X_SLAVE_CAMNOC_UNCOMP }
394
+
.link_nodes = { &slv_qns_camnoc_uncomp },
269
395
};
270
396
271
397
static struct qcom_icc_node mas_qnm_npu = {
272
398
.name = "mas_qnm_npu",
273
-
.id = SC8180X_MASTER_NPU,
274
399
.channels = 1,
275
400
.buswidth = 32,
276
401
.num_links = 1,
277
-
.links = { SC8180X_SLAVE_CDSP_MEM_NOC }
402
+
.link_nodes = { &slv_qns_cdsp_mem_noc },
278
403
};
279
404
280
405
static struct qcom_icc_node mas_qnm_snoc = {
281
406
.name = "mas_qnm_snoc",
282
-
.id = SC8180X_SNOC_CNOC_MAS,
283
407
.channels = 1,
284
408
.buswidth = 8,
285
409
.num_links = 56,
286
-
.links = { SC8180X_SLAVE_TLMM_SOUTH,
287
-
SC8180X_SLAVE_CDSP_CFG,
288
-
SC8180X_SLAVE_SPSS_CFG,
289
-
SC8180X_SLAVE_CAMERA_CFG,
290
-
SC8180X_SLAVE_SDCC_4,
291
-
SC8180X_SLAVE_AHB2PHY_CENTER,
292
-
SC8180X_SLAVE_SDCC_2,
293
-
SC8180X_SLAVE_PCIE_2_CFG,
294
-
SC8180X_SLAVE_CNOC_MNOC_CFG,
295
-
SC8180X_SLAVE_EMAC_CFG,
296
-
SC8180X_SLAVE_QSPI_0,
297
-
SC8180X_SLAVE_QSPI_1,
298
-
SC8180X_SLAVE_TLMM_EAST,
299
-
SC8180X_SLAVE_SNOC_CFG,
300
-
SC8180X_SLAVE_AHB2PHY_EAST,
301
-
SC8180X_SLAVE_GLM,
302
-
SC8180X_SLAVE_PDM,
303
-
SC8180X_SLAVE_PCIE_1_CFG,
304
-
SC8180X_SLAVE_A2NOC_CFG,
305
-
SC8180X_SLAVE_QDSS_CFG,
306
-
SC8180X_SLAVE_DISPLAY_CFG,
307
-
SC8180X_SLAVE_TCSR,
308
-
SC8180X_SLAVE_UFS_MEM_0_CFG,
309
-
SC8180X_SLAVE_CNOC_DDRSS,
310
-
SC8180X_SLAVE_PCIE_0_CFG,
311
-
SC8180X_SLAVE_QUP_1,
312
-
SC8180X_SLAVE_QUP_2,
313
-
SC8180X_SLAVE_NPU_CFG,
314
-
SC8180X_SLAVE_CRYPTO_0_CFG,
315
-
SC8180X_SLAVE_GRAPHICS_3D_CFG,
316
-
SC8180X_SLAVE_VENUS_CFG,
317
-
SC8180X_SLAVE_TSIF,
318
-
SC8180X_SLAVE_IPA_CFG,
319
-
SC8180X_SLAVE_CLK_CTL,
320
-
SC8180X_SLAVE_SECURITY,
321
-
SC8180X_SLAVE_AOP,
322
-
SC8180X_SLAVE_AHB2PHY_WEST,
323
-
SC8180X_SLAVE_AHB2PHY_SOUTH,
324
-
SC8180X_SLAVE_SERVICE_CNOC,
325
-
SC8180X_SLAVE_UFS_CARD_CFG,
326
-
SC8180X_SLAVE_USB3_1,
327
-
SC8180X_SLAVE_USB3_2,
328
-
SC8180X_SLAVE_PCIE_3_CFG,
329
-
SC8180X_SLAVE_RBCPR_CX_CFG,
330
-
SC8180X_SLAVE_TLMM_WEST,
331
-
SC8180X_SLAVE_A1NOC_CFG,
332
-
SC8180X_SLAVE_AOSS,
333
-
SC8180X_SLAVE_PRNG,
334
-
SC8180X_SLAVE_VSENSE_CTRL_CFG,
335
-
SC8180X_SLAVE_QUP_0,
336
-
SC8180X_SLAVE_USB3,
337
-
SC8180X_SLAVE_RBCPR_MMCX_CFG,
338
-
SC8180X_SLAVE_PIMEM_CFG,
339
-
SC8180X_SLAVE_UFS_MEM_1_CFG,
340
-
SC8180X_SLAVE_RBCPR_MX_CFG,
341
-
SC8180X_SLAVE_IMEM_CFG }
410
+
.link_nodes = { &slv_qhs_tlmm_south,
411
+
&slv_qhs_compute_dsp,
412
+
&slv_qhs_spss_cfg,
413
+
&slv_qhs_camera_cfg,
414
+
&slv_qhs_sdc4,
415
+
&slv_qhs_ahb2phy_refgen_center,
416
+
&slv_qhs_sdc2,
417
+
&slv_qhs_pcie2_cfg,
418
+
&slv_qhs_mnoc_cfg,
419
+
&slv_qhs_emac_cfg,
420
+
&slv_qhs_qspi_0,
421
+
&slv_qhs_qspi_1,
422
+
&slv_qhs_tlmm_east,
423
+
&slv_qhs_snoc_cfg,
424
+
&slv_qhs_ahb2phy_refgen_east,
425
+
&slv_qhs_glm,
426
+
&slv_qhs_pdm,
427
+
&slv_qhs_pcie1_cfg,
428
+
&slv_qhs_a2_noc_cfg,
429
+
&slv_qhs_qdss_cfg,
430
+
&slv_qhs_display_cfg,
431
+
&slv_qhs_tcsr,
432
+
&slv_qhs_ufs_mem0_cfg,
433
+
&slv_qhs_ddrss_cfg,
434
+
&slv_qhs_pcie0_cfg,
435
+
&slv_qhs_qupv3_east0,
436
+
&slv_qhs_qupv3_east1,
437
+
&slv_qhs_npu_cfg,
438
+
&slv_qhs_crypto0_cfg,
439
+
&slv_qhs_gpuss_cfg,
440
+
&slv_qhs_venus_cfg,
441
+
&slv_qhs_tsif,
442
+
&slv_qhs_ipa,
443
+
&slv_qhs_clk_ctl,
444
+
&slv_qhs_security,
445
+
&slv_qhs_aop,
446
+
&slv_qhs_ahb2phy_refgen_west,
447
+
&slv_qhs_ahb2phy_south,
448
+
&slv_srvc_cnoc,
449
+
&slv_qhs_ufs_card_cfg,
450
+
&slv_qhs_usb3_1,
451
+
&slv_qhs_usb3_2,
452
+
&slv_qhs_pcie3_cfg,
453
+
&slv_qhs_cpr_cx,
454
+
&slv_qhs_tlmm_west,
455
+
&slv_qhs_a1_noc_cfg,
456
+
&slv_qhs_aoss,
457
+
&slv_qhs_prng,
458
+
&slv_qhs_vsense_ctrl_cfg,
459
+
&slv_qhs_qupv3_west,
460
+
&slv_qhs_usb3_0,
461
+
&slv_qhs_cpr_mmcx,
462
+
&slv_qhs_pimem_cfg,
463
+
&slv_qhs_ufs_mem1_cfg,
464
+
&slv_qhs_cpr_mx,
465
+
&slv_qhs_imem_cfg },
342
466
};
343
467
344
468
static struct qcom_icc_node mas_qhm_cnoc_dc_noc = {
345
469
.name = "mas_qhm_cnoc_dc_noc",
346
-
.id = SC8180X_MASTER_CNOC_DC_NOC,
347
470
.channels = 1,
348
471
.buswidth = 4,
349
472
.num_links = 2,
350
-
.links = { SC8180X_SLAVE_LLCC_CFG,
351
-
SC8180X_SLAVE_GEM_NOC_CFG }
473
+
.link_nodes = { &slv_qhs_llcc,
474
+
&slv_qhs_gemnoc },
352
475
};
353
476
354
477
static struct qcom_icc_node mas_acm_apps = {
355
478
.name = "mas_acm_apps",
356
-
.id = SC8180X_MASTER_AMPSS_M0,
357
479
.channels = 4,
358
480
.buswidth = 64,
359
481
.num_links = 3,
360
-
.links = { SC8180X_SLAVE_ECC,
361
-
SC8180X_SLAVE_LLCC,
362
-
SC8180X_SLAVE_GEM_NOC_SNOC }
482
+
.link_nodes = { &slv_qns_ecc,
483
+
&slv_qns_llcc,
484
+
&slv_qns_gem_noc_snoc },
363
485
};
364
486
365
487
static struct qcom_icc_node mas_acm_gpu_tcu = {
366
488
.name = "mas_acm_gpu_tcu",
367
-
.id = SC8180X_MASTER_GPU_TCU,
368
489
.channels = 1,
369
490
.buswidth = 8,
370
491
.num_links = 2,
371
-
.links = { SC8180X_SLAVE_LLCC,
372
-
SC8180X_SLAVE_GEM_NOC_SNOC }
492
+
.link_nodes = { &slv_qns_llcc,
493
+
&slv_qns_gem_noc_snoc },
373
494
};
374
495
375
496
static struct qcom_icc_node mas_acm_sys_tcu = {
376
497
.name = "mas_acm_sys_tcu",
377
-
.id = SC8180X_MASTER_SYS_TCU,
378
498
.channels = 1,
379
499
.buswidth = 8,
380
500
.num_links = 2,
381
-
.links = { SC8180X_SLAVE_LLCC,
382
-
SC8180X_SLAVE_GEM_NOC_SNOC }
501
+
.link_nodes = { &slv_qns_llcc,
502
+
&slv_qns_gem_noc_snoc },
383
503
};
384
504
385
505
static struct qcom_icc_node mas_qhm_gemnoc_cfg = {
386
506
.name = "mas_qhm_gemnoc_cfg",
387
-
.id = SC8180X_MASTER_GEM_NOC_CFG,
388
507
.channels = 1,
389
508
.buswidth = 4,
390
509
.num_links = 3,
391
-
.links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1,
392
-
SC8180X_SLAVE_SERVICE_GEM_NOC,
393
-
SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG }
510
+
.link_nodes = { &slv_srvc_gemnoc1,
511
+
&slv_srvc_gemnoc,
512
+
&slv_qhs_mdsp_ms_mpu_cfg },
394
513
};
395
514
396
515
static struct qcom_icc_node mas_qnm_cmpnoc = {
397
516
.name = "mas_qnm_cmpnoc",
398
-
.id = SC8180X_MASTER_COMPUTE_NOC,
399
517
.channels = 2,
400
518
.buswidth = 32,
401
519
.num_links = 3,
402
-
.links = { SC8180X_SLAVE_ECC,
403
-
SC8180X_SLAVE_LLCC,
404
-
SC8180X_SLAVE_GEM_NOC_SNOC }
520
+
.link_nodes = { &slv_qns_ecc,
521
+
&slv_qns_llcc,
522
+
&slv_qns_gem_noc_snoc },
405
523
};
406
524
407
525
static struct qcom_icc_node mas_qnm_gpu = {
408
526
.name = "mas_qnm_gpu",
409
-
.id = SC8180X_MASTER_GRAPHICS_3D,
410
527
.channels = 4,
411
528
.buswidth = 32,
412
529
.num_links = 2,
413
-
.links = { SC8180X_SLAVE_LLCC,
414
-
SC8180X_SLAVE_GEM_NOC_SNOC }
530
+
.link_nodes = { &slv_qns_llcc,
531
+
&slv_qns_gem_noc_snoc },
415
532
};
416
533
417
534
static struct qcom_icc_node mas_qnm_mnoc_hf = {
418
535
.name = "mas_qnm_mnoc_hf",
419
-
.id = SC8180X_MASTER_MNOC_HF_MEM_NOC,
420
536
.channels = 2,
421
537
.buswidth = 32,
422
538
.num_links = 1,
423
-
.links = { SC8180X_SLAVE_LLCC }
539
+
.link_nodes = { &slv_qns_llcc },
424
540
};
425
541
426
542
static struct qcom_icc_node mas_qnm_mnoc_sf = {
427
543
.name = "mas_qnm_mnoc_sf",
428
-
.id = SC8180X_MASTER_MNOC_SF_MEM_NOC,
429
544
.channels = 1,
430
545
.buswidth = 32,
431
546
.num_links = 2,
432
-
.links = { SC8180X_SLAVE_LLCC,
433
-
SC8180X_SLAVE_GEM_NOC_SNOC }
547
+
.link_nodes = { &slv_qns_llcc,
548
+
&slv_qns_gem_noc_snoc },
434
549
};
435
550
436
551
static struct qcom_icc_node mas_qnm_pcie = {
437
552
.name = "mas_qnm_pcie",
438
-
.id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC,
439
553
.channels = 1,
440
554
.buswidth = 32,
441
555
.num_links = 2,
442
-
.links = { SC8180X_SLAVE_LLCC,
443
-
SC8180X_SLAVE_GEM_NOC_SNOC }
556
+
.link_nodes = { &slv_qns_llcc,
557
+
&slv_qns_gem_noc_snoc },
444
558
};
445
559
446
560
static struct qcom_icc_node mas_qnm_snoc_gc = {
447
561
.name = "mas_qnm_snoc_gc",
448
-
.id = SC8180X_MASTER_SNOC_GC_MEM_NOC,
449
562
.channels = 1,
450
563
.buswidth = 8,
451
564
.num_links = 1,
452
-
.links = { SC8180X_SLAVE_LLCC }
565
+
.link_nodes = { &slv_qns_llcc },
453
566
};
454
567
455
568
static struct qcom_icc_node mas_qnm_snoc_sf = {
456
569
.name = "mas_qnm_snoc_sf",
457
-
.id = SC8180X_MASTER_SNOC_SF_MEM_NOC,
458
570
.channels = 1,
459
571
.buswidth = 32,
460
572
.num_links = 1,
461
-
.links = { SC8180X_SLAVE_LLCC }
573
+
.link_nodes = { &slv_qns_llcc },
462
574
};
463
575
464
576
static struct qcom_icc_node mas_qxm_ecc = {
465
577
.name = "mas_qxm_ecc",
466
-
.id = SC8180X_MASTER_ECC,
467
578
.channels = 2,
468
579
.buswidth = 32,
469
580
.num_links = 1,
470
-
.links = { SC8180X_SLAVE_LLCC }
581
+
.link_nodes = { &slv_qns_llcc },
471
582
};
472
583
473
584
static struct qcom_icc_node mas_llcc_mc = {
474
585
.name = "mas_llcc_mc",
475
-
.id = SC8180X_MASTER_LLCC,
476
586
.channels = 8,
477
587
.buswidth = 4,
478
588
.num_links = 1,
479
-
.links = { SC8180X_SLAVE_EBI_CH0 }
589
+
.link_nodes = { &slv_ebi },
480
590
};
481
591
482
592
static struct qcom_icc_node mas_qhm_mnoc_cfg = {
483
593
.name = "mas_qhm_mnoc_cfg",
484
-
.id = SC8180X_MASTER_CNOC_MNOC_CFG,
485
594
.channels = 1,
486
595
.buswidth = 4,
487
596
.num_links = 1,
488
-
.links = { SC8180X_SLAVE_SERVICE_MNOC }
597
+
.link_nodes = { &slv_srvc_mnoc },
489
598
};
490
599
491
600
static struct qcom_icc_node mas_qxm_camnoc_hf0 = {
492
601
.name = "mas_qxm_camnoc_hf0",
493
-
.id = SC8180X_MASTER_CAMNOC_HF0,
494
602
.channels = 1,
495
603
.buswidth = 32,
496
604
.num_links = 1,
497
-
.links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
605
+
.link_nodes = { &slv_qns_mem_noc_hf },
498
606
};
499
607
500
608
static struct qcom_icc_node mas_qxm_camnoc_hf1 = {
501
609
.name = "mas_qxm_camnoc_hf1",
502
-
.id = SC8180X_MASTER_CAMNOC_HF1,
503
610
.channels = 1,
504
611
.buswidth = 32,
505
612
.num_links = 1,
506
-
.links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
613
+
.link_nodes = { &slv_qns_mem_noc_hf },
507
614
};
508
615
509
616
static struct qcom_icc_node mas_qxm_camnoc_sf = {
510
617
.name = "mas_qxm_camnoc_sf",
511
-
.id = SC8180X_MASTER_CAMNOC_SF,
512
618
.channels = 1,
513
619
.buswidth = 32,
514
620
.num_links = 1,
515
-
.links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
621
+
.link_nodes = { &slv_qns2_mem_noc },
516
622
};
517
623
518
624
static struct qcom_icc_node mas_qxm_mdp0 = {
519
625
.name = "mas_qxm_mdp0",
520
-
.id = SC8180X_MASTER_MDP_PORT0,
521
626
.channels = 1,
522
627
.buswidth = 32,
523
628
.num_links = 1,
524
-
.links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
629
+
.link_nodes = { &slv_qns_mem_noc_hf },
525
630
};
526
631
527
632
static struct qcom_icc_node mas_qxm_mdp1 = {
528
633
.name = "mas_qxm_mdp1",
529
-
.id = SC8180X_MASTER_MDP_PORT1,
530
634
.channels = 1,
531
635
.buswidth = 32,
532
636
.num_links = 1,
533
-
.links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC }
637
+
.link_nodes = { &slv_qns_mem_noc_hf },
534
638
};
535
639
536
640
static struct qcom_icc_node mas_qxm_rot = {
537
641
.name = "mas_qxm_rot",
538
-
.id = SC8180X_MASTER_ROTATOR,
539
642
.channels = 1,
540
643
.buswidth = 32,
541
644
.num_links = 1,
542
-
.links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
645
+
.link_nodes = { &slv_qns2_mem_noc },
543
646
};
544
647
545
648
static struct qcom_icc_node mas_qxm_venus0 = {
546
649
.name = "mas_qxm_venus0",
547
-
.id = SC8180X_MASTER_VIDEO_P0,
548
650
.channels = 1,
549
651
.buswidth = 32,
550
652
.num_links = 1,
551
-
.links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
653
+
.link_nodes = { &slv_qns2_mem_noc },
552
654
};
553
655
554
656
static struct qcom_icc_node mas_qxm_venus1 = {
555
657
.name = "mas_qxm_venus1",
556
-
.id = SC8180X_MASTER_VIDEO_P1,
557
658
.channels = 1,
558
659
.buswidth = 32,
559
660
.num_links = 1,
560
-
.links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
661
+
.link_nodes = { &slv_qns2_mem_noc },
561
662
};
562
663
563
664
static struct qcom_icc_node mas_qxm_venus_arm9 = {
564
665
.name = "mas_qxm_venus_arm9",
565
-
.id = SC8180X_MASTER_VIDEO_PROC,
566
666
.channels = 1,
567
667
.buswidth = 8,
568
668
.num_links = 1,
569
-
.links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC }
669
+
.link_nodes = { &slv_qns2_mem_noc },
570
670
};
571
671
572
672
static struct qcom_icc_node mas_qhm_snoc_cfg = {
573
673
.name = "mas_qhm_snoc_cfg",
574
-
.id = SC8180X_MASTER_SNOC_CFG,
575
674
.channels = 1,
576
675
.buswidth = 4,
577
676
.num_links = 1,
578
-
.links = { SC8180X_SLAVE_SERVICE_SNOC }
677
+
.link_nodes = { &slv_srvc_snoc },
579
678
};
580
679
581
680
static struct qcom_icc_node mas_qnm_aggre1_noc = {
582
681
.name = "mas_qnm_aggre1_noc",
583
-
.id = SC8180X_A1NOC_SNOC_MAS,
584
682
.channels = 1,
585
683
.buswidth = 32,
586
684
.num_links = 6,
587
-
.links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF,
588
-
SC8180X_SLAVE_PIMEM,
589
-
SC8180X_SLAVE_OCIMEM,
590
-
SC8180X_SLAVE_APPSS,
591
-
SC8180X_SNOC_CNOC_SLV,
592
-
SC8180X_SLAVE_QDSS_STM }
685
+
.link_nodes = { &slv_qns_gemnoc_sf,
686
+
&slv_qxs_pimem,
687
+
&slv_qxs_imem,
688
+
&slv_qhs_apss,
689
+
&slv_qns_cnoc,
690
+
&slv_xs_qdss_stm },
593
691
};
594
692
595
693
static struct qcom_icc_node mas_qnm_aggre2_noc = {
596
694
.name = "mas_qnm_aggre2_noc",
597
-
.id = SC8180X_A2NOC_SNOC_MAS,
598
695
.channels = 1,
599
696
.buswidth = 16,
600
697
.num_links = 11,
601
-
.links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF,
602
-
SC8180X_SLAVE_PIMEM,
603
-
SC8180X_SLAVE_PCIE_3,
604
-
SC8180X_SLAVE_OCIMEM,
605
-
SC8180X_SLAVE_APPSS,
606
-
SC8180X_SLAVE_PCIE_2,
607
-
SC8180X_SNOC_CNOC_SLV,
608
-
SC8180X_SLAVE_PCIE_0,
609
-
SC8180X_SLAVE_PCIE_1,
610
-
SC8180X_SLAVE_TCU,
611
-
SC8180X_SLAVE_QDSS_STM }
698
+
.link_nodes = { &slv_qns_gemnoc_sf,
699
+
&slv_qxs_pimem,
700
+
&slv_xs_pcie_3,
701
+
&slv_qxs_imem,
702
+
&slv_qhs_apss,
703
+
&slv_xs_pcie_2,
704
+
&slv_qns_cnoc,
705
+
&slv_xs_pcie_0,
706
+
&slv_xs_pcie_1,
707
+
&slv_xs_sys_tcu_cfg,
708
+
&slv_xs_qdss_stm },
612
709
};
613
710
614
711
static struct qcom_icc_node mas_qnm_gemnoc = {
615
712
.name = "mas_qnm_gemnoc",
616
-
.id = SC8180X_MASTER_GEM_NOC_SNOC,
617
713
.channels = 1,
618
714
.buswidth = 8,
619
715
.num_links = 6,
620
-
.links = { SC8180X_SLAVE_PIMEM,
621
-
SC8180X_SLAVE_OCIMEM,
622
-
SC8180X_SLAVE_APPSS,
623
-
SC8180X_SNOC_CNOC_SLV,
624
-
SC8180X_SLAVE_TCU,
625
-
SC8180X_SLAVE_QDSS_STM }
716
+
.link_nodes = { &slv_qxs_pimem,
717
+
&slv_qxs_imem,
718
+
&slv_qhs_apss,
719
+
&slv_qns_cnoc,
720
+
&slv_xs_sys_tcu_cfg,
721
+
&slv_xs_qdss_stm },
626
722
};
627
723
628
724
static struct qcom_icc_node mas_qxm_pimem = {
629
725
.name = "mas_qxm_pimem",
630
-
.id = SC8180X_MASTER_PIMEM,
631
726
.channels = 1,
632
727
.buswidth = 8,
633
728
.num_links = 2,
634
-
.links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC,
635
-
SC8180X_SLAVE_OCIMEM }
729
+
.link_nodes = { &slv_qns_gemnoc_gc,
730
+
&slv_qxs_imem },
636
731
};
637
732
638
733
static struct qcom_icc_node mas_xm_gic = {
639
734
.name = "mas_xm_gic",
640
-
.id = SC8180X_MASTER_GIC,
641
735
.channels = 1,
642
736
.buswidth = 8,
643
737
.num_links = 2,
644
-
.links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC,
645
-
SC8180X_SLAVE_OCIMEM }
738
+
.link_nodes = { &slv_qns_gemnoc_gc,
739
+
&slv_qxs_imem },
646
740
};
647
741
648
742
static struct qcom_icc_node mas_qup_core_0 = {
649
743
.name = "mas_qup_core_0",
650
-
.id = SC8180X_MASTER_QUP_CORE_0,
651
744
.channels = 1,
652
745
.buswidth = 4,
653
746
.num_links = 1,
654
-
.links = { SC8180X_SLAVE_QUP_CORE_0 }
747
+
.link_nodes = { &slv_qup_core_0 },
655
748
};
656
749
657
750
static struct qcom_icc_node mas_qup_core_1 = {
658
751
.name = "mas_qup_core_1",
659
-
.id = SC8180X_MASTER_QUP_CORE_1,
660
752
.channels = 1,
661
753
.buswidth = 4,
662
754
.num_links = 1,
663
-
.links = { SC8180X_SLAVE_QUP_CORE_1 }
755
+
.link_nodes = { &slv_qup_core_1 },
664
756
};
665
757
666
758
static struct qcom_icc_node mas_qup_core_2 = {
667
759
.name = "mas_qup_core_2",
668
-
.id = SC8180X_MASTER_QUP_CORE_2,
669
760
.channels = 1,
670
761
.buswidth = 4,
671
762
.num_links = 1,
672
-
.links = { SC8180X_SLAVE_QUP_CORE_2 }
763
+
.link_nodes = { &slv_qup_core_2 },
673
764
};
674
765
675
766
static struct qcom_icc_node slv_qns_a1noc_snoc = {
676
767
.name = "slv_qns_a1noc_snoc",
677
-
.id = SC8180X_A1NOC_SNOC_SLV,
678
768
.channels = 1,
679
769
.buswidth = 32,
680
770
.num_links = 1,
681
-
.links = { SC8180X_A1NOC_SNOC_MAS }
771
+
.link_nodes = { &mas_qnm_aggre1_noc },
682
772
};
683
773
684
774
static struct qcom_icc_node slv_srvc_aggre1_noc = {
685
775
.name = "slv_srvc_aggre1_noc",
686
-
.id = SC8180X_SLAVE_SERVICE_A1NOC,
687
776
.channels = 1,
688
777
.buswidth = 4
689
778
};
690
779
691
780
static struct qcom_icc_node slv_qns_a2noc_snoc = {
692
781
.name = "slv_qns_a2noc_snoc",
693
-
.id = SC8180X_A2NOC_SNOC_SLV,
694
782
.channels = 1,
695
783
.buswidth = 16,
696
784
.num_links = 1,
697
-
.links = { SC8180X_A2NOC_SNOC_MAS }
785
+
.link_nodes = { &mas_qnm_aggre2_noc },
698
786
};
699
787
700
788
static struct qcom_icc_node slv_qns_pcie_mem_noc = {
701
789
.name = "slv_qns_pcie_mem_noc",
702
-
.id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC,
703
790
.channels = 1,
704
791
.buswidth = 32,
705
792
.num_links = 1,
706
-
.links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC }
793
+
.link_nodes = { &mas_qnm_pcie },
707
794
};
708
795
709
796
static struct qcom_icc_node slv_srvc_aggre2_noc = {
710
797
.name = "slv_srvc_aggre2_noc",
711
-
.id = SC8180X_SLAVE_SERVICE_A2NOC,
712
798
.channels = 1,
713
799
.buswidth = 4
714
800
};
715
801
716
802
static struct qcom_icc_node slv_qns_camnoc_uncomp = {
717
803
.name = "slv_qns_camnoc_uncomp",
718
-
.id = SC8180X_SLAVE_CAMNOC_UNCOMP,
719
804
.channels = 1,
720
805
.buswidth = 32
721
806
};
722
807
723
808
static struct qcom_icc_node slv_qns_cdsp_mem_noc = {
724
809
.name = "slv_qns_cdsp_mem_noc",
725
-
.id = SC8180X_SLAVE_CDSP_MEM_NOC,
726
810
.channels = 2,
727
811
.buswidth = 32,
728
812
.num_links = 1,
729
-
.links = { SC8180X_MASTER_COMPUTE_NOC }
813
+
.link_nodes = { &mas_qnm_cmpnoc },
730
814
};
731
815
732
816
static struct qcom_icc_node slv_qhs_a1_noc_cfg = {
733
817
.name = "slv_qhs_a1_noc_cfg",
734
-
.id = SC8180X_SLAVE_A1NOC_CFG,
735
818
.channels = 1,
736
819
.buswidth = 4,
737
820
.num_links = 1,
738
-
.links = { SC8180X_MASTER_A1NOC_CFG }
821
+
.link_nodes = { &mas_qhm_a1noc_cfg },
739
822
};
740
823
741
824
static struct qcom_icc_node slv_qhs_a2_noc_cfg = {
742
825
.name = "slv_qhs_a2_noc_cfg",
743
-
.id = SC8180X_SLAVE_A2NOC_CFG,
744
826
.channels = 1,
745
827
.buswidth = 4,
746
828
.num_links = 1,
747
-
.links = { SC8180X_MASTER_A2NOC_CFG }
829
+
.link_nodes = { &mas_qhm_a2noc_cfg },
748
830
};
749
831
750
832
static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = {
751
833
.name = "slv_qhs_ahb2phy_refgen_center",
752
-
.id = SC8180X_SLAVE_AHB2PHY_CENTER,
753
834
.channels = 1,
754
835
.buswidth = 4
755
836
};
756
837
757
838
static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = {
758
839
.name = "slv_qhs_ahb2phy_refgen_east",
759
-
.id = SC8180X_SLAVE_AHB2PHY_EAST,
760
840
.channels = 1,
761
841
.buswidth = 4
762
842
};
763
843
764
844
static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = {
765
845
.name = "slv_qhs_ahb2phy_refgen_west",
766
-
.id = SC8180X_SLAVE_AHB2PHY_WEST,
767
846
.channels = 1,
768
847
.buswidth = 4
769
848
};
770
849
771
850
static struct qcom_icc_node slv_qhs_ahb2phy_south = {
772
851
.name = "slv_qhs_ahb2phy_south",
773
-
.id = SC8180X_SLAVE_AHB2PHY_SOUTH,
774
852
.channels = 1,
775
853
.buswidth = 4
776
854
};
777
855
778
856
static struct qcom_icc_node slv_qhs_aop = {
779
857
.name = "slv_qhs_aop",
780
-
.id = SC8180X_SLAVE_AOP,
781
858
.channels = 1,
782
859
.buswidth = 4
783
860
};
784
861
785
862
static struct qcom_icc_node slv_qhs_aoss = {
786
863
.name = "slv_qhs_aoss",
787
-
.id = SC8180X_SLAVE_AOSS,
788
864
.channels = 1,
789
865
.buswidth = 4
790
866
};
791
867
792
868
static struct qcom_icc_node slv_qhs_camera_cfg = {
793
869
.name = "slv_qhs_camera_cfg",
794
-
.id = SC8180X_SLAVE_CAMERA_CFG,
795
870
.channels = 1,
796
871
.buswidth = 4
797
872
};
798
873
799
874
static struct qcom_icc_node slv_qhs_clk_ctl = {
800
875
.name = "slv_qhs_clk_ctl",
801
-
.id = SC8180X_SLAVE_CLK_CTL,
802
876
.channels = 1,
803
877
.buswidth = 4
804
878
};
805
879
806
880
static struct qcom_icc_node slv_qhs_compute_dsp = {
807
881
.name = "slv_qhs_compute_dsp",
808
-
.id = SC8180X_SLAVE_CDSP_CFG,
809
882
.channels = 1,
810
883
.buswidth = 4
811
884
};
812
885
813
886
static struct qcom_icc_node slv_qhs_cpr_cx = {
814
887
.name = "slv_qhs_cpr_cx",
815
-
.id = SC8180X_SLAVE_RBCPR_CX_CFG,
816
888
.channels = 1,
817
889
.buswidth = 4
818
890
};
819
891
820
892
static struct qcom_icc_node slv_qhs_cpr_mmcx = {
821
893
.name = "slv_qhs_cpr_mmcx",
822
-
.id = SC8180X_SLAVE_RBCPR_MMCX_CFG,
823
894
.channels = 1,
824
895
.buswidth = 4
825
896
};
826
897
827
898
static struct qcom_icc_node slv_qhs_cpr_mx = {
828
899
.name = "slv_qhs_cpr_mx",
829
-
.id = SC8180X_SLAVE_RBCPR_MX_CFG,
830
900
.channels = 1,
831
901
.buswidth = 4
832
902
};
833
903
834
904
static struct qcom_icc_node slv_qhs_crypto0_cfg = {
835
905
.name = "slv_qhs_crypto0_cfg",
836
-
.id = SC8180X_SLAVE_CRYPTO_0_CFG,
837
906
.channels = 1,
838
907
.buswidth = 4
839
908
};
840
909
841
910
static struct qcom_icc_node slv_qhs_ddrss_cfg = {
842
911
.name = "slv_qhs_ddrss_cfg",
843
-
.id = SC8180X_SLAVE_CNOC_DDRSS,
844
912
.channels = 1,
845
913
.buswidth = 4,
846
914
.num_links = 1,
847
-
.links = { SC8180X_MASTER_CNOC_DC_NOC }
915
+
.link_nodes = { &mas_qhm_cnoc_dc_noc },
848
916
};
849
917
850
918
static struct qcom_icc_node slv_qhs_display_cfg = {
851
919
.name = "slv_qhs_display_cfg",
852
-
.id = SC8180X_SLAVE_DISPLAY_CFG,
853
920
.channels = 1,
854
921
.buswidth = 4
855
922
};
856
923
857
924
static struct qcom_icc_node slv_qhs_emac_cfg = {
858
925
.name = "slv_qhs_emac_cfg",
859
-
.id = SC8180X_SLAVE_EMAC_CFG,
860
926
.channels = 1,
861
927
.buswidth = 4
862
928
};
863
929
864
930
static struct qcom_icc_node slv_qhs_glm = {
865
931
.name = "slv_qhs_glm",
866
-
.id = SC8180X_SLAVE_GLM,
867
932
.channels = 1,
868
933
.buswidth = 4
869
934
};
870
935
871
936
static struct qcom_icc_node slv_qhs_gpuss_cfg = {
872
937
.name = "slv_qhs_gpuss_cfg",
873
-
.id = SC8180X_SLAVE_GRAPHICS_3D_CFG,
874
938
.channels = 1,
875
939
.buswidth = 8
876
940
};
877
941
878
942
static struct qcom_icc_node slv_qhs_imem_cfg = {
879
943
.name = "slv_qhs_imem_cfg",
880
-
.id = SC8180X_SLAVE_IMEM_CFG,
881
944
.channels = 1,
882
945
.buswidth = 4
883
946
};
884
947
885
948
static struct qcom_icc_node slv_qhs_ipa = {
886
949
.name = "slv_qhs_ipa",
887
-
.id = SC8180X_SLAVE_IPA_CFG,
888
950
.channels = 1,
889
951
.buswidth = 4
890
952
};
891
953
892
954
static struct qcom_icc_node slv_qhs_mnoc_cfg = {
893
955
.name = "slv_qhs_mnoc_cfg",
894
-
.id = SC8180X_SLAVE_CNOC_MNOC_CFG,
895
956
.channels = 1,
896
957
.buswidth = 4,
897
958
.num_links = 1,
898
-
.links = { SC8180X_MASTER_CNOC_MNOC_CFG }
959
+
.link_nodes = { &mas_qhm_mnoc_cfg },
899
960
};
900
961
901
962
static struct qcom_icc_node slv_qhs_npu_cfg = {
902
963
.name = "slv_qhs_npu_cfg",
903
-
.id = SC8180X_SLAVE_NPU_CFG,
904
964
.channels = 1,
905
965
.buswidth = 4
906
966
};
907
967
908
968
static struct qcom_icc_node slv_qhs_pcie0_cfg = {
909
969
.name = "slv_qhs_pcie0_cfg",
910
-
.id = SC8180X_SLAVE_PCIE_0_CFG,
911
970
.channels = 1,
912
971
.buswidth = 4
913
972
};
914
973
915
974
static struct qcom_icc_node slv_qhs_pcie1_cfg = {
916
975
.name = "slv_qhs_pcie1_cfg",
917
-
.id = SC8180X_SLAVE_PCIE_1_CFG,
918
976
.channels = 1,
919
977
.buswidth = 4
920
978
};
921
979
922
980
static struct qcom_icc_node slv_qhs_pcie2_cfg = {
923
981
.name = "slv_qhs_pcie2_cfg",
924
-
.id = SC8180X_SLAVE_PCIE_2_CFG,
925
982
.channels = 1,
926
983
.buswidth = 4
927
984
};
928
985
929
986
static struct qcom_icc_node slv_qhs_pcie3_cfg = {
930
987
.name = "slv_qhs_pcie3_cfg",
931
-
.id = SC8180X_SLAVE_PCIE_3_CFG,
932
988
.channels = 1,
933
989
.buswidth = 4
934
990
};
935
991
936
992
static struct qcom_icc_node slv_qhs_pdm = {
937
993
.name = "slv_qhs_pdm",
938
-
.id = SC8180X_SLAVE_PDM,
939
994
.channels = 1,
940
995
.buswidth = 4
941
996
};
942
997
943
998
static struct qcom_icc_node slv_qhs_pimem_cfg = {
944
999
.name = "slv_qhs_pimem_cfg",
945
-
.id = SC8180X_SLAVE_PIMEM_CFG,
946
1000
.channels = 1,
947
1001
.buswidth = 4
948
1002
};
949
1003
950
1004
static struct qcom_icc_node slv_qhs_prng = {
951
1005
.name = "slv_qhs_prng",
952
-
.id = SC8180X_SLAVE_PRNG,
953
1006
.channels = 1,
954
1007
.buswidth = 4
955
1008
};
956
1009
957
1010
static struct qcom_icc_node slv_qhs_qdss_cfg = {
958
1011
.name = "slv_qhs_qdss_cfg",
959
-
.id = SC8180X_SLAVE_QDSS_CFG,
960
1012
.channels = 1,
961
1013
.buswidth = 4
962
1014
};
963
1015
964
1016
static struct qcom_icc_node slv_qhs_qspi_0 = {
965
1017
.name = "slv_qhs_qspi_0",
966
-
.id = SC8180X_SLAVE_QSPI_0,
967
1018
.channels = 1,
968
1019
.buswidth = 4
969
1020
};
970
1021
971
1022
static struct qcom_icc_node slv_qhs_qspi_1 = {
972
1023
.name = "slv_qhs_qspi_1",
973
-
.id = SC8180X_SLAVE_QSPI_1,
974
1024
.channels = 1,
975
1025
.buswidth = 4
976
1026
};
977
1027
978
1028
static struct qcom_icc_node slv_qhs_qupv3_east0 = {
979
1029
.name = "slv_qhs_qupv3_east0",
980
-
.id = SC8180X_SLAVE_QUP_1,
981
1030
.channels = 1,
982
1031
.buswidth = 4
983
1032
};
984
1033
985
1034
static struct qcom_icc_node slv_qhs_qupv3_east1 = {
986
1035
.name = "slv_qhs_qupv3_east1",
987
-
.id = SC8180X_SLAVE_QUP_2,
988
1036
.channels = 1,
989
1037
.buswidth = 4
990
1038
};
991
1039
992
1040
static struct qcom_icc_node slv_qhs_qupv3_west = {
993
1041
.name = "slv_qhs_qupv3_west",
994
-
.id = SC8180X_SLAVE_QUP_0,
995
1042
.channels = 1,
996
1043
.buswidth = 4
997
1044
};
998
1045
999
1046
static struct qcom_icc_node slv_qhs_sdc2 = {
1000
1047
.name = "slv_qhs_sdc2",
1001
-
.id = SC8180X_SLAVE_SDCC_2,
1002
1048
.channels = 1,
1003
1049
.buswidth = 4
1004
1050
};
1005
1051
1006
1052
static struct qcom_icc_node slv_qhs_sdc4 = {
1007
1053
.name = "slv_qhs_sdc4",
1008
-
.id = SC8180X_SLAVE_SDCC_4,
1009
1054
.channels = 1,
1010
1055
.buswidth = 4
1011
1056
};
1012
1057
1013
1058
static struct qcom_icc_node slv_qhs_security = {
1014
1059
.name = "slv_qhs_security",
1015
-
.id = SC8180X_SLAVE_SECURITY,
1016
1060
.channels = 1,
1017
1061
.buswidth = 4
1018
1062
};
1019
1063
1020
1064
static struct qcom_icc_node slv_qhs_snoc_cfg = {
1021
1065
.name = "slv_qhs_snoc_cfg",
1022
-
.id = SC8180X_SLAVE_SNOC_CFG,
1023
1066
.channels = 1,
1024
1067
.buswidth = 4,
1025
1068
.num_links = 1,
1026
-
.links = { SC8180X_MASTER_SNOC_CFG }
1069
+
.link_nodes = { &mas_qhm_snoc_cfg },
1027
1070
};
1028
1071
1029
1072
static struct qcom_icc_node slv_qhs_spss_cfg = {
1030
1073
.name = "slv_qhs_spss_cfg",
1031
-
.id = SC8180X_SLAVE_SPSS_CFG,
1032
1074
.channels = 1,
1033
1075
.buswidth = 4
1034
1076
};
1035
1077
1036
1078
static struct qcom_icc_node slv_qhs_tcsr = {
1037
1079
.name = "slv_qhs_tcsr",
1038
-
.id = SC8180X_SLAVE_TCSR,
1039
1080
.channels = 1,
1040
1081
.buswidth = 4
1041
1082
};
1042
1083
1043
1084
static struct qcom_icc_node slv_qhs_tlmm_east = {
1044
1085
.name = "slv_qhs_tlmm_east",
1045
-
.id = SC8180X_SLAVE_TLMM_EAST,
1046
1086
.channels = 1,
1047
1087
.buswidth = 4
1048
1088
};
1049
1089
1050
1090
static struct qcom_icc_node slv_qhs_tlmm_south = {
1051
1091
.name = "slv_qhs_tlmm_south",
1052
-
.id = SC8180X_SLAVE_TLMM_SOUTH,
1053
1092
.channels = 1,
1054
1093
.buswidth = 4
1055
1094
};
1056
1095
1057
1096
static struct qcom_icc_node slv_qhs_tlmm_west = {
1058
1097
.name = "slv_qhs_tlmm_west",
1059
-
.id = SC8180X_SLAVE_TLMM_WEST,
1060
1098
.channels = 1,
1061
1099
.buswidth = 4
1062
1100
};
1063
1101
1064
1102
static struct qcom_icc_node slv_qhs_tsif = {
1065
1103
.name = "slv_qhs_tsif",
1066
-
.id = SC8180X_SLAVE_TSIF,
1067
1104
.channels = 1,
1068
1105
.buswidth = 4
1069
1106
};
1070
1107
1071
1108
static struct qcom_icc_node slv_qhs_ufs_card_cfg = {
1072
1109
.name = "slv_qhs_ufs_card_cfg",
1073
-
.id = SC8180X_SLAVE_UFS_CARD_CFG,
1074
1110
.channels = 1,
1075
1111
.buswidth = 4
1076
1112
};
1077
1113
1078
1114
static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = {
1079
1115
.name = "slv_qhs_ufs_mem0_cfg",
1080
-
.id = SC8180X_SLAVE_UFS_MEM_0_CFG,
1081
1116
.channels = 1,
1082
1117
.buswidth = 4
1083
1118
};
1084
1119
1085
1120
static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = {
1086
1121
.name = "slv_qhs_ufs_mem1_cfg",
1087
-
.id = SC8180X_SLAVE_UFS_MEM_1_CFG,
1088
1122
.channels = 1,
1089
1123
.buswidth = 4
1090
1124
};
1091
1125
1092
1126
static struct qcom_icc_node slv_qhs_usb3_0 = {
1093
1127
.name = "slv_qhs_usb3_0",
1094
-
.id = SC8180X_SLAVE_USB3,
1095
1128
.channels = 1,
1096
1129
.buswidth = 4
1097
1130
};
1098
1131
1099
1132
static struct qcom_icc_node slv_qhs_usb3_1 = {
1100
1133
.name = "slv_qhs_usb3_1",
1101
-
.id = SC8180X_SLAVE_USB3_1,
1102
1134
.channels = 1,
1103
1135
.buswidth = 4
1104
1136
};
1105
1137
1106
1138
static struct qcom_icc_node slv_qhs_usb3_2 = {
1107
1139
.name = "slv_qhs_usb3_2",
1108
-
.id = SC8180X_SLAVE_USB3_2,
1109
1140
.channels = 1,
1110
1141
.buswidth = 4
1111
1142
};
1112
1143
1113
1144
static struct qcom_icc_node slv_qhs_venus_cfg = {
1114
1145
.name = "slv_qhs_venus_cfg",
1115
-
.id = SC8180X_SLAVE_VENUS_CFG,
1116
1146
.channels = 1,
1117
1147
.buswidth = 4
1118
1148
};
1119
1149
1120
1150
static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = {
1121
1151
.name = "slv_qhs_vsense_ctrl_cfg",
1122
-
.id = SC8180X_SLAVE_VSENSE_CTRL_CFG,
1123
1152
.channels = 1,
1124
1153
.buswidth = 4
1125
1154
};
1126
1155
1127
1156
static struct qcom_icc_node slv_srvc_cnoc = {
1128
1157
.name = "slv_srvc_cnoc",
1129
-
.id = SC8180X_SLAVE_SERVICE_CNOC,
1130
1158
.channels = 1,
1131
1159
.buswidth = 4
1132
1160
};
1133
1161
1134
1162
static struct qcom_icc_node slv_qhs_gemnoc = {
1135
1163
.name = "slv_qhs_gemnoc",
1136
-
.id = SC8180X_SLAVE_GEM_NOC_CFG,
1137
1164
.channels = 1,
1138
1165
.buswidth = 4,
1139
1166
.num_links = 1,
1140
-
.links = { SC8180X_MASTER_GEM_NOC_CFG }
1167
+
.link_nodes = { &mas_qhm_gemnoc_cfg },
1141
1168
};
1142
1169
1143
1170
static struct qcom_icc_node slv_qhs_llcc = {
1144
1171
.name = "slv_qhs_llcc",
1145
-
.id = SC8180X_SLAVE_LLCC_CFG,
1146
1172
.channels = 1,
1147
1173
.buswidth = 4
1148
1174
};
1149
1175
1150
1176
static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = {
1151
1177
.name = "slv_qhs_mdsp_ms_mpu_cfg",
1152
-
.id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG,
1153
1178
.channels = 1,
1154
1179
.buswidth = 4
1155
1180
};
1156
1181
1157
1182
static struct qcom_icc_node slv_qns_ecc = {
1158
1183
.name = "slv_qns_ecc",
1159
-
.id = SC8180X_SLAVE_ECC,
1160
1184
.channels = 1,
1161
1185
.buswidth = 32
1162
1186
};
1163
1187
1164
1188
static struct qcom_icc_node slv_qns_gem_noc_snoc = {
1165
1189
.name = "slv_qns_gem_noc_snoc",
1166
-
.id = SC8180X_SLAVE_GEM_NOC_SNOC,
1167
1190
.channels = 1,
1168
1191
.buswidth = 8,
1169
1192
.num_links = 1,
1170
-
.links = { SC8180X_MASTER_GEM_NOC_SNOC }
1193
+
.link_nodes = { &mas_qnm_gemnoc },
1171
1194
};
1172
1195
1173
1196
static struct qcom_icc_node slv_qns_llcc = {
1174
1197
.name = "slv_qns_llcc",
1175
-
.id = SC8180X_SLAVE_LLCC,
1176
1198
.channels = 8,
1177
1199
.buswidth = 16,
1178
1200
.num_links = 1,
1179
-
.links = { SC8180X_MASTER_LLCC }
1201
+
.link_nodes = { &mas_llcc_mc },
1180
1202
};
1181
1203
1182
1204
static struct qcom_icc_node slv_srvc_gemnoc = {
1183
1205
.name = "slv_srvc_gemnoc",
1184
-
.id = SC8180X_SLAVE_SERVICE_GEM_NOC,
1185
1206
.channels = 1,
1186
1207
.buswidth = 4
1187
1208
};
1188
1209
1189
1210
static struct qcom_icc_node slv_srvc_gemnoc1 = {
1190
1211
.name = "slv_srvc_gemnoc1",
1191
-
.id = SC8180X_SLAVE_SERVICE_GEM_NOC_1,
1192
1212
.channels = 1,
1193
1213
.buswidth = 4
1194
1214
};
1195
1215
1196
1216
static struct qcom_icc_node slv_ebi = {
1197
1217
.name = "slv_ebi",
1198
-
.id = SC8180X_SLAVE_EBI_CH0,
1199
1218
.channels = 8,
1200
1219
.buswidth = 4
1201
1220
};
1202
1221
1203
1222
static struct qcom_icc_node slv_qns2_mem_noc = {
1204
1223
.name = "slv_qns2_mem_noc",
1205
-
.id = SC8180X_SLAVE_MNOC_SF_MEM_NOC,
1206
1224
.channels = 1,
1207
1225
.buswidth = 32,
1208
1226
.num_links = 1,
1209
-
.links = { SC8180X_MASTER_MNOC_SF_MEM_NOC }
1227
+
.link_nodes = { &mas_qnm_mnoc_sf },
1210
1228
};
1211
1229
1212
1230
static struct qcom_icc_node slv_qns_mem_noc_hf = {
1213
1231
.name = "slv_qns_mem_noc_hf",
1214
-
.id = SC8180X_SLAVE_MNOC_HF_MEM_NOC,
1215
1232
.channels = 2,
1216
1233
.buswidth = 32,
1217
1234
.num_links = 1,
1218
-
.links = { SC8180X_MASTER_MNOC_HF_MEM_NOC }
1235
+
.link_nodes = { &mas_qnm_mnoc_hf },
1219
1236
};
1220
1237
1221
1238
static struct qcom_icc_node slv_srvc_mnoc = {
1222
1239
.name = "slv_srvc_mnoc",
1223
-
.id = SC8180X_SLAVE_SERVICE_MNOC,
1224
1240
.channels = 1,
1225
1241
.buswidth = 4
1226
1242
};
1227
1243
1228
1244
static struct qcom_icc_node slv_qhs_apss = {
1229
1245
.name = "slv_qhs_apss",
1230
-
.id = SC8180X_SLAVE_APPSS,
1231
1246
.channels = 1,
1232
1247
.buswidth = 8
1233
1248
};
1234
1249
1235
1250
static struct qcom_icc_node slv_qns_cnoc = {
1236
1251
.name = "slv_qns_cnoc",
1237
-
.id = SC8180X_SNOC_CNOC_SLV,
1238
1252
.channels = 1,
1239
1253
.buswidth = 8,
1240
1254
.num_links = 1,
1241
-
.links = { SC8180X_SNOC_CNOC_MAS }
1255
+
.link_nodes = { &mas_qnm_snoc },
1242
1256
};
1243
1257
1244
1258
static struct qcom_icc_node slv_qns_gemnoc_gc = {
1245
1259
.name = "slv_qns_gemnoc_gc",
1246
-
.id = SC8180X_SLAVE_SNOC_GEM_NOC_GC,
1247
1260
.channels = 1,
1248
1261
.buswidth = 8,
1249
1262
.num_links = 1,
1250
-
.links = { SC8180X_MASTER_SNOC_GC_MEM_NOC }
1263
+
.link_nodes = { &mas_qnm_snoc_gc },
1251
1264
};
1252
1265
1253
1266
static struct qcom_icc_node slv_qns_gemnoc_sf = {
1254
1267
.name = "slv_qns_gemnoc_sf",
1255
-
.id = SC8180X_SLAVE_SNOC_GEM_NOC_SF,
1256
1268
.channels = 1,
1257
1269
.buswidth = 32,
1258
1270
.num_links = 1,
1259
-
.links = { SC8180X_MASTER_SNOC_SF_MEM_NOC }
1271
+
.link_nodes = { &mas_qnm_snoc_sf },
1260
1272
};
1261
1273
1262
1274
static struct qcom_icc_node slv_qxs_imem = {
1263
1275
.name = "slv_qxs_imem",
1264
-
.id = SC8180X_SLAVE_OCIMEM,
1265
1276
.channels = 1,
1266
1277
.buswidth = 8
1267
1278
};
1268
1279
1269
1280
static struct qcom_icc_node slv_qxs_pimem = {
1270
1281
.name = "slv_qxs_pimem",
1271
-
.id = SC8180X_SLAVE_PIMEM,
1272
1282
.channels = 1,
1273
1283
.buswidth = 8
1274
1284
};
1275
1285
1276
1286
static struct qcom_icc_node slv_srvc_snoc = {
1277
1287
.name = "slv_srvc_snoc",
1278
-
.id = SC8180X_SLAVE_SERVICE_SNOC,
1279
1288
.channels = 1,
1280
1289
.buswidth = 4
1281
1290
};
1282
1291
1283
1292
static struct qcom_icc_node slv_xs_pcie_0 = {
1284
1293
.name = "slv_xs_pcie_0",
1285
-
.id = SC8180X_SLAVE_PCIE_0,
1286
1294
.channels = 1,
1287
1295
.buswidth = 8
1288
1296
};
1289
1297
1290
1298
static struct qcom_icc_node slv_xs_pcie_1 = {
1291
1299
.name = "slv_xs_pcie_1",
1292
-
.id = SC8180X_SLAVE_PCIE_1,
1293
1300
.channels = 1,
1294
1301
.buswidth = 8
1295
1302
};
1296
1303
1297
1304
static struct qcom_icc_node slv_xs_pcie_2 = {
1298
1305
.name = "slv_xs_pcie_2",
1299
-
.id = SC8180X_SLAVE_PCIE_2,
1300
1306
.channels = 1,
1301
1307
.buswidth = 8
1302
1308
};
1303
1309
1304
1310
static struct qcom_icc_node slv_xs_pcie_3 = {
1305
1311
.name = "slv_xs_pcie_3",
1306
-
.id = SC8180X_SLAVE_PCIE_3,
1307
1312
.channels = 1,
1308
1313
.buswidth = 8
1309
1314
};
1310
1315
1311
1316
static struct qcom_icc_node slv_xs_qdss_stm = {
1312
1317
.name = "slv_xs_qdss_stm",
1313
-
.id = SC8180X_SLAVE_QDSS_STM,
1314
1318
.channels = 1,
1315
1319
.buswidth = 4
1316
1320
};
1317
1321
1318
1322
static struct qcom_icc_node slv_xs_sys_tcu_cfg = {
1319
1323
.name = "slv_xs_sys_tcu_cfg",
1320
-
.id = SC8180X_SLAVE_TCU,
1321
1324
.channels = 1,
1322
1325
.buswidth = 8
1323
1326
};
1324
1327
1325
1328
static struct qcom_icc_node slv_qup_core_0 = {
1326
1329
.name = "slv_qup_core_0",
1327
-
.id = SC8180X_SLAVE_QUP_CORE_0,
1328
1330
.channels = 1,
1329
1331
.buswidth = 4
1330
1332
};
1331
1333
1332
1334
static struct qcom_icc_node slv_qup_core_1 = {
1333
1335
.name = "slv_qup_core_1",
1334
-
.id = SC8180X_SLAVE_QUP_CORE_1,
1335
1336
.channels = 1,
1336
1337
.buswidth = 4
1337
1338
};
1338
1339
1339
1340
static struct qcom_icc_node slv_qup_core_2 = {
1340
1341
.name = "slv_qup_core_2",
1341
-
.id = SC8180X_SLAVE_QUP_CORE_2,
1342
1342
.channels = 1,
1343
1343
.buswidth = 4
1344
1344
};
···
1790
1790
};
1791
1791
1792
1792
static const struct qcom_icc_desc sc8180x_aggre1_noc = {
1793
+
.alloc_dyn_id = true,
1793
1794
.nodes = aggre1_noc_nodes,
1794
1795
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1795
1796
.bcms = aggre1_noc_bcms,
···
1798
1797
};
1799
1798
1800
1799
static const struct qcom_icc_desc sc8180x_aggre2_noc = {
1800
+
.alloc_dyn_id = true,
1801
1801
.nodes = aggre2_noc_nodes,
1802
1802
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1803
1803
.bcms = aggre2_noc_bcms,
···
1806
1804
};
1807
1805
1808
1806
static const struct qcom_icc_desc sc8180x_camnoc_virt = {
1807
+
.alloc_dyn_id = true,
1809
1808
.nodes = camnoc_virt_nodes,
1810
1809
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1811
1810
.bcms = camnoc_virt_bcms,
···
1814
1811
};
1815
1812
1816
1813
static const struct qcom_icc_desc sc8180x_compute_noc = {
1814
+
.alloc_dyn_id = true,
1817
1815
.nodes = compute_noc_nodes,
1818
1816
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
1819
1817
.bcms = compute_noc_bcms,
···
1822
1818
};
1823
1819
1824
1820
static const struct qcom_icc_desc sc8180x_config_noc = {
1821
+
.alloc_dyn_id = true,
1825
1822
.nodes = config_noc_nodes,
1826
1823
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1827
1824
.bcms = config_noc_bcms,
···
1830
1825
};
1831
1826
1832
1827
static const struct qcom_icc_desc sc8180x_dc_noc = {
1828
+
.alloc_dyn_id = true,
1833
1829
.nodes = dc_noc_nodes,
1834
1830
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1835
1831
};
1836
1832
1837
1833
static const struct qcom_icc_desc sc8180x_gem_noc = {
1834
+
.alloc_dyn_id = true,
1838
1835
.nodes = gem_noc_nodes,
1839
1836
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1840
1837
.bcms = gem_noc_bcms,
···
1844
1837
};
1845
1838
1846
1839
static const struct qcom_icc_desc sc8180x_mc_virt = {
1840
+
.alloc_dyn_id = true,
1847
1841
.nodes = mc_virt_nodes,
1848
1842
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1849
1843
.bcms = mc_virt_bcms,
···
1852
1844
};
1853
1845
1854
1846
static const struct qcom_icc_desc sc8180x_mmss_noc = {
1847
+
.alloc_dyn_id = true,
1855
1848
.nodes = mmss_noc_nodes,
1856
1849
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1857
1850
.bcms = mmss_noc_bcms,
···
1860
1851
};
1861
1852
1862
1853
static const struct qcom_icc_desc sc8180x_system_noc = {
1854
+
.alloc_dyn_id = true,
1863
1855
.nodes = system_noc_nodes,
1864
1856
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1865
1857
.bcms = system_noc_bcms,
···
1881
1871
};
1882
1872
1883
1873
static const struct qcom_icc_desc sc8180x_qup_virt = {
1874
+
.alloc_dyn_id = true,
1884
1875
.nodes = qup_virt_nodes,
1885
1876
.num_nodes = ARRAY_SIZE(qup_virt_nodes),
1886
1877
.bcms = qup_virt_bcms,
-179
drivers/interconnect/qcom/sc8180x.h
-179
drivers/interconnect/qcom/sc8180x.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Qualcomm #define SC8180X interconnect IDs
4
-
*
5
-
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
6
-
*/
7
-
8
-
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
9
-
#define __DRIVERS_INTERCONNECT_QCOM_SC8180X_H
10
-
11
-
#define SC8180X_MASTER_A1NOC_CFG 1
12
-
#define SC8180X_MASTER_UFS_CARD 2
13
-
#define SC8180X_MASTER_UFS_GEN4 3
14
-
#define SC8180X_MASTER_UFS_MEM 4
15
-
#define SC8180X_MASTER_USB3 5
16
-
#define SC8180X_MASTER_USB3_1 6
17
-
#define SC8180X_MASTER_USB3_2 7
18
-
#define SC8180X_MASTER_A2NOC_CFG 8
19
-
#define SC8180X_MASTER_QDSS_BAM 9
20
-
#define SC8180X_MASTER_QSPI_0 10
21
-
#define SC8180X_MASTER_QSPI_1 11
22
-
#define SC8180X_MASTER_QUP_0 12
23
-
#define SC8180X_MASTER_QUP_1 13
24
-
#define SC8180X_MASTER_QUP_2 14
25
-
#define SC8180X_MASTER_SENSORS_AHB 15
26
-
#define SC8180X_MASTER_CRYPTO_CORE_0 16
27
-
#define SC8180X_MASTER_IPA 17
28
-
#define SC8180X_MASTER_EMAC 18
29
-
#define SC8180X_MASTER_PCIE 19
30
-
#define SC8180X_MASTER_PCIE_1 20
31
-
#define SC8180X_MASTER_PCIE_2 21
32
-
#define SC8180X_MASTER_PCIE_3 22
33
-
#define SC8180X_MASTER_QDSS_ETR 23
34
-
#define SC8180X_MASTER_SDCC_2 24
35
-
#define SC8180X_MASTER_SDCC_4 25
36
-
#define SC8180X_MASTER_CAMNOC_HF0_UNCOMP 26
37
-
#define SC8180X_MASTER_CAMNOC_HF1_UNCOMP 27
38
-
#define SC8180X_MASTER_CAMNOC_SF_UNCOMP 28
39
-
#define SC8180X_MASTER_NPU 29
40
-
#define SC8180X_SNOC_CNOC_MAS 30
41
-
#define SC8180X_MASTER_CNOC_DC_NOC 31
42
-
#define SC8180X_MASTER_AMPSS_M0 32
43
-
#define SC8180X_MASTER_GPU_TCU 33
44
-
#define SC8180X_MASTER_SYS_TCU 34
45
-
#define SC8180X_MASTER_GEM_NOC_CFG 35
46
-
#define SC8180X_MASTER_COMPUTE_NOC 36
47
-
#define SC8180X_MASTER_GRAPHICS_3D 37
48
-
#define SC8180X_MASTER_MNOC_HF_MEM_NOC 38
49
-
#define SC8180X_MASTER_MNOC_SF_MEM_NOC 39
50
-
#define SC8180X_MASTER_GEM_NOC_PCIE_SNOC 40
51
-
#define SC8180X_MASTER_SNOC_GC_MEM_NOC 41
52
-
#define SC8180X_MASTER_SNOC_SF_MEM_NOC 42
53
-
#define SC8180X_MASTER_ECC 43
54
-
/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */
55
-
#define SC8180X_MASTER_LLCC 45
56
-
#define SC8180X_MASTER_CNOC_MNOC_CFG 46
57
-
#define SC8180X_MASTER_CAMNOC_HF0 47
58
-
#define SC8180X_MASTER_CAMNOC_HF1 48
59
-
#define SC8180X_MASTER_CAMNOC_SF 49
60
-
#define SC8180X_MASTER_MDP_PORT0 50
61
-
#define SC8180X_MASTER_MDP_PORT1 51
62
-
#define SC8180X_MASTER_ROTATOR 52
63
-
#define SC8180X_MASTER_VIDEO_P0 53
64
-
#define SC8180X_MASTER_VIDEO_P1 54
65
-
#define SC8180X_MASTER_VIDEO_PROC 55
66
-
#define SC8180X_MASTER_SNOC_CFG 56
67
-
#define SC8180X_A1NOC_SNOC_MAS 57
68
-
#define SC8180X_A2NOC_SNOC_MAS 58
69
-
#define SC8180X_MASTER_GEM_NOC_SNOC 59
70
-
#define SC8180X_MASTER_PIMEM 60
71
-
#define SC8180X_MASTER_GIC 61
72
-
#define SC8180X_MASTER_MNOC_HF_MEM_NOC_DISPLAY 62
73
-
#define SC8180X_MASTER_MNOC_SF_MEM_NOC_DISPLAY 63
74
-
#define SC8180X_MASTER_LLCC_DISPLAY 64
75
-
#define SC8180X_MASTER_MDP_PORT0_DISPLAY 65
76
-
#define SC8180X_MASTER_MDP_PORT1_DISPLAY 66
77
-
#define SC8180X_MASTER_ROTATOR_DISPLAY 67
78
-
#define SC8180X_A1NOC_SNOC_SLV 68
79
-
#define SC8180X_SLAVE_SERVICE_A1NOC 69
80
-
#define SC8180X_A2NOC_SNOC_SLV 70
81
-
#define SC8180X_SLAVE_ANOC_PCIE_GEM_NOC 71
82
-
#define SC8180X_SLAVE_SERVICE_A2NOC 72
83
-
#define SC8180X_SLAVE_CAMNOC_UNCOMP 73
84
-
#define SC8180X_SLAVE_CDSP_MEM_NOC 74
85
-
#define SC8180X_SLAVE_A1NOC_CFG 75
86
-
#define SC8180X_SLAVE_A2NOC_CFG 76
87
-
#define SC8180X_SLAVE_AHB2PHY_CENTER 77
88
-
#define SC8180X_SLAVE_AHB2PHY_EAST 78
89
-
#define SC8180X_SLAVE_AHB2PHY_WEST 79
90
-
#define SC8180X_SLAVE_AHB2PHY_SOUTH 80
91
-
#define SC8180X_SLAVE_AOP 81
92
-
#define SC8180X_SLAVE_AOSS 82
93
-
#define SC8180X_SLAVE_CAMERA_CFG 83
94
-
#define SC8180X_SLAVE_CLK_CTL 84
95
-
#define SC8180X_SLAVE_CDSP_CFG 85
96
-
#define SC8180X_SLAVE_RBCPR_CX_CFG 86
97
-
#define SC8180X_SLAVE_RBCPR_MMCX_CFG 87
98
-
#define SC8180X_SLAVE_RBCPR_MX_CFG 88
99
-
#define SC8180X_SLAVE_CRYPTO_0_CFG 89
100
-
#define SC8180X_SLAVE_CNOC_DDRSS 90
101
-
#define SC8180X_SLAVE_DISPLAY_CFG 91
102
-
#define SC8180X_SLAVE_EMAC_CFG 92
103
-
#define SC8180X_SLAVE_GLM 93
104
-
#define SC8180X_SLAVE_GRAPHICS_3D_CFG 94
105
-
#define SC8180X_SLAVE_IMEM_CFG 95
106
-
#define SC8180X_SLAVE_IPA_CFG 96
107
-
#define SC8180X_SLAVE_CNOC_MNOC_CFG 97
108
-
#define SC8180X_SLAVE_NPU_CFG 98
109
-
#define SC8180X_SLAVE_PCIE_0_CFG 99
110
-
#define SC8180X_SLAVE_PCIE_1_CFG 100
111
-
#define SC8180X_SLAVE_PCIE_2_CFG 101
112
-
#define SC8180X_SLAVE_PCIE_3_CFG 102
113
-
#define SC8180X_SLAVE_PDM 103
114
-
#define SC8180X_SLAVE_PIMEM_CFG 104
115
-
#define SC8180X_SLAVE_PRNG 105
116
-
#define SC8180X_SLAVE_QDSS_CFG 106
117
-
#define SC8180X_SLAVE_QSPI_0 107
118
-
#define SC8180X_SLAVE_QSPI_1 108
119
-
#define SC8180X_SLAVE_QUP_1 109
120
-
#define SC8180X_SLAVE_QUP_2 110
121
-
#define SC8180X_SLAVE_QUP_0 111
122
-
#define SC8180X_SLAVE_SDCC_2 112
123
-
#define SC8180X_SLAVE_SDCC_4 113
124
-
#define SC8180X_SLAVE_SECURITY 114
125
-
#define SC8180X_SLAVE_SNOC_CFG 115
126
-
#define SC8180X_SLAVE_SPSS_CFG 116
127
-
#define SC8180X_SLAVE_TCSR 117
128
-
#define SC8180X_SLAVE_TLMM_EAST 118
129
-
#define SC8180X_SLAVE_TLMM_SOUTH 119
130
-
#define SC8180X_SLAVE_TLMM_WEST 120
131
-
#define SC8180X_SLAVE_TSIF 121
132
-
#define SC8180X_SLAVE_UFS_CARD_CFG 122
133
-
#define SC8180X_SLAVE_UFS_MEM_0_CFG 123
134
-
#define SC8180X_SLAVE_UFS_MEM_1_CFG 124
135
-
#define SC8180X_SLAVE_USB3 125
136
-
#define SC8180X_SLAVE_USB3_1 126
137
-
#define SC8180X_SLAVE_USB3_2 127
138
-
#define SC8180X_SLAVE_VENUS_CFG 128
139
-
#define SC8180X_SLAVE_VSENSE_CTRL_CFG 129
140
-
#define SC8180X_SLAVE_SERVICE_CNOC 130
141
-
#define SC8180X_SLAVE_GEM_NOC_CFG 131
142
-
#define SC8180X_SLAVE_LLCC_CFG 132
143
-
#define SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG 133
144
-
#define SC8180X_SLAVE_ECC 134
145
-
#define SC8180X_SLAVE_GEM_NOC_SNOC 135
146
-
#define SC8180X_SLAVE_LLCC 136
147
-
#define SC8180X_SLAVE_SERVICE_GEM_NOC 137
148
-
#define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138
149
-
/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */
150
-
#define SC8180X_SLAVE_EBI_CH0 140
151
-
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141
152
-
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142
153
-
#define SC8180X_SLAVE_SERVICE_MNOC 143
154
-
#define SC8180X_SLAVE_APPSS 144
155
-
#define SC8180X_SNOC_CNOC_SLV 145
156
-
#define SC8180X_SLAVE_SNOC_GEM_NOC_GC 146
157
-
#define SC8180X_SLAVE_SNOC_GEM_NOC_SF 147
158
-
#define SC8180X_SLAVE_OCIMEM 148
159
-
#define SC8180X_SLAVE_PIMEM 149
160
-
#define SC8180X_SLAVE_SERVICE_SNOC 150
161
-
#define SC8180X_SLAVE_PCIE_0 151
162
-
#define SC8180X_SLAVE_PCIE_1 152
163
-
#define SC8180X_SLAVE_PCIE_2 153
164
-
#define SC8180X_SLAVE_PCIE_3 154
165
-
#define SC8180X_SLAVE_QDSS_STM 155
166
-
#define SC8180X_SLAVE_TCU 156
167
-
#define SC8180X_SLAVE_LLCC_DISPLAY 157
168
-
#define SC8180X_SLAVE_EBI_CH0_DISPLAY 158
169
-
#define SC8180X_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 159
170
-
#define SC8180X_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 160
171
-
172
-
#define SC8180X_MASTER_QUP_CORE_0 163
173
-
#define SC8180X_MASTER_QUP_CORE_1 164
174
-
#define SC8180X_MASTER_QUP_CORE_2 165
175
-
#define SC8180X_SLAVE_QUP_CORE_0 166
176
-
#define SC8180X_SLAVE_QUP_CORE_1 167
177
-
#define SC8180X_SLAVE_QUP_CORE_2 168
178
-
179
-
#endif