Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
riscv: errata: Fix the PAUSE Opcode for MIPS P8700
Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.
Handle errata for the MIPS PAUSE instruction.
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com>
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-7-a6cbbe1c3412@htecgroup.com
[pjw@kernel.org: updated to apply and compile; fixed a checkpatch issue]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
authored by
Djordje Todorovic
and committed by
Paul Walmsley
0b0ca959
c9a9fc23
+127
-3
+23
arch/riscv/Kconfig.errata
+23
arch/riscv/Kconfig.errata
···
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If you don't know what to do here, say "Y".
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config ERRATA_MIPS
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bool "MIPS errata"
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depends on RISCV_ALTERNATIVE
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help
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All MIPS errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all MIPS errata. Please say "Y"
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here if your platform uses MIPS CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_MIPS_P8700_PAUSE_OPCODE
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bool "Fix the PAUSE Opcode for MIPS P8700"
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depends on ERRATA_MIPS && 64BIT
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default n
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help
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The RISCV MIPS P8700 uses a different opcode for PAUSE.
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It is a 'hint' encoding of the SLLI instruction,
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with rd=0, rs1=0 and imm=5. It will behave as a NOP
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instruction if no additional behavior beyond that of
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SLLI is implemented.
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If you are not using the P8700 processor, say n.
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config ERRATA_SIFIVE
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bool "SiFive errata"
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depends on RISCV_ALTERNATIVE
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arch/riscv/errata/Makefile
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arch/riscv/errata/Makefile
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arch/riscv/errata/mips/Makefile
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arch/riscv/errata/mips/Makefile
+67
arch/riscv/errata/mips/errata.c
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arch/riscv/errata/mips/errata.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025 MIPS.
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*/
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#include <linux/memory.h>
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#include <linux/module.h>
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#include <asm/text-patching.h>
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#include <asm/alternative.h>
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#include <asm/errata_list.h>
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#include <asm/vendorid_list.h>
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#include <asm/vendor_extensions.h>
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#include <asm/vendor_extensions/mips.h>
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static inline bool errata_probe_pause(void)
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{
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if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE))
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return false;
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if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL))
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return false;
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return true;
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}
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static u32 mips_errata_probe(void)
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{
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u32 cpu_req_errata = 0;
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if (errata_probe_pause())
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cpu_req_errata |= BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE);
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return cpu_req_errata;
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}
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void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid,
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unsigned int stage)
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{
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struct alt_entry *alt;
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u32 cpu_req_errata = mips_errata_probe();
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u32 tmp;
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BUILD_BUG_ON(ERRATA_MIPS_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
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if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
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return;
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for (alt = begin; alt < end; alt++) {
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if (alt->vendor_id != MIPS_VENDOR_ID)
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continue;
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if (alt->patch_id >= ERRATA_MIPS_NUMBER) {
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WARN(1, "MIPS errata id:%d not in kernel errata list\n",
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alt->patch_id);
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continue;
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}
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tmp = (1U << alt->patch_id);
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if (cpu_req_errata && tmp) {
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mutex_lock(&text_mutex);
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patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
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alt->alt_len);
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mutex_unlock(&text_mutex);
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}
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}
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}
+3
arch/riscv/include/asm/alternative.h
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arch/riscv/include/asm/alternative.h
···
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void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid,
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unsigned int stage);
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void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid,
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unsigned int stage);
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void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid,
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unsigned int stage);
+2
-1
arch/riscv/include/asm/cmpxchg.h
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-1
arch/riscv/include/asm/cmpxchg.h
···
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#include <asm/insn-def.h>
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#include <asm/cpufeature-macros.h>
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#include <asm/processor.h>
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#include <asm/errata_list.h>
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#define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \
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swap_append, r, p, n) \
···
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return;
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no_zawrs:
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asm volatile(RISCV_PAUSE : : : "memory");
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ALT_RISCV_PAUSE();
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}
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#define __cmpwait_relaxed(ptr, val) \
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-1
arch/riscv/include/asm/errata_list.h
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-1
arch/riscv/include/asm/errata_list.h
···
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#ifndef ASM_ERRATA_LIST_H
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#define ASM_ERRATA_LIST_H
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-
#include <asm/alternative.h>
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#include <asm/csr.h>
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#include <asm/insn-def.h>
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#include <asm/hwcap.h>
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#include <asm/vendorid_list.h>
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#include <asm/errata_list_vendors.h>
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#include <asm/vendor_extensions/mips.h>
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#ifdef __ASSEMBLER__
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···
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asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (addr), "r" (asid) : "memory")
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#define ALT_RISCV_PAUSE() \
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asm(ALTERNATIVE( \
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RISCV_PAUSE, /* Original RISC‑V pause insn */ \
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MIPS_PAUSE, /* Replacement for MIPS P8700 */ \
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MIPS_VENDOR_ID, /* Vendor ID to match */ \
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ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */ \
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CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE) \
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: /* no outputs */ \
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: /* no inputs */ \
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: "memory")
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/*
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* _val is marked as "will be overwritten", so need to set it to 0
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arch/riscv/include/asm/errata_list_vendors.h
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arch/riscv/include/asm/errata_list_vendors.h
+2
-1
arch/riscv/include/asm/vdso/processor.h
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-1
arch/riscv/include/asm/vdso/processor.h
···
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#ifndef __ASSEMBLER__
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#include <asm/barrier.h>
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#include <asm/errata_list.h>
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#include <asm/insn-def.h>
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static inline void cpu_relax(void)
···
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* Reduce instruction retirement.
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* This assumes the PC changes.
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*/
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__asm__ __volatile__ (RISCV_PAUSE);
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ALT_RISCV_PAUSE();
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barrier();
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}
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+5
arch/riscv/kernel/alternative.c
+5
arch/riscv/kernel/alternative.c
···
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cpu_mfr_info->patch_func = andes_errata_patch_func;
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break;
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#endif
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#ifdef CONFIG_ERRATA_MIPS
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case MIPS_VENDOR_ID:
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cpu_mfr_info->patch_func = mips_errata_patch_func;
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break;
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#endif
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#ifdef CONFIG_ERRATA_SIFIVE
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case SIFIVE_VENDOR_ID:
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cpu_mfr_info->patch_func = sifive_errata_patch_func;
+1
arch/riscv/kernel/entry.S
+1
arch/riscv/kernel/entry.S