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riscv: hwprobe: Document MIPS xmipsexectl vendor extension

Document support for MIPS vendor extensions using the key
"RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" and xmipsexectl vendor extension
using the key "RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL".

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-5-a6cbbe1c3412@htecgroup.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>

authored by

Aleksa Paunovic and committed by
Paul Walmsley
c9a9fc23 bb4b0f8a

+9
+9
Documentation/arch/riscv/hwprobe.rst
··· 327 327 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are 328 328 not supported at all and will generate a misaligned address fault. 329 329 330 + * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the 331 + mips vendor extensions that are compatible with the 332 + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. 333 + 334 + * MIPS 335 + 336 + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor 337 + extension is supported in the MIPS ISA extensions spec. 338 + 330 339 * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the 331 340 thead vendor extensions that are compatible with the 332 341 :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.