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clk: qcom: gpucc-sm8450: Add SM8475 support

Add support to the SM8475 graphics clock controller by extending the
SM8450 graphics clock controller, which is almost identical but has
some minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-7-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Danila Tikhonov and committed by
Bjorn Andersson
0b71e3b0 7c0e8764

+47 -6
+2 -1
drivers/clk/qcom/Kconfig
··· 1150 1150 depends on ARM64 || COMPILE_TEST 1151 1151 select SM_GCC_8450 1152 1152 help 1153 - Support for the graphics clock controller on SM8450 devices. 1153 + Support for the graphics clock controller on SM8450 or SM8475 1154 + devices. 1154 1155 Say Y if you want to support graphics controller devices and 1155 1156 functionality such as 3D graphics. 1156 1157
+45 -5
drivers/clk/qcom/gpucc-sm8450.c
··· 40 40 { 249600000, 2000000000, 0 }, 41 41 }; 42 42 43 - static struct alpha_pll_config gpu_cc_pll0_config = { 43 + static const struct alpha_pll_config gpu_cc_pll0_config = { 44 44 .l = 0x1d, 45 45 .alpha = 0xb000, 46 46 .config_ctl_val = 0x20485699, ··· 48 48 .config_ctl_hi1_val = 0x32aa299c, 49 49 .user_ctl_val = 0x00000000, 50 50 .user_ctl_hi_val = 0x00000805, 51 + }; 52 + 53 + static const struct alpha_pll_config sm8475_gpu_cc_pll0_config = { 54 + .l = 0x1d, 55 + .alpha = 0xb000, 56 + .config_ctl_val = 0x20485699, 57 + .config_ctl_hi_val = 0x00182261, 58 + .config_ctl_hi1_val = 0x82aa299c, 59 + .test_ctl_val = 0x00000000, 60 + .test_ctl_hi_val = 0x00000003, 61 + .test_ctl_hi1_val = 0x00009000, 62 + .test_ctl_hi2_val = 0x00000034, 63 + .user_ctl_val = 0x00000000, 64 + .user_ctl_hi_val = 0x00000005, 51 65 }; 52 66 53 67 static struct clk_alpha_pll gpu_cc_pll0 = { ··· 81 67 }, 82 68 }; 83 69 84 - static struct alpha_pll_config gpu_cc_pll1_config = { 70 + static const struct alpha_pll_config gpu_cc_pll1_config = { 85 71 .l = 0x34, 86 72 .alpha = 0x1555, 87 73 .config_ctl_val = 0x20485699, ··· 89 75 .config_ctl_hi1_val = 0x32aa299c, 90 76 .user_ctl_val = 0x00000000, 91 77 .user_ctl_hi_val = 0x00000805, 78 + }; 79 + 80 + static const struct alpha_pll_config sm8475_gpu_cc_pll1_config = { 81 + .l = 0x34, 82 + .alpha = 0x1555, 83 + .config_ctl_val = 0x20485699, 84 + .config_ctl_hi_val = 0x00182261, 85 + .config_ctl_hi1_val = 0x82aa299c, 86 + .test_ctl_val = 0x00000000, 87 + .test_ctl_hi_val = 0x00000003, 88 + .test_ctl_hi1_val = 0x00009000, 89 + .test_ctl_hi2_val = 0x00000034, 90 + .user_ctl_val = 0x00000000, 91 + .user_ctl_hi_val = 0x00000005, 92 92 }; 93 93 94 94 static struct clk_alpha_pll gpu_cc_pll1 = { ··· 764 736 765 737 static const struct of_device_id gpu_cc_sm8450_match_table[] = { 766 738 { .compatible = "qcom,sm8450-gpucc" }, 739 + { .compatible = "qcom,sm8475-gpucc" }, 767 740 { } 768 741 }; 769 742 MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table); ··· 777 748 if (IS_ERR(regmap)) 778 749 return PTR_ERR(regmap); 779 750 780 - clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 781 - clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 751 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) { 752 + /* Update GPUCC PLL0 */ 753 + gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 754 + 755 + /* Update GPUCC PLL1 */ 756 + gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 757 + 758 + clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &sm8475_gpu_cc_pll0_config); 759 + clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &sm8475_gpu_cc_pll1_config); 760 + } else { 761 + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 762 + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 763 + } 782 764 783 765 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap); 784 766 } ··· 803 763 }; 804 764 module_platform_driver(gpu_cc_sm8450_driver); 805 765 806 - MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver"); 766 + MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver"); 807 767 MODULE_LICENSE("GPL");