Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gpucc-sm8450: Add SM8475 support
Add support to the SM8475 graphics clock controller by extending the
SM8450 graphics clock controller, which is almost identical but has
some minor differences.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-7-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Danila Tikhonov
and committed by
Bjorn Andersson
0b71e3b0
7c0e8764
+47
-6
+2
-1
drivers/clk/qcom/Kconfig
+2
-1
drivers/clk/qcom/Kconfig
···
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depends on ARM64 || COMPILE_TEST
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select SM_GCC_8450
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help
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-
Support for the graphics clock controller on SM8450 devices.
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+
Support for the graphics clock controller on SM8450 or SM8475
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+
devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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+45
-5
drivers/clk/qcom/gpucc-sm8450.c
+45
-5
drivers/clk/qcom/gpucc-sm8450.c
···
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{ 249600000, 2000000000, 0 },
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};
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-
static struct alpha_pll_config gpu_cc_pll0_config = {
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x1d,
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.alpha = 0xb000,
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.config_ctl_val = 0x20485699,
···
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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+
};
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+
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static const struct alpha_pll_config sm8475_gpu_cc_pll0_config = {
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.l = 0x1d,
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.alpha = 0xb000,
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+
.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00182261,
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+
.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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+
.test_ctl_hi_val = 0x00000003,
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+
.test_ctl_hi1_val = 0x00009000,
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+
.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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+
.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll gpu_cc_pll0 = {
···
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},
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};
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-
static struct alpha_pll_config gpu_cc_pll1_config = {
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static const struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x34,
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.alpha = 0x1555,
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.config_ctl_val = 0x20485699,
···
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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+
};
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+
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static const struct alpha_pll_config sm8475_gpu_cc_pll1_config = {
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.l = 0x34,
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.alpha = 0x1555,
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.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00182261,
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+
.config_ctl_hi1_val = 0x82aa299c,
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+
.test_ctl_val = 0x00000000,
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+
.test_ctl_hi_val = 0x00000003,
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+
.test_ctl_hi1_val = 0x00009000,
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+
.test_ctl_hi2_val = 0x00000034,
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+
.user_ctl_val = 0x00000000,
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+
.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
···
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static const struct of_device_id gpu_cc_sm8450_match_table[] = {
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{ .compatible = "qcom,sm8450-gpucc" },
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{ .compatible = "qcom,sm8475-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
···
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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-
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
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-
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
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+
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) {
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+
/* Update GPUCC PLL0 */
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+
gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
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+
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+
/* Update GPUCC PLL1 */
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+
gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
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+
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+
clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &sm8475_gpu_cc_pll0_config);
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+
clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &sm8475_gpu_cc_pll1_config);
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+
} else {
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clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
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clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
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+
}
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return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap);
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}
···
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};
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module_platform_driver(gpu_cc_sm8450_driver);
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-
MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver");
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MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver");
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MODULE_LICENSE("GPL");