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arm64: cpucaps: Rename GICv3 CPU interface capability

In preparation for adding a GICv5 CPU interface capability,
rework the existing GICv3 CPUIF capability - change its name and
description so that the subsequent GICv5 CPUIF capability
can be added with a more consistent naming on top.

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-16-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Lorenzo Pieralisi and committed by
Marc Zyngier 0bb5b6fa 25374470

+7 -7
+5 -5
arch/arm64/kernel/cpufeature.c
··· 2296 2296 int scope) 2297 2297 { 2298 2298 /* 2299 - * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2299 + * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2300 2300 * feature, so will be detected earlier. 2301 2301 */ 2302 - BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2303 - if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2302 + BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2303 + if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2304 2304 return false; 2305 2305 2306 2306 return enable_pseudo_nmi; ··· 2496 2496 .matches = has_always, 2497 2497 }, 2498 2498 { 2499 - .desc = "GIC system register CPU interface", 2500 - .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2499 + .desc = "GICv3 CPU interface", 2500 + .capability = ARM64_HAS_GICV3_CPUIF, 2501 2501 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2502 2502 .matches = has_useable_gicv3_cpuif, 2503 2503 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
+1 -1
arch/arm64/tools/cpucaps
··· 35 35 HAS_GENERIC_AUTH_ARCH_QARMA3 36 36 HAS_GENERIC_AUTH_ARCH_QARMA5 37 37 HAS_GENERIC_AUTH_IMP_DEF 38 - HAS_GIC_CPUIF_SYSREGS 38 + HAS_GICV3_CPUIF 39 39 HAS_GIC_PRIO_MASKING 40 40 HAS_GIC_PRIO_RELAXED_SYNC 41 41 HAS_HCR_NV1
+1 -1
drivers/irqchip/irq-gic.c
··· 54 54 55 55 static void gic_check_cpu_features(void) 56 56 { 57 - WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GIC_CPUIF_SYSREGS), 57 + WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF), 58 58 TAINT_CPU_OUT_OF_SPEC, 59 59 "GICv3 system registers enabled, broken firmware!\n"); 60 60 }