tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

- An improvement from Ard Biesheuvel, who noted that the identity map
setup was taking a long time due to flush_cache_louis().

- Update a comment about dma_ops from Wolfram Sang.

- Remove use of "-p" with ld, where this flag has been a no-op since
2004.

- Remove the printing of the virtual memory layout, which is no longer
useful since we hide pointers.

- Correct SCU help text.

- Remove legacy TWD registration method.

- Add pgprot_device() implementation for mapping PCI sysfs resource
files.

- Initialise PFN limits earlier for kmemleak.

- Fix argument count to match macro definition (affects clang builds)

- Use unified assembler language almost everywhere for clang, and other
clang improvements (from Stefan Agner, Nathan Chancellor).

- Support security extension for noMMU and other noMMU cleanups (from
Vladimir Murzin).

- Remove unnecessary SMP bringup code (which was incorrectly copy'n'
pasted from the ARM platform implementations) and remove it from the
arch code to discourge further copys of it appearing.

- Add Cortex A9 erratum preventing kexec working on some SoCs.

- AMBA bus identification updates from Mike Leach.

- More use of raw spinlocks to avoid -RT kernel issues (from Yang Shi
and Sebastian Andrzej Siewior).

- MCPM hyp/svc mode mismatch fixes from Marek Szyprowski.

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (32 commits)
ARM: 8849/1: NOMMU: Fix encodings for PMSAv8's PRBAR4/PRLAR4
ARM: 8848/1: virt: Align GIC version check with arm64 counterpart
ARM: 8847/1: pm: fix HYP/SVC mode mismatch when MCPM is used
ARM: 8845/1: use unified assembler in c files
ARM: 8844/1: use unified assembler in assembly files
ARM: 8843/1: use unified assembler in headers
ARM: 8841/1: use unified assembler in macros
ARM: 8840/1: use a raw_spinlock_t in unwind
ARM: 8839/1: kprobe: make patch_lock a raw_spinlock_t
ARM: 8837/1: coresight: etmv4: Update ID register table to add UCI support
ARM: 8836/1: drivers: amba: Update component matching to use the CoreSight UCI values.
ARM: 8838/1: drivers: amba: Updates to component identification for driver matching.
ARM: 8833/1: Ensure that NEON code always compiles with Clang
ARM: avoid Cortex-A9 livelock on tight dmb loops
ARM: smp: remove arch-provided "pen_release"
ARM: actions: remove boot_lock and pen_release
ARM: oxnas: remove CPU hotplug implementation
ARM: qcom: remove unnecessary boot_lock
ARM: 8832/1: NOMMU: Limit visibility for CONFIG_FLASH_{MEM_BASE,SIZE}
ARM: 8831/1: NOMMU: pmsa-v8: remove unneeded semicolon
...

Linus Torvalds 0be28863 e8a71a38

+440 -609
+2 -2
Documentation/arm/kernel_mode_neon.txt
··· 6 6 * Use only NEON instructions, or VFP instructions that don't rely on support 7 7 code 8 8 * Isolate your NEON code in a separate compilation unit, and compile it with 9 - '-mfpu=neon -mfloat-abi=softfp' 9 + '-march=armv7-a -mfpu=neon -mfloat-abi=softfp' 10 10 * Put kernel_neon_begin() and kernel_neon_end() calls around the calls into your 11 11 NEON code 12 12 * Don't sleep in your NEON code, and be aware that it will be executed with ··· 87 87 Therefore, the recommended and only supported way of using NEON/VFP in the 88 88 kernel is by adhering to the following rules: 89 89 * isolate the NEON code in a separate compilation unit and compile it with 90 - '-mfpu=neon -mfloat-abi=softfp'; 90 + '-march=armv7-a -mfpu=neon -mfloat-abi=softfp'; 91 91 * issue the calls to kernel_neon_begin(), kernel_neon_end() as well as the calls 92 92 into the unit containing the NEON code from a compilation unit which is *not* 93 93 built with the GCC flag '-mfpu=neon' set.
+1 -2
arch/arm/Kconfig
··· 1310 1310 config HAVE_ARM_SCU 1311 1311 bool 1312 1312 help 1313 - This option enables support for the ARM system coherency unit 1313 + This option enables support for the ARM snoop control unit 1314 1314 1315 1315 config HAVE_ARM_ARCH_TIMER 1316 1316 bool "Architected timer support" ··· 1322 1322 1323 1323 config HAVE_ARM_TWD 1324 1324 bool 1325 - select TIMER_OF if OF 1326 1325 help 1327 1326 This options enables support for the ARM timer and watchdog unit 1328 1327
+2
arch/arm/Kconfig-nommu
··· 20 20 21 21 config FLASH_MEM_BASE 22 22 hex 'FLASH Base Address' if SET_MEM_PARAM 23 + depends on CPU_ARM740T || CPU_ARM946E || CPU_ARM940T 23 24 default 0x00400000 24 25 25 26 config FLASH_SIZE 26 27 hex 'FLASH Size' if SET_MEM_PARAM 28 + depends on CPU_ARM740T || CPU_ARM946E || CPU_ARM940T 27 29 default 0x00400000 28 30 29 31 config PROCESSOR_ID
+1 -1
arch/arm/Makefile
··· 10 10 # 11 11 # Copyright (C) 1995-2001 by Russell King 12 12 13 - LDFLAGS_vmlinux :=-p --no-undefined -X --pic-veneer 13 + LDFLAGS_vmlinux := --no-undefined -X --pic-veneer 14 14 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) 15 15 LDFLAGS_vmlinux += --be8 16 16 KBUILD_LDFLAGS_MODULE += --be8
+1 -1
arch/arm/boot/bootp/Makefile
··· 8 8 9 9 GCOV_PROFILE := n 10 10 11 - LDFLAGS_bootp :=-p --no-undefined -X \ 11 + LDFLAGS_bootp := --no-undefined -X \ 12 12 --defsym initrd_phys=$(INITRD_PHYS) \ 13 13 --defsym params_phys=$(PARAMS_PHYS) -T 14 14 AFLAGS_initrd.o :=-DINITRD=\"$(INITRD)\"
+1 -1
arch/arm/boot/bootp/init.S
··· 44 44 */ 45 45 movne r10, #0 @ terminator 46 46 movne r4, #2 @ Size of this entry (2 words) 47 - stmneia r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator 47 + stmiane r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator 48 48 49 49 /* 50 50 * find the end of the tag list, and then add an INITRD tag on the end.
-2
arch/arm/boot/compressed/Makefile
··· 132 132 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) 133 133 LDFLAGS_vmlinux += --be8 134 134 endif 135 - # ? 136 - LDFLAGS_vmlinux += -p 137 135 # Report unresolved symbol references 138 136 LDFLAGS_vmlinux += --no-undefined 139 137 # Delete all temporary local symbols
+2 -2
arch/arm/boot/compressed/ll_char_wr.S
··· 75 75 tst r1, #7 @ avoid using r7 directly after 76 76 str r7, [r0, -r5]! 77 77 subne r1, r1, #1 78 - ldrneb r7, [r6, r1] 78 + ldrbne r7, [r6, r1] 79 79 bne Lrow4bpplp 80 80 ldmfd sp!, {r4 - r7, pc} 81 81 ··· 103 103 sub r0, r0, r5 @ avoid ip 104 104 stmia r0, {r4, ip} 105 105 subne r1, r1, #1 106 - ldrneb r7, [r6, r1] 106 + ldrbne r7, [r6, r1] 107 107 bne Lrow8bpplp 108 108 ldmfd sp!, {r4 - r7, pc} 109 109
+1 -1
arch/arm/common/mcpm_entry.c
··· 381 381 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 382 382 phys_reset_t phys_reset; 383 383 384 - mcpm_set_entry_vector(cpu, cluster, cpu_resume); 384 + mcpm_set_entry_vector(cpu, cluster, cpu_resume_no_hyp); 385 385 setup_mm_for_reboot(); 386 386 387 387 __mcpm_cpu_going_down(cpu, cluster);
+6 -6
arch/arm/include/asm/assembler.h
··· 376 376 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 377 377 9999: 378 378 .if \inc == 1 379 - \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] 379 + \instr\()b\t\cond\().w \reg, [\ptr, #\off] 380 380 .elseif \inc == 4 381 - \instr\cond\()\t\().w \reg, [\ptr, #\off] 381 + \instr\t\cond\().w \reg, [\ptr, #\off] 382 382 .else 383 383 .error "Unsupported inc macro argument" 384 384 .endif ··· 417 417 .rept \rept 418 418 9999: 419 419 .if \inc == 1 420 - \instr\cond\()b\()\t \reg, [\ptr], #\inc 420 + \instr\()b\t\cond \reg, [\ptr], #\inc 421 421 .elseif \inc == 4 422 - \instr\cond\()\t \reg, [\ptr], #\inc 422 + \instr\t\cond \reg, [\ptr], #\inc 423 423 .else 424 424 .error "Unsupported inc macro argument" 425 425 .endif ··· 460 460 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req 461 461 #ifndef CONFIG_CPU_USE_DOMAINS 462 462 adds \tmp, \addr, #\size - 1 463 - sbcccs \tmp, \tmp, \limit 463 + sbcscc \tmp, \tmp, \limit 464 464 bcs \bad 465 465 #ifdef CONFIG_CPU_SPECTRE 466 466 movcs \addr, #0 ··· 474 474 sub \tmp, \limit, #1 475 475 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr 476 476 addhs \tmp, \tmp, #1 @ if (tmp >= 0) { 477 - subhss \tmp, \tmp, \size @ tmp = limit - (addr + size) } 477 + subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) } 478 478 movlo \addr, #0 @ if (tmp < 0) addr = NULL 479 479 csdb 480 480 #endif
+2
arch/arm/include/asm/barrier.h
··· 11 11 #define sev() __asm__ __volatile__ ("sev" : : : "memory") 12 12 #define wfe() __asm__ __volatile__ ("wfe" : : : "memory") 13 13 #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") 14 + #else 15 + #define wfe() do { } while (0) 14 16 #endif 15 17 16 18 #if __LINUX_ARM_ARCH__ >= 7
+5 -5
arch/arm/include/asm/hardware/entry-macro-iomd.S
··· 16 16 ldr \tmp, =irq_prio_h 17 17 teq \irqstat, #0 18 18 #ifdef IOMD_BASE 19 - ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma 19 + ldrbeq \irqstat, [\base, #IOMD_DMAREQ] @ get dma 20 20 addeq \tmp, \tmp, #256 @ irq_prio_h table size 21 21 teqeq \irqstat, #0 22 22 bne 2406f 23 23 #endif 24 - ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority 24 + ldrbeq \irqstat, [\base, #IOMD_IRQREQA] @ get low priority 25 25 addeq \tmp, \tmp, #256 @ irq_prio_d table size 26 26 teqeq \irqstat, #0 27 27 #ifdef IOMD_IRQREQC 28 - ldreqb \irqstat, [\base, #IOMD_IRQREQC] 28 + ldrbeq \irqstat, [\base, #IOMD_IRQREQC] 29 29 addeq \tmp, \tmp, #256 @ irq_prio_l table size 30 30 teqeq \irqstat, #0 31 31 #endif 32 32 #ifdef IOMD_IRQREQD 33 - ldreqb \irqstat, [\base, #IOMD_IRQREQD] 33 + ldrbeq \irqstat, [\base, #IOMD_IRQREQD] 34 34 addeq \tmp, \tmp, #256 @ irq_prio_lc table size 35 35 teqeq \irqstat, #0 36 36 #endif 37 - 2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number 37 + 2406: ldrbne \irqnr, [\tmp, \irqstat] @ get IRQ number 38 38 .endm 39 39 40 40 /*
+3
arch/arm/include/asm/pgtable.h
··· 125 125 #define pgprot_stronglyordered(prot) \ 126 126 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) 127 127 128 + #define pgprot_device(prot) \ 129 + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_SHARED | L_PTE_SHARED | L_PTE_DIRTY | L_PTE_XN) 130 + 128 131 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 129 132 #define pgprot_dmacoherent(prot) \ 130 133 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
+5 -1
arch/arm/include/asm/processor.h
··· 89 89 unsigned long get_wchan(struct task_struct *p); 90 90 91 91 #if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327) 92 - #define cpu_relax() smp_mb() 92 + #define cpu_relax() \ 93 + do { \ 94 + smp_mb(); \ 95 + __asm__ __volatile__("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;"); \ 96 + } while (0) 93 97 #else 94 98 #define cpu_relax() barrier() 95 99 #endif
-1
arch/arm/include/asm/smp.h
··· 67 67 void *stack; 68 68 }; 69 69 extern struct secondary_data secondary_data; 70 - extern volatile int pen_release; 71 70 extern void secondary_startup(void); 72 71 extern void secondary_startup_arm(void); 73 72
-16
arch/arm/include/asm/smp_twd.h
··· 19 19 #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) 20 20 #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) 21 21 22 - #include <linux/ioport.h> 23 - 24 - struct twd_local_timer { 25 - struct resource res[2]; 26 - }; 27 - 28 - #define DEFINE_TWD_LOCAL_TIMER(name,base,irq) \ 29 - struct twd_local_timer name __initdata = { \ 30 - .res = { \ 31 - DEFINE_RES_MEM(base, 0x10), \ 32 - DEFINE_RES_IRQ(irq), \ 33 - }, \ 34 - }; 35 - 36 - int twd_local_timer_register(struct twd_local_timer *); 37 - 38 22 #endif
+2 -1
arch/arm/include/asm/spinlock.h
··· 210 210 211 211 prefetchw(&rw->lock); 212 212 __asm__ __volatile__( 213 + " .syntax unified\n" 213 214 "1: ldrex %0, [%2]\n" 214 215 " adds %0, %0, #1\n" 215 216 " strexpl %1, %0, [%2]\n" 216 217 WFE("mi") 217 - " rsbpls %0, %1, #0\n" 218 + " rsbspl %0, %1, #0\n" 218 219 " bmi 1b" 219 220 : "=&r" (tmp), "=&r" (tmp2) 220 221 : "r" (&rw->lock)
+1
arch/arm/include/asm/suspend.h
··· 10 10 }; 11 11 12 12 extern void cpu_resume(void); 13 + extern void cpu_resume_no_hyp(void); 13 14 extern void cpu_resume_arm(void); 14 15 extern int cpu_suspend(unsigned long, int (*)(unsigned long)); 15 16
+2 -1
arch/arm/include/asm/uaccess.h
··· 85 85 #define __range_ok(addr, size) ({ \ 86 86 unsigned long flag, roksum; \ 87 87 __chk_user_ptr(addr); \ 88 - __asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \ 88 + __asm__(".syntax unified\n" \ 89 + "adds %1, %2, %3; sbcscc %1, %1, %0; movcc %0, #0" \ 89 90 : "=&r" (flag), "=&r" (roksum) \ 90 91 : "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \ 91 92 : "cc"); \
+1 -1
arch/arm/include/asm/v7m.h
··· 49 49 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. 50 50 */ 51 51 #define EXC_RET_STACK_MASK 0x00000004 52 - #define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd 52 + #define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2) 53 53 54 54 /* Cache related definitions */ 55 55
+4 -4
arch/arm/include/asm/vfpmacros.h
··· 29 29 ldr \tmp, =elf_hwcap @ may not have MVFR regs 30 30 ldr \tmp, [\tmp, #0] 31 31 tst \tmp, #HWCAP_VFPD32 32 - ldcnel p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} 32 + ldclne p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} 33 33 addeq \base, \base, #32*4 @ step over unused register space 34 34 #else 35 35 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 36 36 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 37 37 cmp \tmp, #2 @ 32 x 64bit registers? 38 - ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} 38 + ldcleq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} 39 39 addne \base, \base, #32*4 @ step over unused register space 40 40 #endif 41 41 #endif ··· 53 53 ldr \tmp, =elf_hwcap @ may not have MVFR regs 54 54 ldr \tmp, [\tmp, #0] 55 55 tst \tmp, #HWCAP_VFPD32 56 - stcnel p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} 56 + stclne p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} 57 57 addeq \base, \base, #32*4 @ step over unused register space 58 58 #else 59 59 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 60 60 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field 61 61 cmp \tmp, #2 @ 32 x 64bit registers? 62 - stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} 62 + stcleq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} 63 63 addne \base, \base, #32*4 @ step over unused register space 64 64 #endif 65 65 #endif
+1 -1
arch/arm/include/debug/tegra.S
··· 173 173 174 174 .macro senduart, rd, rx 175 175 cmp \rx, #0 176 - strneb \rd, [\rx, #UART_TX << UART_SHIFT] 176 + strbne \rd, [\rx, #UART_TX << UART_SHIFT] 177 177 1001: 178 178 .endm 179 179
+1 -1
arch/arm/kernel/debug.S
··· 86 86 ENTRY(printascii) 87 87 addruart_current r3, r1, r2 88 88 1: teq r0, #0 89 - ldrneb r1, [r0], #1 89 + ldrbne r1, [r0], #1 90 90 teqne r1, #0 91 91 reteq lr 92 92 2: teq r1, #'\n'
+6 -6
arch/arm/kernel/entry-armv.S
··· 636 636 @ Test if we need to give access to iWMMXt coprocessors 637 637 ldr r5, [r10, #TI_FLAGS] 638 638 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 639 - movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 639 + movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) 640 640 bcs iwmmxt_task_enable 641 641 #endif 642 642 ARM( add pc, pc, r8, lsr #6 ) ··· 872 872 smp_dmb arm 873 873 1: ldrexd r0, r1, [r2] @ load current val 874 874 eors r3, r0, r4 @ compare with oldval (1) 875 - eoreqs r3, r1, r5 @ compare with oldval (2) 875 + eorseq r3, r1, r5 @ compare with oldval (2) 876 876 strexdeq r3, r6, r7, [r2] @ store newval if eq 877 877 teqeq r3, #1 @ success? 878 878 beq 1b @ if no then retry ··· 896 896 ldmia r1, {r6, lr} @ load new val 897 897 1: ldmia r2, {r0, r1} @ load current val 898 898 eors r3, r0, r4 @ compare with oldval (1) 899 - eoreqs r3, r1, r5 @ compare with oldval (2) 900 - 2: stmeqia r2, {r6, lr} @ store newval if eq 899 + eorseq r3, r1, r5 @ compare with oldval (2) 900 + 2: stmiaeq r2, {r6, lr} @ store newval if eq 901 901 rsbs r0, r3, #0 @ set return val and C flag 902 902 ldmfd sp!, {r4, r5, r6, pc} 903 903 ··· 911 911 mov r7, #0xffff0fff 912 912 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) 913 913 subs r8, r4, r7 914 - rsbcss r8, r8, #(2b - 1b) 914 + rsbscs r8, r8, #(2b - 1b) 915 915 strcs r7, [sp, #S_PC] 916 916 #if __LINUX_ARM_ARCH__ < 6 917 917 bcc kuser_cmpxchg32_fixup ··· 969 969 mov r7, #0xffff0fff 970 970 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 971 971 subs r8, r4, r7 972 - rsbcss r8, r8, #(2b - 1b) 972 + rsbscs r8, r8, #(2b - 1b) 973 973 strcs r7, [sp, #S_PC] 974 974 ret lr 975 975 .previous
+1 -1
arch/arm/kernel/entry-common.S
··· 373 373 movhs scno, #0 374 374 csdb 375 375 #endif 376 - stmloia sp, {r5, r6} @ shuffle args 376 + stmialo sp, {r5, r6} @ shuffle args 377 377 movlo r0, r1 378 378 movlo r1, r2 379 379 movlo r2, r3
+6 -5
arch/arm/kernel/entry-header.S
··· 127 127 */ 128 128 .macro v7m_exception_slow_exit ret_r0 129 129 cpsid i 130 - ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK 130 + ldr lr, =exc_ret 131 + ldr lr, [lr] 131 132 132 133 @ read original r12, sp, lr, pc and xPSR 133 134 add r12, sp, #S_IP ··· 388 387 badr lr, \ret @ return address 389 388 .if \reload 390 389 add r1, sp, #S_R0 + S_OFF @ pointer to regs 391 - ldmccia r1, {r0 - r6} @ reload r0-r6 392 - stmccia sp, {r4, r5} @ update stack arguments 390 + ldmiacc r1, {r0 - r6} @ reload r0-r6 391 + stmiacc sp, {r4, r5} @ update stack arguments 393 392 .endif 394 393 ldrcc pc, [\table, \tmp, lsl #2] @ call sys_* routine 395 394 #else ··· 397 396 badr lr, \ret @ return address 398 397 .if \reload 399 398 add r1, sp, #S_R0 + S_OFF @ pointer to regs 400 - ldmccia r1, {r0 - r6} @ reload r0-r6 401 - stmccia sp, {r4, r5} @ update stack arguments 399 + ldmiacc r1, {r0 - r6} @ reload r0-r6 400 + stmiacc sp, {r4, r5} @ update stack arguments 402 401 .endif 403 402 ldrcc pc, [\table, \nr, lsl #2] @ call sys_* routine 404 403 #endif
+4
arch/arm/kernel/entry-v7m.S
··· 146 146 .rept CONFIG_CPU_V7M_NUM_IRQ 147 147 .long __irq_entry @ External Interrupts 148 148 .endr 149 + .align 2 150 + .globl exc_ret 151 + exc_ret: 152 + .space 4
+2 -2
arch/arm/kernel/head-nommu.S
··· 439 439 str r5, [r12, #PMSAv8_RBAR_A(0)] 440 440 str r6, [r12, #PMSAv8_RLAR_A(0)] 441 441 #else 442 - mcr p15, 0, r5, c6, c10, 1 @ PRBAR4 443 - mcr p15, 0, r6, c6, c10, 2 @ PRLAR4 442 + mcr p15, 0, r5, c6, c10, 0 @ PRBAR4 443 + mcr p15, 0, r6, c6, c10, 1 @ PRLAR4 444 444 #endif 445 445 #endif 446 446 ret lr
+2 -2
arch/arm/kernel/hyp-stub.S
··· 180 180 @ Check whether GICv3 system registers are available 181 181 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 182 182 ubfx r7, r7, #28, #4 183 - cmp r7, #1 184 - bne 2f 183 + teq r7, #0 184 + beq 2f 185 185 186 186 @ Enable system register accesses 187 187 mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
+4 -1
arch/arm/kernel/machine_kexec.c
··· 91 91 92 92 set_cpu_online(smp_processor_id(), false); 93 93 atomic_dec(&waiting_for_crash_ipi); 94 - while (1) 94 + 95 + while (1) { 95 96 cpu_relax(); 97 + wfe(); 98 + } 96 99 } 97 100 98 101 void crash_smp_send_stop(void)
+3 -3
arch/arm/kernel/patch.c
··· 16 16 unsigned int insn; 17 17 }; 18 18 19 - static DEFINE_SPINLOCK(patch_lock); 19 + static DEFINE_RAW_SPINLOCK(patch_lock); 20 20 21 21 static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags) 22 22 __acquires(&patch_lock) ··· 33 33 return addr; 34 34 35 35 if (flags) 36 - spin_lock_irqsave(&patch_lock, *flags); 36 + raw_spin_lock_irqsave(&patch_lock, *flags); 37 37 else 38 38 __acquire(&patch_lock); 39 39 ··· 48 48 clear_fixmap(fixmap); 49 49 50 50 if (flags) 51 - spin_unlock_irqrestore(&patch_lock, *flags); 51 + raw_spin_unlock_irqrestore(&patch_lock, *flags); 52 52 else 53 53 __release(&patch_lock); 54 54 }
+12
arch/arm/kernel/sleep.S
··· 120 120 .text 121 121 .align 122 122 123 + #ifdef CONFIG_MCPM 124 + .arm 125 + THUMB( .thumb ) 126 + ENTRY(cpu_resume_no_hyp) 127 + ARM_BE8(setend be) @ ensure we are in BE mode 128 + b no_hyp 129 + #endif 130 + 123 131 #ifdef CONFIG_MMU 124 132 .arm 125 133 ENTRY(cpu_resume_arm) ··· 143 135 bl __hyp_stub_install_secondary 144 136 #endif 145 137 safe_svcmode_maskall r1 138 + no_hyp: 146 139 mov r1, #0 147 140 ALT_SMP(mrc p15, 0, r0, c0, c0, 5) 148 141 ALT_UP_B(1f) ··· 172 163 173 164 #ifdef CONFIG_MMU 174 165 ENDPROC(cpu_resume_arm) 166 + #endif 167 + #ifdef CONFIG_MCPM 168 + ENDPROC(cpu_resume_no_hyp) 175 169 #endif 176 170 177 171 .align 2
+3 -7
arch/arm/kernel/smp.c
··· 62 62 */ 63 63 struct secondary_data secondary_data; 64 64 65 - /* 66 - * control for which core is the next to come out of the secondary 67 - * boot "holding pen" 68 - */ 69 - volatile int pen_release = -1; 70 - 71 65 enum ipi_msg_type { 72 66 IPI_WAKEUP, 73 67 IPI_TIMER, ··· 598 604 local_fiq_disable(); 599 605 local_irq_disable(); 600 606 601 - while (1) 607 + while (1) { 602 608 cpu_relax(); 609 + wfe(); 610 + } 603 611 } 604 612 605 613 static DEFINE_PER_CPU(struct completion *, cpu_completion);
-66
arch/arm/kernel/smp_twd.c
··· 100 100 disable_percpu_irq(clk->irq); 101 101 } 102 102 103 - #ifdef CONFIG_COMMON_CLK 104 - 105 103 /* 106 104 * Updates clockevent frequency when the cpu frequency changes. 107 105 * Called on the cpu that is changing frequency with interrupts disabled. ··· 140 142 return 0; 141 143 } 142 144 core_initcall(twd_clk_init); 143 - 144 - #elif defined (CONFIG_CPU_FREQ) 145 - 146 - #include <linux/cpufreq.h> 147 - 148 - /* 149 - * Updates clockevent frequency when the cpu frequency changes. 150 - * Called on the cpu that is changing frequency with interrupts disabled. 151 - */ 152 - static void twd_update_frequency(void *data) 153 - { 154 - twd_timer_rate = clk_get_rate(twd_clk); 155 - 156 - clockevents_update_freq(raw_cpu_ptr(twd_evt), twd_timer_rate); 157 - } 158 - 159 - static int twd_cpufreq_transition(struct notifier_block *nb, 160 - unsigned long state, void *data) 161 - { 162 - struct cpufreq_freqs *freqs = data; 163 - 164 - /* 165 - * The twd clock events must be reprogrammed to account for the new 166 - * frequency. The timer is local to a cpu, so cross-call to the 167 - * changing cpu. 168 - */ 169 - if (state == CPUFREQ_POSTCHANGE) 170 - smp_call_function_single(freqs->cpu, twd_update_frequency, 171 - NULL, 1); 172 - 173 - return NOTIFY_OK; 174 - } 175 - 176 - static struct notifier_block twd_cpufreq_nb = { 177 - .notifier_call = twd_cpufreq_transition, 178 - }; 179 - 180 - static int twd_cpufreq_init(void) 181 - { 182 - if (twd_evt && raw_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) 183 - return cpufreq_register_notifier(&twd_cpufreq_nb, 184 - CPUFREQ_TRANSITION_NOTIFIER); 185 - 186 - return 0; 187 - } 188 - core_initcall(twd_cpufreq_init); 189 - 190 - #endif 191 145 192 146 static void twd_calibrate_rate(void) 193 147 { ··· 316 366 return err; 317 367 } 318 368 319 - int __init twd_local_timer_register(struct twd_local_timer *tlt) 320 - { 321 - if (twd_base || twd_evt) 322 - return -EBUSY; 323 - 324 - twd_ppi = tlt->res[1].start; 325 - 326 - twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0])); 327 - if (!twd_base) 328 - return -ENOMEM; 329 - 330 - return twd_local_timer_common_register(NULL); 331 - } 332 - 333 - #ifdef CONFIG_OF 334 369 static int __init twd_local_timer_of_register(struct device_node *np) 335 370 { 336 371 int err; ··· 341 406 TIMER_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); 342 407 TIMER_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); 343 408 TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); 344 - #endif
+7 -7
arch/arm/kernel/unwind.c
··· 93 93 static const struct unwind_idx *__origin_unwind_idx; 94 94 extern const struct unwind_idx __stop_unwind_idx[]; 95 95 96 - static DEFINE_SPINLOCK(unwind_lock); 96 + static DEFINE_RAW_SPINLOCK(unwind_lock); 97 97 static LIST_HEAD(unwind_tables); 98 98 99 99 /* Convert a prel31 symbol to an absolute address */ ··· 201 201 /* module unwind tables */ 202 202 struct unwind_table *table; 203 203 204 - spin_lock_irqsave(&unwind_lock, flags); 204 + raw_spin_lock_irqsave(&unwind_lock, flags); 205 205 list_for_each_entry(table, &unwind_tables, list) { 206 206 if (addr >= table->begin_addr && 207 207 addr < table->end_addr) { ··· 213 213 break; 214 214 } 215 215 } 216 - spin_unlock_irqrestore(&unwind_lock, flags); 216 + raw_spin_unlock_irqrestore(&unwind_lock, flags); 217 217 } 218 218 219 219 pr_debug("%s: idx = %p\n", __func__, idx); ··· 529 529 tab->begin_addr = text_addr; 530 530 tab->end_addr = text_addr + text_size; 531 531 532 - spin_lock_irqsave(&unwind_lock, flags); 532 + raw_spin_lock_irqsave(&unwind_lock, flags); 533 533 list_add_tail(&tab->list, &unwind_tables); 534 - spin_unlock_irqrestore(&unwind_lock, flags); 534 + raw_spin_unlock_irqrestore(&unwind_lock, flags); 535 535 536 536 return tab; 537 537 } ··· 543 543 if (!tab) 544 544 return; 545 545 546 - spin_lock_irqsave(&unwind_lock, flags); 546 + raw_spin_lock_irqsave(&unwind_lock, flags); 547 547 list_del(&tab->list); 548 - spin_unlock_irqrestore(&unwind_lock, flags); 548 + raw_spin_unlock_irqrestore(&unwind_lock, flags); 549 549 550 550 kfree(tab); 551 551 }
+1 -1
arch/arm/lib/Makefile
··· 39 39 $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S 40 40 41 41 ifeq ($(CONFIG_KERNEL_MODE_NEON),y) 42 - NEON_FLAGS := -mfloat-abi=softfp -mfpu=neon 42 + NEON_FLAGS := -march=armv7-a -mfloat-abi=softfp -mfpu=neon 43 43 CFLAGS_xor-neon.o += $(NEON_FLAGS) 44 44 obj-$(CONFIG_XOR_BLOCKS) += xor-neon.o 45 45 endif
+4 -4
arch/arm/lib/bitops.h
··· 7 7 ENTRY( \name ) 8 8 UNWIND( .fnstart ) 9 9 ands ip, r1, #3 10 - strneb r1, [ip] @ assert word-aligned 10 + strbne r1, [ip] @ assert word-aligned 11 11 mov r2, #1 12 12 and r3, r0, #31 @ Get bit offset 13 13 mov r0, r0, lsr #5 ··· 32 32 ENTRY( \name ) 33 33 UNWIND( .fnstart ) 34 34 ands ip, r1, #3 35 - strneb r1, [ip] @ assert word-aligned 35 + strbne r1, [ip] @ assert word-aligned 36 36 mov r2, #1 37 37 and r3, r0, #31 @ Get bit offset 38 38 mov r0, r0, lsr #5 ··· 62 62 ENTRY( \name ) 63 63 UNWIND( .fnstart ) 64 64 ands ip, r1, #3 65 - strneb r1, [ip] @ assert word-aligned 65 + strbne r1, [ip] @ assert word-aligned 66 66 and r2, r0, #31 67 67 mov r0, r0, lsr #5 68 68 mov r3, #1 ··· 89 89 ENTRY( \name ) 90 90 UNWIND( .fnstart ) 91 91 ands ip, r1, #3 92 - strneb r1, [ip] @ assert word-aligned 92 + strbne r1, [ip] @ assert word-aligned 93 93 and r3, r0, #31 94 94 mov r0, r0, lsr #5 95 95 save_and_disable_irqs ip
+1 -1
arch/arm/lib/clear_user.S
··· 44 44 strusr r2, r0, 1, ne, rept=2 45 45 tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1 46 46 it ne @ explicit IT needed for the label 47 - USER( strnebt r2, [r0]) 47 + USER( strbtne r2, [r0]) 48 48 mov r0, #0 49 49 ldmfd sp!, {r1, pc} 50 50 UNWIND(.fnend)
+1 -1
arch/arm/lib/copy_from_user.S
··· 91 91 .endm 92 92 93 93 .macro str1b ptr reg cond=al abort 94 - str\cond\()b \reg, [\ptr], #1 94 + strb\cond \reg, [\ptr], #1 95 95 .endm 96 96 97 97 .macro enter reg1 reg2
+2 -2
arch/arm/lib/copy_page.S
··· 39 39 .endr 40 40 subs r2, r2, #1 @ 1 41 41 stmia r0!, {r3, r4, ip, lr} @ 4 42 - ldmgtia r1!, {r3, r4, ip, lr} @ 4 42 + ldmiagt r1!, {r3, r4, ip, lr} @ 4 43 43 bgt 1b @ 1 44 - PLD( ldmeqia r1!, {r3, r4, ip, lr} ) 44 + PLD( ldmiaeq r1!, {r3, r4, ip, lr} ) 45 45 PLD( beq 2b ) 46 46 ldmfd sp!, {r4, pc} @ 3 47 47 ENDPROC(copy_page)
+3 -3
arch/arm/lib/copy_template.S
··· 99 99 100 100 CALGN( ands ip, r0, #31 ) 101 101 CALGN( rsb r3, ip, #32 ) 102 - CALGN( sbcnes r4, r3, r2 ) @ C is always set here 102 + CALGN( sbcsne r4, r3, r2 ) @ C is always set here 103 103 CALGN( bcs 2f ) 104 104 CALGN( adr r4, 6f ) 105 105 CALGN( subs r2, r2, r3 ) @ C gets set ··· 204 204 205 205 CALGN( ands ip, r0, #31 ) 206 206 CALGN( rsb ip, ip, #32 ) 207 - CALGN( sbcnes r4, ip, r2 ) @ C is always set here 207 + CALGN( sbcsne r4, ip, r2 ) @ C is always set here 208 208 CALGN( subcc r2, r2, ip ) 209 209 CALGN( bcc 15f ) 210 210 ··· 241 241 orr r9, r9, ip, lspush #\push 242 242 mov ip, ip, lspull #\pull 243 243 orr ip, ip, lr, lspush #\push 244 - str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f 244 + str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f 245 245 bge 12b 246 246 PLD( cmn r2, #96 ) 247 247 PLD( bge 13b )
+1 -1
arch/arm/lib/copy_to_user.S
··· 49 49 .endm 50 50 51 51 .macro ldr1b ptr reg cond=al abort 52 - ldr\cond\()b \reg, [\ptr], #1 52 + ldrb\cond \reg, [\ptr], #1 53 53 .endm 54 54 55 55 #ifdef CONFIG_CPU_USE_DOMAINS
+10 -10
arch/arm/lib/csumpartial.S
··· 40 40 /* we must have at least one byte. */ 41 41 tst buf, #1 @ odd address? 42 42 movne sum, sum, ror #8 43 - ldrneb td0, [buf], #1 43 + ldrbne td0, [buf], #1 44 44 subne len, len, #1 45 - adcnes sum, sum, td0, put_byte_1 45 + adcsne sum, sum, td0, put_byte_1 46 46 47 47 .Lless4: tst len, #6 48 48 beq .Lless8_byte ··· 68 68 bne .Lless8_wordlp 69 69 70 70 .Lless8_byte: tst len, #1 @ odd number of bytes 71 - ldrneb td0, [buf], #1 @ include last byte 72 - adcnes sum, sum, td0, put_byte_0 @ update checksum 71 + ldrbne td0, [buf], #1 @ include last byte 72 + adcsne sum, sum, td0, put_byte_0 @ update checksum 73 73 74 74 .Ldone: adc r0, sum, #0 @ collect up the last carry 75 75 ldr td0, [sp], #4 ··· 78 78 ldr pc, [sp], #4 @ return 79 79 80 80 .Lnot_aligned: tst buf, #1 @ odd address 81 - ldrneb td0, [buf], #1 @ make even 81 + ldrbne td0, [buf], #1 @ make even 82 82 subne len, len, #1 83 - adcnes sum, sum, td0, put_byte_1 @ update checksum 83 + adcsne sum, sum, td0, put_byte_1 @ update checksum 84 84 85 85 tst buf, #2 @ 32-bit aligned? 86 86 #if __LINUX_ARM_ARCH__ >= 4 87 - ldrneh td0, [buf], #2 @ make 32-bit aligned 87 + ldrhne td0, [buf], #2 @ make 32-bit aligned 88 88 subne len, len, #2 89 89 #else 90 - ldrneb td0, [buf], #1 91 - ldrneb ip, [buf], #1 90 + ldrbne td0, [buf], #1 91 + ldrbne ip, [buf], #1 92 92 subne len, len, #2 93 93 #ifndef __ARMEB__ 94 94 orrne td0, td0, ip, lsl #8 ··· 96 96 orrne td0, ip, td0, lsl #8 97 97 #endif 98 98 #endif 99 - adcnes sum, sum, td0 @ update checksum 99 + adcsne sum, sum, td0 @ update checksum 100 100 ret lr 101 101 102 102 ENTRY(csum_partial)
+2 -2
arch/arm/lib/csumpartialcopygeneric.S
··· 148 148 strb r5, [dst], #1 149 149 mov r5, r4, get_byte_2 150 150 .Lexit: tst len, #1 151 - strneb r5, [dst], #1 151 + strbne r5, [dst], #1 152 152 andne r5, r5, #255 153 - adcnes sum, sum, r5, put_byte_0 153 + adcsne sum, sum, r5, put_byte_0 154 154 155 155 /* 156 156 * If the dst pointer was not 16-bit aligned, we
+1 -1
arch/arm/lib/csumpartialcopyuser.S
··· 95 95 add r2, r2, r1 96 96 mov r0, #0 @ zero the buffer 97 97 9002: teq r2, r1 98 - strneb r0, [r1], #1 98 + strbne r0, [r1], #1 99 99 bne 9002b 100 100 load_regs 101 101 .popsection
+2 -2
arch/arm/lib/div64.S
··· 88 88 @ Break out early if dividend reaches 0. 89 89 2: cmp xh, yl 90 90 orrcs yh, yh, ip 91 - subcss xh, xh, yl 92 - movnes ip, ip, lsr #1 91 + subscs xh, xh, yl 92 + movsne ip, ip, lsr #1 93 93 mov yl, yl, lsr #1 94 94 bne 2b 95 95
+5 -5
arch/arm/lib/floppydma.S
··· 14 14 .global floppy_fiqin_end 15 15 ENTRY(floppy_fiqin_start) 16 16 subs r9, r9, #1 17 - ldrgtb r12, [r11, #-4] 18 - ldrleb r12, [r11], #0 17 + ldrbgt r12, [r11, #-4] 18 + ldrble r12, [r11], #0 19 19 strb r12, [r10], #1 20 20 subs pc, lr, #4 21 21 floppy_fiqin_end: ··· 23 23 .global floppy_fiqout_end 24 24 ENTRY(floppy_fiqout_start) 25 25 subs r9, r9, #1 26 - ldrgeb r12, [r10], #1 26 + ldrbge r12, [r10], #1 27 27 movlt r12, #0 28 - strleb r12, [r11], #0 29 - subles pc, lr, #4 28 + strble r12, [r11], #0 29 + subsle pc, lr, #4 30 30 strb r12, [r11, #-4] 31 31 subs pc, lr, #4 32 32 floppy_fiqout_end:
+10 -10
arch/arm/lib/io-readsb.S
··· 16 16 cmp ip, #2 17 17 ldrb r3, [r0] 18 18 strb r3, [r1], #1 19 - ldrgeb r3, [r0] 20 - strgeb r3, [r1], #1 21 - ldrgtb r3, [r0] 22 - strgtb r3, [r1], #1 19 + ldrbge r3, [r0] 20 + strbge r3, [r1], #1 21 + ldrbgt r3, [r0] 22 + strbgt r3, [r1], #1 23 23 subs r2, r2, ip 24 24 bne .Linsb_aligned 25 25 ··· 72 72 bpl .Linsb_16_lp 73 73 74 74 tst r2, #15 75 - ldmeqfd sp!, {r4 - r6, pc} 75 + ldmfdeq sp!, {r4 - r6, pc} 76 76 77 77 .Linsb_no_16: tst r2, #8 78 78 beq .Linsb_no_8 ··· 109 109 str r3, [r1], #4 110 110 111 111 .Linsb_no_4: ands r2, r2, #3 112 - ldmeqfd sp!, {r4 - r6, pc} 112 + ldmfdeq sp!, {r4 - r6, pc} 113 113 114 114 cmp r2, #2 115 115 ldrb r3, [r0] 116 116 strb r3, [r1], #1 117 - ldrgeb r3, [r0] 118 - strgeb r3, [r1], #1 119 - ldrgtb r3, [r0] 120 - strgtb r3, [r1] 117 + ldrbge r3, [r0] 118 + strbge r3, [r1], #1 119 + ldrbgt r3, [r0] 120 + strbgt r3, [r1] 121 121 122 122 ldmfd sp!, {r4 - r6, pc} 123 123 ENDPROC(__raw_readsb)
+1 -1
arch/arm/lib/io-readsl.S
··· 30 30 2: movs r2, r2, lsl #31 31 31 ldrcs r3, [r0, #0] 32 32 ldrcs ip, [r0, #0] 33 - stmcsia r1!, {r3, ip} 33 + stmiacs r1!, {r3, ip} 34 34 ldrne r3, [r0, #0] 35 35 strne r3, [r1, #0] 36 36 ret lr
+3 -3
arch/arm/lib/io-readsw-armv3.S
··· 68 68 bpl .Linsw_8_lp 69 69 70 70 tst r2, #7 71 - ldmeqfd sp!, {r4, r5, r6, pc} 71 + ldmfdeq sp!, {r4, r5, r6, pc} 72 72 73 73 .Lno_insw_8: tst r2, #4 74 74 beq .Lno_insw_4 ··· 97 97 98 98 .Lno_insw_2: tst r2, #1 99 99 ldrne r3, [r0] 100 - strneb r3, [r1], #1 100 + strbne r3, [r1], #1 101 101 movne r3, r3, lsr #8 102 - strneb r3, [r1] 102 + strbne r3, [r1] 103 103 104 104 ldmfd sp!, {r4, r5, r6, pc} 105 105
+6 -6
arch/arm/lib/io-readsw-armv4.S
··· 76 76 pack r3, r3, ip 77 77 str r3, [r1], #4 78 78 79 - .Lno_insw_2: ldrneh r3, [r0] 80 - strneh r3, [r1] 79 + .Lno_insw_2: ldrhne r3, [r0] 80 + strhne r3, [r1] 81 81 82 82 ldmfd sp!, {r4, r5, pc} 83 83 ··· 94 94 #endif 95 95 96 96 .Linsw_noalign: stmfd sp!, {r4, lr} 97 - ldrccb ip, [r1, #-1]! 97 + ldrbcc ip, [r1, #-1]! 98 98 bcc 1f 99 99 100 100 ldrh ip, [r0] ··· 121 121 122 122 3: tst r2, #1 123 123 strb ip, [r1], #1 124 - ldrneh ip, [r0] 124 + ldrhne ip, [r0] 125 125 _BE_ONLY_( movne ip, ip, ror #8 ) 126 - strneb ip, [r1], #1 126 + strbne ip, [r1], #1 127 127 _LE_ONLY_( movne ip, ip, lsr #8 ) 128 128 _BE_ONLY_( movne ip, ip, lsr #24 ) 129 - strneb ip, [r1] 129 + strbne ip, [r1] 130 130 ldmfd sp!, {r4, pc} 131 131 ENDPROC(__raw_readsw)
+10 -10
arch/arm/lib/io-writesb.S
··· 36 36 cmp ip, #2 37 37 ldrb r3, [r1], #1 38 38 strb r3, [r0] 39 - ldrgeb r3, [r1], #1 40 - strgeb r3, [r0] 41 - ldrgtb r3, [r1], #1 42 - strgtb r3, [r0] 39 + ldrbge r3, [r1], #1 40 + strbge r3, [r0] 41 + ldrbgt r3, [r1], #1 42 + strbgt r3, [r0] 43 43 subs r2, r2, ip 44 44 bne .Loutsb_aligned 45 45 ··· 64 64 bpl .Loutsb_16_lp 65 65 66 66 tst r2, #15 67 - ldmeqfd sp!, {r4, r5, pc} 67 + ldmfdeq sp!, {r4, r5, pc} 68 68 69 69 .Loutsb_no_16: tst r2, #8 70 70 beq .Loutsb_no_8 ··· 80 80 outword r3 81 81 82 82 .Loutsb_no_4: ands r2, r2, #3 83 - ldmeqfd sp!, {r4, r5, pc} 83 + ldmfdeq sp!, {r4, r5, pc} 84 84 85 85 cmp r2, #2 86 86 ldrb r3, [r1], #1 87 87 strb r3, [r0] 88 - ldrgeb r3, [r1], #1 89 - strgeb r3, [r0] 90 - ldrgtb r3, [r1] 91 - strgtb r3, [r0] 88 + ldrbge r3, [r1], #1 89 + strbge r3, [r0] 90 + ldrbgt r3, [r1] 91 + strbgt r3, [r0] 92 92 93 93 ldmfd sp!, {r4, r5, pc} 94 94 ENDPROC(__raw_writesb)
+1 -1
arch/arm/lib/io-writesl.S
··· 28 28 bpl 1b 29 29 ldmfd sp!, {r4, lr} 30 30 2: movs r2, r2, lsl #31 31 - ldmcsia r1!, {r3, ip} 31 + ldmiacs r1!, {r3, ip} 32 32 strcs r3, [r0, #0] 33 33 ldrne r3, [r1, #0] 34 34 strcs ip, [r0, #0]
+1 -1
arch/arm/lib/io-writesw-armv3.S
··· 79 79 bpl .Loutsw_8_lp 80 80 81 81 tst r2, #7 82 - ldmeqfd sp!, {r4, r5, r6, pc} 82 + ldmfdeq sp!, {r4, r5, r6, pc} 83 83 84 84 .Lno_outsw_8: tst r2, #4 85 85 beq .Lno_outsw_4
+3 -3
arch/arm/lib/io-writesw-armv4.S
··· 61 61 ldr r3, [r1], #4 62 62 outword r3 63 63 64 - .Lno_outsw_2: ldrneh r3, [r1] 65 - strneh r3, [r0] 64 + .Lno_outsw_2: ldrhne r3, [r1] 65 + strhne r3, [r0] 66 66 67 67 ldmfd sp!, {r4, r5, pc} 68 68 ··· 95 95 96 96 tst r2, #1 97 97 3: movne ip, r3, lsr #8 98 - strneh ip, [r0] 98 + strhne ip, [r0] 99 99 ret lr 100 100 ENDPROC(__raw_writesw)
+2 -2
arch/arm/lib/lib1funcs.S
··· 96 96 subhs \dividend, \dividend, \divisor, lsr #3 97 97 orrhs \result, \result, \curbit, lsr #3 98 98 cmp \dividend, #0 @ Early termination? 99 - movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? 99 + movsne \curbit, \curbit, lsr #4 @ No, any more bits to do? 100 100 movne \divisor, \divisor, lsr #4 101 101 bne 1b 102 102 ··· 182 182 subhs \dividend, \dividend, \divisor, lsr #3 183 183 cmp \dividend, #1 184 184 mov \divisor, \divisor, lsr #4 185 - subges \order, \order, #4 185 + subsge \order, \order, #4 186 186 bge 1b 187 187 188 188 tst \order, #3
+2 -2
arch/arm/lib/memcpy.S
··· 30 30 .endm 31 31 32 32 .macro ldr1b ptr reg cond=al abort 33 - ldr\cond\()b \reg, [\ptr], #1 33 + ldrb\cond \reg, [\ptr], #1 34 34 .endm 35 35 36 36 .macro str1w ptr reg abort ··· 42 42 .endm 43 43 44 44 .macro str1b ptr reg cond=al abort 45 - str\cond\()b \reg, [\ptr], #1 45 + strb\cond \reg, [\ptr], #1 46 46 .endm 47 47 48 48 .macro enter reg1 reg2
+12 -12
arch/arm/lib/memmove.S
··· 59 59 blt 5f 60 60 61 61 CALGN( ands ip, r0, #31 ) 62 - CALGN( sbcnes r4, ip, r2 ) @ C is always set here 62 + CALGN( sbcsne r4, ip, r2 ) @ C is always set here 63 63 CALGN( bcs 2f ) 64 64 CALGN( adr r4, 6f ) 65 65 CALGN( subs r2, r2, ip ) @ C is set here ··· 114 114 UNWIND( .save {r0, r4, lr} ) @ still in first stmfd block 115 115 116 116 8: movs r2, r2, lsl #31 117 - ldrneb r3, [r1, #-1]! 118 - ldrcsb r4, [r1, #-1]! 119 - ldrcsb ip, [r1, #-1] 120 - strneb r3, [r0, #-1]! 121 - strcsb r4, [r0, #-1]! 122 - strcsb ip, [r0, #-1] 117 + ldrbne r3, [r1, #-1]! 118 + ldrbcs r4, [r1, #-1]! 119 + ldrbcs ip, [r1, #-1] 120 + strbne r3, [r0, #-1]! 121 + strbcs r4, [r0, #-1]! 122 + strbcs ip, [r0, #-1] 123 123 ldmfd sp!, {r0, r4, pc} 124 124 125 125 9: cmp ip, #2 126 - ldrgtb r3, [r1, #-1]! 127 - ldrgeb r4, [r1, #-1]! 126 + ldrbgt r3, [r1, #-1]! 127 + ldrbge r4, [r1, #-1]! 128 128 ldrb lr, [r1, #-1]! 129 - strgtb r3, [r0, #-1]! 130 - strgeb r4, [r0, #-1]! 129 + strbgt r3, [r0, #-1]! 130 + strbge r4, [r0, #-1]! 131 131 subs r2, r2, ip 132 132 strb lr, [r0, #-1]! 133 133 blt 8b ··· 150 150 blt 14f 151 151 152 152 CALGN( ands ip, r0, #31 ) 153 - CALGN( sbcnes r4, ip, r2 ) @ C is always set here 153 + CALGN( sbcsne r4, ip, r2 ) @ C is always set here 154 154 CALGN( subcc r2, r2, ip ) 155 155 CALGN( bcc 15f ) 156 156
+21 -21
arch/arm/lib/memset.S
··· 44 44 mov lr, r3 45 45 46 46 2: subs r2, r2, #64 47 - stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time. 48 - stmgeia ip!, {r1, r3, r8, lr} 49 - stmgeia ip!, {r1, r3, r8, lr} 50 - stmgeia ip!, {r1, r3, r8, lr} 47 + stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time. 48 + stmiage ip!, {r1, r3, r8, lr} 49 + stmiage ip!, {r1, r3, r8, lr} 50 + stmiage ip!, {r1, r3, r8, lr} 51 51 bgt 2b 52 - ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. 52 + ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go. 53 53 /* 54 54 * No need to correct the count; we're only testing bits from now on 55 55 */ 56 56 tst r2, #32 57 - stmneia ip!, {r1, r3, r8, lr} 58 - stmneia ip!, {r1, r3, r8, lr} 57 + stmiane ip!, {r1, r3, r8, lr} 58 + stmiane ip!, {r1, r3, r8, lr} 59 59 tst r2, #16 60 - stmneia ip!, {r1, r3, r8, lr} 60 + stmiane ip!, {r1, r3, r8, lr} 61 61 ldmfd sp!, {r8, lr} 62 62 UNWIND( .fnend ) 63 63 ··· 87 87 rsb r8, r8, #32 88 88 sub r2, r2, r8 89 89 movs r8, r8, lsl #(32 - 4) 90 - stmcsia ip!, {r4, r5, r6, r7} 91 - stmmiia ip!, {r4, r5} 90 + stmiacs ip!, {r4, r5, r6, r7} 91 + stmiami ip!, {r4, r5} 92 92 tst r8, #(1 << 30) 93 93 mov r8, r1 94 94 strne r1, [ip], #4 95 95 96 96 3: subs r2, r2, #64 97 - stmgeia ip!, {r1, r3-r8, lr} 98 - stmgeia ip!, {r1, r3-r8, lr} 97 + stmiage ip!, {r1, r3-r8, lr} 98 + stmiage ip!, {r1, r3-r8, lr} 99 99 bgt 3b 100 - ldmeqfd sp!, {r4-r8, pc} 100 + ldmfdeq sp!, {r4-r8, pc} 101 101 102 102 tst r2, #32 103 - stmneia ip!, {r1, r3-r8, lr} 103 + stmiane ip!, {r1, r3-r8, lr} 104 104 tst r2, #16 105 - stmneia ip!, {r4-r7} 105 + stmiane ip!, {r4-r7} 106 106 ldmfd sp!, {r4-r8, lr} 107 107 UNWIND( .fnend ) 108 108 ··· 110 110 111 111 UNWIND( .fnstart ) 112 112 4: tst r2, #8 113 - stmneia ip!, {r1, r3} 113 + stmiane ip!, {r1, r3} 114 114 tst r2, #4 115 115 strne r1, [ip], #4 116 116 /* ··· 118 118 * may have an unaligned pointer as well. 119 119 */ 120 120 5: tst r2, #2 121 - strneb r1, [ip], #1 122 - strneb r1, [ip], #1 121 + strbne r1, [ip], #1 122 + strbne r1, [ip], #1 123 123 tst r2, #1 124 - strneb r1, [ip], #1 124 + strbne r1, [ip], #1 125 125 ret lr 126 126 127 127 6: subs r2, r2, #4 @ 1 do we have enough 128 128 blt 5b @ 1 bytes to align with? 129 129 cmp r3, #2 @ 1 130 - strltb r1, [ip], #1 @ 1 131 - strleb r1, [ip], #1 @ 1 130 + strblt r1, [ip], #1 @ 1 131 + strble r1, [ip], #1 @ 1 132 132 strb r1, [ip], #1 @ 1 133 133 add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) 134 134 b 1b
+1 -1
arch/arm/lib/xor-neon.c
··· 14 14 MODULE_LICENSE("GPL"); 15 15 16 16 #ifndef __ARM_NEON__ 17 - #error You should compile this file with '-mfloat-abi=softfp -mfpu=neon' 17 + #error You should compile this file with '-march=armv7-a -mfloat-abi=softfp -mfpu=neon' 18 18 #endif 19 19 20 20 /*
-15
arch/arm/mach-actions/platsmp.c
··· 39 39 static void __iomem *timer_base_addr; 40 40 static int ncores; 41 41 42 - static DEFINE_SPINLOCK(boot_lock); 43 - 44 - void owl_secondary_startup(void); 45 - 46 42 static int s500_wakeup_secondary(unsigned int cpu) 47 43 { 48 44 int ret; ··· 80 84 81 85 static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) 82 86 { 83 - unsigned long timeout; 84 87 int ret; 85 88 86 89 ret = s500_wakeup_secondary(cpu); ··· 88 93 89 94 udelay(10); 90 95 91 - spin_lock(&boot_lock); 92 - 93 96 smp_send_reschedule(cpu); 94 - 95 - timeout = jiffies + (1 * HZ); 96 - while (time_before(jiffies, timeout)) { 97 - if (pen_release == -1) 98 - break; 99 - } 100 97 101 98 writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); 102 99 writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); 103 - 104 - spin_unlock(&boot_lock); 105 100 106 101 return 0; 107 102 }
+1 -1
arch/arm/mach-exynos/headsmp.S
··· 36 36 37 37 .align 2 38 38 1: .long . 39 - .long pen_release 39 + .long exynos_pen_release
+18 -13
arch/arm/mach-exynos/platsmp.c
··· 28 28 29 29 extern void exynos4_secondary_startup(void); 30 30 31 + /* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX */ 32 + volatile int exynos_pen_release = -1; 33 + 31 34 #ifdef CONFIG_HOTPLUG_CPU 32 35 static inline void cpu_leave_lowpower(u32 core_id) 33 36 { ··· 60 57 61 58 wfi(); 62 59 63 - if (pen_release == core_id) { 60 + if (exynos_pen_release == core_id) { 64 61 /* 65 62 * OK, proper wakeup, we're done 66 63 */ ··· 231 228 } 232 229 233 230 /* 234 - * Write pen_release in a way that is guaranteed to be visible to all 235 - * observers, irrespective of whether they're taking part in coherency 231 + * XXX CARGO CULTED CODE - DO NOT COPY XXX 232 + * 233 + * Write exynos_pen_release in a way that is guaranteed to be visible to 234 + * all observers, irrespective of whether they're taking part in coherency 236 235 * or not. This is necessary for the hotplug code to work reliably. 237 236 */ 238 - static void write_pen_release(int val) 237 + static void exynos_write_pen_release(int val) 239 238 { 240 - pen_release = val; 239 + exynos_pen_release = val; 241 240 smp_wmb(); 242 - sync_cache_w(&pen_release); 241 + sync_cache_w(&exynos_pen_release); 243 242 } 244 243 245 244 static DEFINE_SPINLOCK(boot_lock); ··· 252 247 * let the primary processor know we're out of the 253 248 * pen, then head off into the C entry point 254 249 */ 255 - write_pen_release(-1); 250 + exynos_write_pen_release(-1); 256 251 257 252 /* 258 253 * Synchronise with the boot thread. ··· 327 322 /* 328 323 * The secondary processor is waiting to be released from 329 324 * the holding pen - release it, then wait for it to flag 330 - * that it has been released by resetting pen_release. 325 + * that it has been released by resetting exynos_pen_release. 331 326 * 332 - * Note that "pen_release" is the hardware CPU core ID, whereas 327 + * Note that "exynos_pen_release" is the hardware CPU core ID, whereas 333 328 * "cpu" is Linux's internal ID. 334 329 */ 335 - write_pen_release(core_id); 330 + exynos_write_pen_release(core_id); 336 331 337 332 if (!exynos_cpu_power_state(core_id)) { 338 333 exynos_cpu_power_up(core_id); ··· 381 376 else 382 377 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 383 378 384 - if (pen_release == -1) 379 + if (exynos_pen_release == -1) 385 380 break; 386 381 387 382 udelay(10); 388 383 } 389 384 390 - if (pen_release != -1) 385 + if (exynos_pen_release != -1) 391 386 ret = -ETIMEDOUT; 392 387 393 388 /* ··· 397 392 fail: 398 393 spin_unlock(&boot_lock); 399 394 400 - return pen_release != -1 ? ret : 0; 395 + return exynos_pen_release != -1 ? ret : 0; 401 396 } 402 397 403 398 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
+1 -1
arch/arm/mach-ks8695/include/mach/entry-macro.S
··· 42 42 moveq \irqstat, \irqstat, lsr #2 43 43 addeq \irqnr, \irqnr, #2 44 44 tst \irqstat, #0x01 45 - addeqs \irqnr, \irqnr, #1 45 + addseq \irqnr, \irqnr, #1 46 46 1001: 47 47 .endm
+3 -1
arch/arm/mach-omap2/prm_common.c
··· 523 523 524 524 prm_ll_data->reset_system(); 525 525 526 - while (1) 526 + while (1) { 527 527 cpu_relax(); 528 + wfe(); 529 + } 528 530 } 529 531 530 532 /**
-1
arch/arm/mach-oxnas/Makefile
··· 1 1 obj-$(CONFIG_SMP) += platsmp.o headsmp.o 2 - obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-109
arch/arm/mach-oxnas/hotplug.c
··· 1 - /* 2 - * Copyright (C) 2002 ARM Ltd. 3 - * All Rights Reserved 4 - * 5 - * This program is free software; you can redistribute it and/or modify 6 - * it under the terms of the GNU General Public License version 2 as 7 - * published by the Free Software Foundation. 8 - */ 9 - #include <linux/kernel.h> 10 - #include <linux/errno.h> 11 - #include <linux/smp.h> 12 - 13 - #include <asm/cp15.h> 14 - #include <asm/smp_plat.h> 15 - 16 - static inline void cpu_enter_lowpower(void) 17 - { 18 - unsigned int v; 19 - 20 - asm volatile( 21 - " mcr p15, 0, %1, c7, c5, 0\n" 22 - " mcr p15, 0, %1, c7, c10, 4\n" 23 - /* 24 - * Turn off coherency 25 - */ 26 - " mrc p15, 0, %0, c1, c0, 1\n" 27 - " bic %0, %0, #0x20\n" 28 - " mcr p15, 0, %0, c1, c0, 1\n" 29 - " mrc p15, 0, %0, c1, c0, 0\n" 30 - " bic %0, %0, %2\n" 31 - " mcr p15, 0, %0, c1, c0, 0\n" 32 - : "=&r" (v) 33 - : "r" (0), "Ir" (CR_C) 34 - : "cc"); 35 - } 36 - 37 - static inline void cpu_leave_lowpower(void) 38 - { 39 - unsigned int v; 40 - 41 - asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" 42 - " orr %0, %0, %1\n" 43 - " mcr p15, 0, %0, c1, c0, 0\n" 44 - " mrc p15, 0, %0, c1, c0, 1\n" 45 - " orr %0, %0, #0x20\n" 46 - " mcr p15, 0, %0, c1, c0, 1\n" 47 - : "=&r" (v) 48 - : "Ir" (CR_C) 49 - : "cc"); 50 - } 51 - 52 - static inline void platform_do_lowpower(unsigned int cpu, int *spurious) 53 - { 54 - /* 55 - * there is no power-control hardware on this platform, so all 56 - * we can do is put the core into WFI; this is safe as the calling 57 - * code will have already disabled interrupts 58 - */ 59 - for (;;) { 60 - /* 61 - * here's the WFI 62 - */ 63 - asm(".word 0xe320f003\n" 64 - : 65 - : 66 - : "memory", "cc"); 67 - 68 - if (pen_release == cpu_logical_map(cpu)) { 69 - /* 70 - * OK, proper wakeup, we're done 71 - */ 72 - break; 73 - } 74 - 75 - /* 76 - * Getting here, means that we have come out of WFI without 77 - * having been woken up - this shouldn't happen 78 - * 79 - * Just note it happening - when we're woken, we can report 80 - * its occurrence. 81 - */ 82 - (*spurious)++; 83 - } 84 - } 85 - 86 - /* 87 - * platform-specific code to shutdown a CPU 88 - * 89 - * Called with IRQs disabled 90 - */ 91 - void ox820_cpu_die(unsigned int cpu) 92 - { 93 - int spurious = 0; 94 - 95 - /* 96 - * we're ready for shutdown now, so do it 97 - */ 98 - cpu_enter_lowpower(); 99 - platform_do_lowpower(cpu, &spurious); 100 - 101 - /* 102 - * bring this CPU back into the world of cache 103 - * coherency, and then restore interrupts 104 - */ 105 - cpu_leave_lowpower(); 106 - 107 - if (spurious) 108 - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); 109 - }
-4
arch/arm/mach-oxnas/platsmp.c
··· 19 19 #include <asm/smp_scu.h> 20 20 21 21 extern void ox820_secondary_startup(void); 22 - extern void ox820_cpu_die(unsigned int cpu); 23 22 24 23 static void __iomem *cpu_ctrl; 25 24 static void __iomem *gic_cpu_ctrl; ··· 93 94 static const struct smp_operations ox820_smp_ops __initconst = { 94 95 .smp_prepare_cpus = ox820_smp_prepare_cpus, 95 96 .smp_boot_secondary = ox820_boot_secondary, 96 - #ifdef CONFIG_HOTPLUG_CPU 97 - .cpu_die = ox820_cpu_die, 98 - #endif 99 97 }; 100 98 101 99 CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
+2
arch/arm/mach-prima2/common.h
··· 15 15 #include <asm/mach/time.h> 16 16 #include <asm/exception.h> 17 17 18 + extern volatile int prima2_pen_release; 19 + 18 20 extern const struct smp_operations sirfsoc_smp_ops; 19 21 extern void sirfsoc_secondary_startup(void); 20 22 extern void sirfsoc_cpu_die(unsigned int cpu);
+1 -1
arch/arm/mach-prima2/headsmp.S
··· 34 34 35 35 .align 36 36 1: .long . 37 - .long pen_release 37 + .long prima2_pen_release
+2 -1
arch/arm/mach-prima2/hotplug.c
··· 11 11 #include <linux/smp.h> 12 12 13 13 #include <asm/smp_plat.h> 14 + #include "common.h" 14 15 15 16 static inline void platform_do_lowpower(unsigned int cpu) 16 17 { ··· 19 18 for (;;) { 20 19 __asm__ __volatile__("dsb\n\t" "wfi\n\t" 21 20 : : : "memory"); 22 - if (pen_release == cpu_logical_map(cpu)) { 21 + if (prima2_pen_release == cpu_logical_map(cpu)) { 23 22 /* 24 23 * OK, proper wakeup, we're done 25 24 */
+10 -7
arch/arm/mach-prima2/platsmp.c
··· 24 24 25 25 static DEFINE_SPINLOCK(boot_lock); 26 26 27 + /* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */ 28 + volatile int prima2_pen_release = -1; 29 + 27 30 static void sirfsoc_secondary_init(unsigned int cpu) 28 31 { 29 32 /* 30 33 * let the primary processor know we're out of the 31 34 * pen, then head off into the C entry point 32 35 */ 33 - pen_release = -1; 36 + prima2_pen_release = -1; 34 37 smp_wmb(); 35 38 36 39 /* ··· 83 80 /* 84 81 * The secondary processor is waiting to be released from 85 82 * the holding pen - release it, then wait for it to flag 86 - * that it has been released by resetting pen_release. 83 + * that it has been released by resetting prima2_pen_release. 87 84 * 88 - * Note that "pen_release" is the hardware CPU ID, whereas 85 + * Note that "prima2_pen_release" is the hardware CPU ID, whereas 89 86 * "cpu" is Linux's internal ID. 90 87 */ 91 - pen_release = cpu_logical_map(cpu); 92 - sync_cache_w(&pen_release); 88 + prima2_pen_release = cpu_logical_map(cpu); 89 + sync_cache_w(&prima2_pen_release); 93 90 94 91 /* 95 92 * Send the secondary CPU SEV, thereby causing the boot monitor to read ··· 100 97 timeout = jiffies + (1 * HZ); 101 98 while (time_before(jiffies, timeout)) { 102 99 smp_rmb(); 103 - if (pen_release == -1) 100 + if (prima2_pen_release == -1) 104 101 break; 105 102 106 103 udelay(10); ··· 112 109 */ 113 110 spin_unlock(&boot_lock); 114 111 115 - return pen_release != -1 ? -ENOSYS : 0; 112 + return prima2_pen_release != -1 ? -ENOSYS : 0; 116 113 } 117 114 118 115 const struct smp_operations sirfsoc_smp_ops __initconst = {
-26
arch/arm/mach-qcom/platsmp.c
··· 46 46 47 47 extern void secondary_startup_arm(void); 48 48 49 - static DEFINE_SPINLOCK(boot_lock); 50 - 51 49 #ifdef CONFIG_HOTPLUG_CPU 52 50 static void qcom_cpu_die(unsigned int cpu) 53 51 { 54 52 wfi(); 55 53 } 56 54 #endif 57 - 58 - static void qcom_secondary_init(unsigned int cpu) 59 - { 60 - /* 61 - * Synchronise with the boot thread. 62 - */ 63 - spin_lock(&boot_lock); 64 - spin_unlock(&boot_lock); 65 - } 66 55 67 56 static int scss_release_secondary(unsigned int cpu) 68 57 { ··· 270 281 } 271 282 272 283 /* 273 - * set synchronisation state between this boot processor 274 - * and the secondary one 275 - */ 276 - spin_lock(&boot_lock); 277 - 278 - /* 279 284 * Send the secondary CPU a soft interrupt, thereby causing 280 285 * the boot monitor to read the system wide flags register, 281 286 * and branch to the address found there. 282 287 */ 283 288 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 284 - 285 - /* 286 - * now the secondary core is starting up let it run its 287 - * calibrations, then wait for it to finish 288 - */ 289 - spin_unlock(&boot_lock); 290 289 291 290 return ret; 292 291 } ··· 311 334 312 335 static const struct smp_operations smp_msm8660_ops __initconst = { 313 336 .smp_prepare_cpus = qcom_smp_prepare_cpus, 314 - .smp_secondary_init = qcom_secondary_init, 315 337 .smp_boot_secondary = msm8660_boot_secondary, 316 338 #ifdef CONFIG_HOTPLUG_CPU 317 339 .cpu_die = qcom_cpu_die, ··· 320 344 321 345 static const struct smp_operations qcom_smp_kpssv1_ops __initconst = { 322 346 .smp_prepare_cpus = qcom_smp_prepare_cpus, 323 - .smp_secondary_init = qcom_secondary_init, 324 347 .smp_boot_secondary = kpssv1_boot_secondary, 325 348 #ifdef CONFIG_HOTPLUG_CPU 326 349 .cpu_die = qcom_cpu_die, ··· 329 354 330 355 static const struct smp_operations qcom_smp_kpssv2_ops __initconst = { 331 356 .smp_prepare_cpus = qcom_smp_prepare_cpus, 332 - .smp_secondary_init = qcom_secondary_init, 333 357 .smp_boot_secondary = kpssv2_boot_secondary, 334 358 #ifdef CONFIG_HOTPLUG_CPU 335 359 .cpu_die = qcom_cpu_die,
+2
arch/arm/mach-spear/generic.h
··· 20 20 21 21 #include <asm/mach/time.h> 22 22 23 + extern volatile int spear_pen_release; 24 + 23 25 extern void spear13xx_timer_init(void); 24 26 extern void spear3xx_timer_init(void); 25 27 extern struct pl022_ssp_controller pl022_plat_data;
+1 -1
arch/arm/mach-spear/headsmp.S
··· 43 43 44 44 .align 45 45 1: .long . 46 - .long pen_release 46 + .long spear_pen_release 47 47 ENDPROC(spear13xx_secondary_startup)
+3 -1
arch/arm/mach-spear/hotplug.c
··· 16 16 #include <asm/cp15.h> 17 17 #include <asm/smp_plat.h> 18 18 19 + #include "generic.h" 20 + 19 21 static inline void cpu_enter_lowpower(void) 20 22 { 21 23 unsigned int v; ··· 59 57 for (;;) { 60 58 wfi(); 61 59 62 - if (pen_release == cpu) { 60 + if (spear_pen_release == cpu) { 63 61 /* 64 62 * OK, proper wakeup, we're done 65 63 */
+16 -11
arch/arm/mach-spear/platsmp.c
··· 20 20 #include <mach/spear.h> 21 21 #include "generic.h" 22 22 23 + /* XXX spear_pen_release is cargo culted code - DO NOT COPY XXX */ 24 + volatile int spear_pen_release = -1; 25 + 23 26 /* 24 - * Write pen_release in a way that is guaranteed to be visible to all 25 - * observers, irrespective of whether they're taking part in coherency 27 + * XXX CARGO CULTED CODE - DO NOT COPY XXX 28 + * 29 + * Write spear_pen_release in a way that is guaranteed to be visible to 30 + * all observers, irrespective of whether they're taking part in coherency 26 31 * or not. This is necessary for the hotplug code to work reliably. 27 32 */ 28 - static void write_pen_release(int val) 33 + static void spear_write_pen_release(int val) 29 34 { 30 - pen_release = val; 35 + spear_pen_release = val; 31 36 smp_wmb(); 32 - sync_cache_w(&pen_release); 37 + sync_cache_w(&spear_pen_release); 33 38 } 34 39 35 40 static DEFINE_SPINLOCK(boot_lock); ··· 47 42 * let the primary processor know we're out of the 48 43 * pen, then head off into the C entry point 49 44 */ 50 - write_pen_release(-1); 45 + spear_write_pen_release(-1); 51 46 52 47 /* 53 48 * Synchronise with the boot thread. ··· 69 64 /* 70 65 * The secondary processor is waiting to be released from 71 66 * the holding pen - release it, then wait for it to flag 72 - * that it has been released by resetting pen_release. 67 + * that it has been released by resetting spear_pen_release. 73 68 * 74 - * Note that "pen_release" is the hardware CPU ID, whereas 69 + * Note that "spear_pen_release" is the hardware CPU ID, whereas 75 70 * "cpu" is Linux's internal ID. 76 71 */ 77 - write_pen_release(cpu); 72 + spear_write_pen_release(cpu); 78 73 79 74 timeout = jiffies + (1 * HZ); 80 75 while (time_before(jiffies, timeout)) { 81 76 smp_rmb(); 82 - if (pen_release == -1) 77 + if (spear_pen_release == -1) 83 78 break; 84 79 85 80 udelay(10); ··· 91 86 */ 92 87 spin_unlock(&boot_lock); 93 88 94 - return pen_release != -1 ? -ENOSYS : 0; 89 + return spear_pen_release != -1 ? -ENOSYS : 0; 95 90 } 96 91 97 92 /*
+1 -1
arch/arm/mach-tegra/reset-handler.S
··· 172 172 mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET 173 173 mov r0, #CPU_NOT_RESETTABLE 174 174 cmp r10, #0 175 - strneb r0, [r5, #__tegra20_cpu1_resettable_status_offset] 175 + strbne r0, [r5, #__tegra20_cpu1_resettable_status_offset] 176 176 1: 177 177 #endif 178 178
+4 -4
arch/arm/mm/cache-v6.S
··· 215 215 #endif 216 216 tst r1, #D_CACHE_LINE_SIZE - 1 217 217 #ifdef CONFIG_DMA_CACHE_RWFO 218 - ldrneb r2, [r1, #-1] @ read for ownership 219 - strneb r2, [r1, #-1] @ write for ownership 218 + ldrbne r2, [r1, #-1] @ read for ownership 219 + strbne r2, [r1, #-1] @ write for ownership 220 220 #endif 221 221 bic r1, r1, #D_CACHE_LINE_SIZE - 1 222 222 #ifdef HARVARD_CACHE ··· 284 284 add r0, r0, #D_CACHE_LINE_SIZE 285 285 cmp r0, r1 286 286 #ifdef CONFIG_DMA_CACHE_RWFO 287 - ldrlob r2, [r0] @ read for ownership 288 - strlob r2, [r0] @ write for ownership 287 + ldrblo r2, [r0] @ read for ownership 288 + strblo r2, [r0] @ write for ownership 289 289 #endif 290 290 blo 1b 291 291 mov r0, #0
+2 -1
arch/arm/mm/copypage-v4mc.c
··· 45 45 int tmp; 46 46 47 47 asm volatile ("\ 48 + .syntax unified\n\ 48 49 ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 49 50 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ 50 51 stmia %1!, {r2, r3, ip, lr} @ 4\n\ ··· 57 56 ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 58 57 subs %2, %2, #1 @ 1\n\ 59 58 stmia %1!, {r2, r3, ip, lr} @ 4\n\ 60 - ldmneia %0!, {r2, r3, ip, lr} @ 4\n\ 59 + ldmiane %0!, {r2, r3, ip, lr} @ 4\n\ 61 60 bne 1b @ " 62 61 : "+&r" (from), "+&r" (to), "=&r" (tmp) 63 62 : "2" (PAGE_SIZE / 64)
+2 -1
arch/arm/mm/copypage-v4wb.c
··· 27 27 int tmp; 28 28 29 29 asm volatile ("\ 30 + .syntax unified\n\ 30 31 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 31 32 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ 32 33 stmia %0!, {r3, r4, ip, lr} @ 4\n\ ··· 39 38 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 40 39 subs %2, %2, #1 @ 1\n\ 41 40 stmia %0!, {r3, r4, ip, lr} @ 4\n\ 42 - ldmneia %1!, {r3, r4, ip, lr} @ 4\n\ 41 + ldmiane %1!, {r3, r4, ip, lr} @ 4\n\ 43 42 bne 1b @ 1\n\ 44 43 mcr p15, 0, %1, c7, c10, 4 @ 1 drain WB" 45 44 : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
+2 -1
arch/arm/mm/copypage-v4wt.c
··· 25 25 int tmp; 26 26 27 27 asm volatile ("\ 28 + .syntax unified\n\ 28 29 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 29 30 1: stmia %0!, {r3, r4, ip, lr} @ 4\n\ 30 31 ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\ ··· 35 34 ldmia %1!, {r3, r4, ip, lr} @ 4\n\ 36 35 subs %2, %2, #1 @ 1\n\ 37 36 stmia %0!, {r3, r4, ip, lr} @ 4\n\ 38 - ldmneia %1!, {r3, r4, ip, lr} @ 4\n\ 37 + ldmiane %1!, {r3, r4, ip, lr} @ 4\n\ 39 38 bne 1b @ 1\n\ 40 39 mcr p15, 0, %2, c7, c7, 0 @ flush ID cache" 41 40 : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
+1 -1
arch/arm/mm/dma-mapping.c
··· 2279 2279 * @dev: valid struct device pointer 2280 2280 * 2281 2281 * Detaches the provided device from a previously attached map. 2282 - * This voids the dma operations (dma_map_ops pointer) 2282 + * This overwrites the dma_ops pointer with appropriate non-IOMMU ops. 2283 2283 */ 2284 2284 void arm_iommu_detach_device(struct device *dev) 2285 2285 {
+3 -1
arch/arm/mm/idmap.c
··· 6 6 7 7 #include <asm/cputype.h> 8 8 #include <asm/idmap.h> 9 + #include <asm/hwcap.h> 9 10 #include <asm/pgalloc.h> 10 11 #include <asm/pgtable.h> 11 12 #include <asm/sections.h> ··· 111 110 __idmap_text_end, 0); 112 111 113 112 /* Flush L1 for the hardware to see this page table content */ 114 - flush_cache_louis(); 113 + if (!(elf_hwcap & HWCAP_LPAE)) 114 + flush_cache_louis(); 115 115 116 116 return 0; 117 117 }
+4 -65
arch/arm/mm/init.c
··· 282 282 283 283 void __init bootmem_init(void) 284 284 { 285 - unsigned long min, max_low, max_high; 286 - 287 285 memblock_allow_resize(); 288 - max_low = max_high = 0; 289 286 290 - find_limits(&min, &max_low, &max_high); 287 + find_limits(&min_low_pfn, &max_low_pfn, &max_pfn); 291 288 292 - early_memtest((phys_addr_t)min << PAGE_SHIFT, 293 - (phys_addr_t)max_low << PAGE_SHIFT); 289 + early_memtest((phys_addr_t)min_low_pfn << PAGE_SHIFT, 290 + (phys_addr_t)max_low_pfn << PAGE_SHIFT); 294 291 295 292 /* 296 293 * Sparsemem tries to allocate bootmem in memory_present(), ··· 305 308 * the sparse mem_map arrays initialized by sparse_init() 306 309 * for memmap_init_zone(), otherwise all PFNs are invalid. 307 310 */ 308 - zone_sizes_init(min, max_low, max_high); 309 - 310 - /* 311 - * This doesn't seem to be used by the Linux memory manager any 312 - * more, but is used by ll_rw_block. If we can get rid of it, we 313 - * also get rid of some of the stuff above as well. 314 - */ 315 - min_low_pfn = min; 316 - max_low_pfn = max_low; 317 - max_pfn = max_high; 311 + zone_sizes_init(min_low_pfn, max_low_pfn, max_pfn); 318 312 } 319 313 320 314 /* ··· 485 497 free_highpages(); 486 498 487 499 mem_init_print_info(NULL); 488 - 489 - #define MLK(b, t) b, t, ((t) - (b)) >> 10 490 - #define MLM(b, t) b, t, ((t) - (b)) >> 20 491 - #define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K) 492 - 493 - pr_notice("Virtual kernel memory layout:\n" 494 - " vector : 0x%08lx - 0x%08lx (%4ld kB)\n" 495 - #ifdef CONFIG_HAVE_TCM 496 - " DTCM : 0x%08lx - 0x%08lx (%4ld kB)\n" 497 - " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n" 498 - #endif 499 - " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" 500 - " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n" 501 - " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n" 502 - #ifdef CONFIG_HIGHMEM 503 - " pkmap : 0x%08lx - 0x%08lx (%4ld MB)\n" 504 - #endif 505 - #ifdef CONFIG_MODULES 506 - " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" 507 - #endif 508 - " .text : 0x%p" " - 0x%p" " (%4td kB)\n" 509 - " .init : 0x%p" " - 0x%p" " (%4td kB)\n" 510 - " .data : 0x%p" " - 0x%p" " (%4td kB)\n" 511 - " .bss : 0x%p" " - 0x%p" " (%4td kB)\n", 512 - 513 - MLK(VECTORS_BASE, VECTORS_BASE + PAGE_SIZE), 514 - #ifdef CONFIG_HAVE_TCM 515 - MLK(DTCM_OFFSET, (unsigned long) dtcm_end), 516 - MLK(ITCM_OFFSET, (unsigned long) itcm_end), 517 - #endif 518 - MLK(FIXADDR_START, FIXADDR_END), 519 - MLM(VMALLOC_START, VMALLOC_END), 520 - MLM(PAGE_OFFSET, (unsigned long)high_memory), 521 - #ifdef CONFIG_HIGHMEM 522 - MLM(PKMAP_BASE, (PKMAP_BASE) + (LAST_PKMAP) * 523 - (PAGE_SIZE)), 524 - #endif 525 - #ifdef CONFIG_MODULES 526 - MLM(MODULES_VADDR, MODULES_END), 527 - #endif 528 - 529 - MLK_ROUNDUP(_text, _etext), 530 - MLK_ROUNDUP(__init_begin, __init_end), 531 - MLK_ROUNDUP(_sdata, _edata), 532 - MLK_ROUNDUP(__bss_start, __bss_stop)); 533 - 534 - #undef MLK 535 - #undef MLM 536 - #undef MLK_ROUNDUP 537 500 538 501 /* 539 502 * Check boundaries twice: Some fundamental inconsistencies can
+2 -2
arch/arm/mm/pmsa-v8.c
··· 165 165 return -EINVAL; 166 166 167 167 bar = start; 168 - lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);; 168 + lar = (end - 1) & ~(PMSAv8_MINALIGN - 1); 169 169 170 170 bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED; 171 171 lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN; ··· 181 181 return -EINVAL; 182 182 183 183 bar = start; 184 - lar = (end - 1) & ~(PMSAv8_MINALIGN - 1);; 184 + lar = (end - 1) & ~(PMSAv8_MINALIGN - 1); 185 185 186 186 bar |= PMSAv8_AP_PL1RW_PL0RW | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN; 187 187 lar |= PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN;
+5 -2
arch/arm/mm/proc-v7m.S
··· 139 139 cpsie i 140 140 svc #0 141 141 1: cpsid i 142 + ldr r0, =exc_ret 143 + orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK 144 + str lr, [r0] 142 145 ldmia sp, {r0-r3, r12} 143 146 str r5, [r12, #11 * 4] @ restore the original SVC vector entry 144 147 mov lr, r6 @ restore LR ··· 152 149 153 150 @ Configure caches (if implemented) 154 151 teq r8, #0 155 - stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 152 + stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 156 153 blne v7m_invalidate_l1 157 154 teq r8, #0 @ re-evalutae condition 158 - ldmneia sp, {r0-r6, lr} 155 + ldmiane sp, {r0-r6, lr} 159 156 160 157 @ Configure the System Control Register to ensure 8-byte stack alignment 161 158 @ Note the STKALIGN bit is either RW or RAO.
+37 -8
drivers/amba/bus.c
··· 26 26 27 27 #define to_amba_driver(d) container_of(d, struct amba_driver, drv) 28 28 29 + /* called on periphid match and class 0x9 coresight device. */ 30 + static int 31 + amba_cs_uci_id_match(const struct amba_id *table, struct amba_device *dev) 32 + { 33 + int ret = 0; 34 + struct amba_cs_uci_id *uci; 35 + 36 + uci = table->data; 37 + 38 + /* no table data or zero mask - return match on periphid */ 39 + if (!uci || (uci->devarch_mask == 0)) 40 + return 1; 41 + 42 + /* test against read devtype and masked devarch value */ 43 + ret = (dev->uci.devtype == uci->devtype) && 44 + ((dev->uci.devarch & uci->devarch_mask) == uci->devarch); 45 + return ret; 46 + } 47 + 29 48 static const struct amba_id * 30 49 amba_lookup(const struct amba_id *table, struct amba_device *dev) 31 50 { 32 - int ret = 0; 33 - 34 51 while (table->mask) { 35 - ret = (dev->periphid & table->mask) == table->id; 36 - if (ret) 37 - break; 52 + if (((dev->periphid & table->mask) == table->id) && 53 + ((dev->cid != CORESIGHT_CID) || 54 + (amba_cs_uci_id_match(table, dev)))) 55 + return table; 38 56 table++; 39 57 } 40 - 41 - return ret ? table : NULL; 58 + return NULL; 42 59 } 43 60 44 61 static int amba_match(struct device *dev, struct device_driver *drv) ··· 416 399 cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << 417 400 (i * 8); 418 401 402 + if (cid == CORESIGHT_CID) { 403 + /* set the base to the start of the last 4k block */ 404 + void __iomem *csbase = tmp + size - 4096; 405 + 406 + dev->uci.devarch = 407 + readl(csbase + UCI_REG_DEVARCH_OFFSET); 408 + dev->uci.devtype = 409 + readl(csbase + UCI_REG_DEVTYPE_OFFSET) & 0xff; 410 + } 411 + 419 412 amba_put_disable_pclk(dev); 420 413 421 - if (cid == AMBA_CID || cid == CORESIGHT_CID) 414 + if (cid == AMBA_CID || cid == CORESIGHT_CID) { 422 415 dev->periphid = pid; 416 + dev->cid = cid; 417 + } 423 418 424 419 if (!dev->periphid) 425 420 ret = -ENODEV;
+13 -31
drivers/hwtracing/coresight/coresight-etm3x.c
··· 871 871 } 872 872 873 873 pm_runtime_put(&adev->dev); 874 - dev_info(dev, "%s initialized\n", (char *)id->data); 874 + dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); 875 875 if (boot_enable) { 876 876 coresight_enable(drvdata->csdev); 877 877 drvdata->boot_enable = true; ··· 915 915 }; 916 916 917 917 static const struct amba_id etm_ids[] = { 918 - { /* ETM 3.3 */ 919 - .id = 0x000bb921, 920 - .mask = 0x000fffff, 921 - .data = "ETM 3.3", 922 - }, 923 - { /* ETM 3.5 - Cortex-A5 */ 924 - .id = 0x000bb955, 925 - .mask = 0x000fffff, 926 - .data = "ETM 3.5", 927 - }, 928 - { /* ETM 3.5 */ 929 - .id = 0x000bb956, 930 - .mask = 0x000fffff, 931 - .data = "ETM 3.5", 932 - }, 933 - { /* PTM 1.0 */ 934 - .id = 0x000bb950, 935 - .mask = 0x000fffff, 936 - .data = "PTM 1.0", 937 - }, 938 - { /* PTM 1.1 */ 939 - .id = 0x000bb95f, 940 - .mask = 0x000fffff, 941 - .data = "PTM 1.1", 942 - }, 943 - { /* PTM 1.1 Qualcomm */ 944 - .id = 0x000b006f, 945 - .mask = 0x000fffff, 946 - .data = "PTM 1.1", 947 - }, 918 + /* ETM 3.3 */ 919 + CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"), 920 + /* ETM 3.5 - Cortex-A5 */ 921 + CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"), 922 + /* ETM 3.5 */ 923 + CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"), 924 + /* PTM 1.0 */ 925 + CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"), 926 + /* PTM 1.1 */ 927 + CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"), 928 + /* PTM 1.1 Qualcomm */ 929 + CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"), 948 930 { 0, 0}, 949 931 }; 950 932
+12 -9
drivers/hwtracing/coresight/coresight-etm4x.c
··· 1068 1068 return ret; 1069 1069 } 1070 1070 1071 - #define ETM4x_AMBA_ID(pid) \ 1072 - { \ 1073 - .id = pid, \ 1074 - .mask = 0x000fffff, \ 1071 + static struct amba_cs_uci_id uci_id_etm4[] = { 1072 + { 1073 + /* ETMv4 UCI data */ 1074 + .devarch = 0x47704a13, 1075 + .devarch_mask = 0xfff0ffff, 1076 + .devtype = 0x00000013, 1075 1077 } 1078 + }; 1076 1079 1077 1080 static const struct amba_id etm4_ids[] = { 1078 - ETM4x_AMBA_ID(0x000bb95d), /* Cortex-A53 */ 1079 - ETM4x_AMBA_ID(0x000bb95e), /* Cortex-A57 */ 1080 - ETM4x_AMBA_ID(0x000bb95a), /* Cortex-A72 */ 1081 - ETM4x_AMBA_ID(0x000bb959), /* Cortex-A73 */ 1082 - ETM4x_AMBA_ID(0x000bb9da), /* Cortex-A35 */ 1081 + CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ 1082 + CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ 1083 + CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ 1084 + CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ 1085 + CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */ 1083 1086 {}, 1084 1087 }; 1085 1088
+40
drivers/hwtracing/coresight/coresight-priv.h
··· 6 6 #ifndef _CORESIGHT_PRIV_H 7 7 #define _CORESIGHT_PRIV_H 8 8 9 + #include <linux/amba/bus.h> 9 10 #include <linux/bitops.h> 10 11 #include <linux/io.h> 11 12 #include <linux/coresight.h> ··· 160 159 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } 161 160 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } 162 161 #endif 162 + 163 + /* 164 + * Macros and inline functions to handle CoreSight UCI data and driver 165 + * private data in AMBA ID table entries, and extract data values. 166 + */ 167 + 168 + /* coresight AMBA ID, no UCI, no driver data: id table entry */ 169 + #define CS_AMBA_ID(pid) \ 170 + { \ 171 + .id = pid, \ 172 + .mask = 0x000fffff, \ 173 + } 174 + 175 + /* coresight AMBA ID, UCI with driver data only: id table entry. */ 176 + #define CS_AMBA_ID_DATA(pid, dval) \ 177 + { \ 178 + .id = pid, \ 179 + .mask = 0x000fffff, \ 180 + .data = (void *)&(struct amba_cs_uci_id) \ 181 + { \ 182 + .data = (void *)dval, \ 183 + } \ 184 + } 185 + 186 + /* coresight AMBA ID, full UCI structure: id table entry. */ 187 + #define CS_AMBA_UCI_ID(pid, uci_ptr) \ 188 + { \ 189 + .id = pid, \ 190 + .mask = 0x000fffff, \ 191 + .data = uci_ptr \ 192 + } 193 + 194 + /* extract the data value from a UCI structure given amba_id pointer. */ 195 + static inline void *coresight_get_uci_data(const struct amba_id *id) 196 + { 197 + if (id->data) 198 + return ((struct amba_cs_uci_id *)(id->data))->data; 199 + return 0; 200 + } 163 201 164 202 #endif
+3 -11
drivers/hwtracing/coresight/coresight-stm.c
··· 870 870 871 871 pm_runtime_put(&adev->dev); 872 872 873 - dev_info(dev, "%s initialized\n", (char *)id->data); 873 + dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); 874 874 return 0; 875 875 876 876 stm_unregister: ··· 905 905 }; 906 906 907 907 static const struct amba_id stm_ids[] = { 908 - { 909 - .id = 0x000bb962, 910 - .mask = 0x000fffff, 911 - .data = "STM32", 912 - }, 913 - { 914 - .id = 0x000bb963, 915 - .mask = 0x000fffff, 916 - .data = "STM500", 917 - }, 908 + CS_AMBA_ID_DATA(0x000bb962, "STM32"), 909 + CS_AMBA_ID_DATA(0x000bb963, "STM500"), 918 910 { 0, 0}, 919 911 }; 920 912
+9 -21
drivers/hwtracing/coresight/coresight-tmc.c
··· 443 443 desc.type = CORESIGHT_DEV_TYPE_SINK; 444 444 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 445 445 desc.ops = &tmc_etr_cs_ops; 446 - ret = tmc_etr_setup_caps(drvdata, devid, id->data); 446 + ret = tmc_etr_setup_caps(drvdata, devid, 447 + coresight_get_uci_data(id)); 447 448 if (ret) 448 449 goto out; 449 450 break; ··· 476 475 } 477 476 478 477 static const struct amba_id tmc_ids[] = { 479 - { 480 - .id = 0x000bb961, 481 - .mask = 0x000fffff, 482 - }, 483 - { 484 - /* Coresight SoC 600 TMC-ETR/ETS */ 485 - .id = 0x000bb9e8, 486 - .mask = 0x000fffff, 487 - .data = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS, 488 - }, 489 - { 490 - /* Coresight SoC 600 TMC-ETB */ 491 - .id = 0x000bb9e9, 492 - .mask = 0x000fffff, 493 - }, 494 - { 495 - /* Coresight SoC 600 TMC-ETF */ 496 - .id = 0x000bb9ea, 497 - .mask = 0x000fffff, 498 - }, 478 + CS_AMBA_ID(0x000bb961), 479 + /* Coresight SoC 600 TMC-ETR/ETS */ 480 + CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS), 481 + /* Coresight SoC 600 TMC-ETB */ 482 + CS_AMBA_ID(0x000bb9e9), 483 + /* Coresight SoC 600 TMC-ETF */ 484 + CS_AMBA_ID(0x000bb9ea), 499 485 { 0, 0}, 500 486 }; 501 487
+39
include/linux/amba/bus.h
··· 25 25 #define AMBA_CID 0xb105f00d 26 26 #define CORESIGHT_CID 0xb105900d 27 27 28 + /* 29 + * CoreSight Architecture specification updates the ID specification 30 + * for components on the AMBA bus. (ARM IHI 0029E) 31 + * 32 + * Bits 15:12 of the CID are the device class. 33 + * 34 + * Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above) 35 + * Class 0x9 defines the component as CoreSight (CORESIGHT_CID above) 36 + * Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support 37 + * at present. 38 + * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved. 39 + * 40 + * Remaining CID bits stay as 0xb105-00d 41 + */ 42 + 43 + /** 44 + * Class 0x9 components use additional values to form a Unique Component 45 + * Identifier (UCI), where peripheral ID values are identical for different 46 + * components. Passed to the amba bus code from the component driver via 47 + * the amba_id->data pointer. 48 + * @devarch : coresight devarch register value 49 + * @devarch_mask: mask bits used for matching. 0 indicates UCI not used. 50 + * @devtype : coresight device type value 51 + * @data : additional driver data. As we have usurped the original 52 + * pointer some devices may still need additional data 53 + */ 54 + struct amba_cs_uci_id { 55 + unsigned int devarch; 56 + unsigned int devarch_mask; 57 + unsigned int devtype; 58 + void *data; 59 + }; 60 + 61 + /* define offsets for registers used by UCI */ 62 + #define UCI_REG_DEVTYPE_OFFSET 0xFCC 63 + #define UCI_REG_DEVARCH_OFFSET 0xFBC 64 + 28 65 struct clk; 29 66 30 67 struct amba_device { ··· 69 32 struct resource res; 70 33 struct clk *pclk; 71 34 unsigned int periphid; 35 + unsigned int cid; 36 + struct amba_cs_uci_id uci; 72 37 unsigned int irq[AMBA_NR_IRQS]; 73 38 char *driver_override; 74 39 };
+1 -1
lib/raid6/Makefile
··· 39 39 ifeq ($(CONFIG_KERNEL_MODE_NEON),y) 40 40 NEON_FLAGS := -ffreestanding 41 41 ifeq ($(ARCH),arm) 42 - NEON_FLAGS += -mfloat-abi=softfp -mfpu=neon 42 + NEON_FLAGS += -march=armv7-a -mfloat-abi=softfp -mfpu=neon 43 43 endif 44 44 CFLAGS_recov_neon_inner.o += $(NEON_FLAGS) 45 45 ifeq ($(ARCH),arm64)