Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i2c: tegra: Add logic to support different register offsets
Tegra410 use different offsets for existing I2C registers, update
the logic to use appropriate offsets per SoC.
As the register offsets are now defined in the SoC-specific
tegra_i2c_regs structures, the tegra_i2c_reg_addr() function is no
longer needed to translate register offsets and has been removed.
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260324055843.549808-3-kkartik@nvidia.com
authored by
Kartik Rajput
and committed by
Andi Shyti
0c0e440b
4eeb19aa
+235
-120
+235
-120
drivers/i2c/busses/i2c-tegra.c
+235
-120
drivers/i2c/busses/i2c-tegra.c
···
30
30
31
31
#define BYTES_PER_FIFO_WORD 4
32
32
33
-
#define I2C_CNFG 0x000
34
33
#define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
35
34
#define I2C_CNFG_PACKET_MODE_EN BIT(10)
36
35
#define I2C_CNFG_NEW_MASTER_FSM BIT(11)
37
36
#define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
38
-
#define I2C_STATUS 0x01c
39
-
#define I2C_SL_CNFG 0x020
37
+
40
38
#define I2C_SL_CNFG_NACK BIT(1)
41
39
#define I2C_SL_CNFG_NEWSL BIT(2)
42
-
#define I2C_SL_ADDR1 0x02c
43
-
#define I2C_SL_ADDR2 0x030
44
-
#define I2C_TLOW_SEXT 0x034
45
-
#define I2C_TX_FIFO 0x050
46
-
#define I2C_RX_FIFO 0x054
47
-
#define I2C_PACKET_TRANSFER_STATUS 0x058
48
-
#define I2C_FIFO_CONTROL 0x05c
40
+
49
41
#define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
50
42
#define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
51
43
#define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52
44
#define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
53
-
#define I2C_FIFO_STATUS 0x060
45
+
54
46
#define I2C_FIFO_STATUS_TX GENMASK(7, 4)
55
47
#define I2C_FIFO_STATUS_RX GENMASK(3, 0)
56
-
#define I2C_INT_MASK 0x064
57
-
#define I2C_INT_STATUS 0x068
48
+
58
49
#define I2C_INT_BUS_CLR_DONE BIT(11)
59
50
#define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
60
51
#define I2C_INT_NO_ACK BIT(3)
61
52
#define I2C_INT_ARBITRATION_LOST BIT(2)
62
53
#define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
63
54
#define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
64
-
#define I2C_CLK_DIVISOR 0x06c
55
+
65
56
#define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
66
57
#define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
67
58
···
85
94
#define I2C_HEADER_CONTINUE_XFER BIT(15)
86
95
#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
87
96
88
-
#define I2C_BUS_CLEAR_CNFG 0x084
89
97
#define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
90
98
#define I2C_BC_STOP_COND BIT(2)
91
99
#define I2C_BC_TERMINATE BIT(1)
92
100
#define I2C_BC_ENABLE BIT(0)
93
-
#define I2C_BUS_CLEAR_STATUS 0x088
101
+
94
102
#define I2C_BC_STATUS BIT(0)
95
103
96
-
#define I2C_CONFIG_LOAD 0x08c
97
104
#define I2C_MSTR_CONFIG_LOAD BIT(0)
98
105
99
-
#define I2C_CLKEN_OVERRIDE 0x090
100
106
#define I2C_MST_CORE_CLKEN_OVR BIT(0)
101
107
102
-
#define I2C_INTERFACE_TIMING_0 0x094
103
-
#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
104
-
#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
105
-
#define I2C_INTERFACE_TIMING_1 0x098
106
-
#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
107
-
#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
108
-
#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
109
-
#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
108
+
#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
109
+
#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
110
+
#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
111
+
#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
112
+
#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
113
+
#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
110
114
111
-
#define I2C_HS_INTERFACE_TIMING_0 0x09c
112
-
#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
113
-
#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
114
-
#define I2C_HS_INTERFACE_TIMING_1 0x0a0
115
-
#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
116
-
#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
117
-
#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
115
+
#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
116
+
#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
117
+
#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
118
+
#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
119
+
#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
118
120
119
-
#define I2C_MST_FIFO_CONTROL 0x0b4
120
121
#define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
121
122
#define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
122
123
#define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
123
124
#define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
124
125
125
-
#define I2C_MST_FIFO_STATUS 0x0b8
126
126
#define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
127
127
#define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
128
128
129
-
#define I2C_MASTER_RESET_CNTRL 0x0a8
130
-
131
-
#define I2C_SW_MUTEX 0x0ec
132
129
#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)
133
130
#define I2C_SW_MUTEX_GRANT GENMASK(7, 4)
134
131
#define I2C_SW_MUTEX_ID_CCPLEX 9
···
137
158
* I2C_PACKET_HEADER_SIZE.
138
159
*/
139
160
#define I2C_PIO_MODE_PREFERRED_LEN 32
161
+
162
+
struct tegra_i2c_regs {
163
+
unsigned int cnfg;
164
+
unsigned int status;
165
+
unsigned int sl_cnfg;
166
+
unsigned int sl_addr1;
167
+
unsigned int sl_addr2;
168
+
unsigned int tlow_sext;
169
+
unsigned int tx_fifo;
170
+
unsigned int rx_fifo;
171
+
unsigned int packet_transfer_status;
172
+
unsigned int fifo_control;
173
+
unsigned int fifo_status;
174
+
unsigned int int_mask;
175
+
unsigned int int_status;
176
+
unsigned int clk_divisor;
177
+
unsigned int bus_clear_cnfg;
178
+
unsigned int bus_clear_status;
179
+
unsigned int config_load;
180
+
unsigned int clken_override;
181
+
unsigned int interface_timing_0;
182
+
unsigned int interface_timing_1;
183
+
unsigned int hs_interface_timing_0;
184
+
unsigned int hs_interface_timing_1;
185
+
unsigned int master_reset_cntrl;
186
+
unsigned int mst_fifo_control;
187
+
unsigned int mst_fifo_status;
188
+
unsigned int sw_mutex;
189
+
};
190
+
191
+
static const struct tegra_i2c_regs tegra20_i2c_regs = {
192
+
.cnfg = 0x000,
193
+
.status = 0x01c,
194
+
.sl_cnfg = 0x020,
195
+
.sl_addr1 = 0x02c,
196
+
.sl_addr2 = 0x030,
197
+
.tx_fifo = 0x050,
198
+
.rx_fifo = 0x054,
199
+
.packet_transfer_status = 0x058,
200
+
.fifo_control = 0x05c,
201
+
.fifo_status = 0x060,
202
+
.int_mask = 0x064,
203
+
.int_status = 0x068,
204
+
.clk_divisor = 0x06c,
205
+
.bus_clear_cnfg = 0x084,
206
+
.bus_clear_status = 0x088,
207
+
.config_load = 0x08c,
208
+
.clken_override = 0x090,
209
+
.interface_timing_0 = 0x094,
210
+
.interface_timing_1 = 0x098,
211
+
.hs_interface_timing_0 = 0x09c,
212
+
.hs_interface_timing_1 = 0x0a0,
213
+
.master_reset_cntrl = 0x0a8,
214
+
.mst_fifo_control = 0x0b4,
215
+
.mst_fifo_status = 0x0b8,
216
+
};
217
+
218
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
219
+
static const struct tegra_i2c_regs tegra20_dvc_i2c_regs = {
220
+
.cnfg = 0x040,
221
+
.status = 0x05c,
222
+
.tx_fifo = 0x060,
223
+
.rx_fifo = 0x064,
224
+
.packet_transfer_status = 0x068,
225
+
.fifo_control = 0x06c,
226
+
.fifo_status = 0x070,
227
+
.int_mask = 0x074,
228
+
.int_status = 0x078,
229
+
.clk_divisor = 0x07c,
230
+
.bus_clear_cnfg = 0x094,
231
+
.bus_clear_status = 0x098,
232
+
.config_load = 0x09c,
233
+
.clken_override = 0x0a0,
234
+
.interface_timing_0 = 0x0a4,
235
+
.interface_timing_1 = 0x0a8,
236
+
.hs_interface_timing_0 = 0x0ac,
237
+
.hs_interface_timing_1 = 0x0b0,
238
+
.master_reset_cntrl = 0x0b8,
239
+
.mst_fifo_control = 0x0c4,
240
+
.mst_fifo_status = 0x0c8,
241
+
};
242
+
#endif
243
+
244
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
245
+
static const struct tegra_i2c_regs tegra210_vi_i2c_regs = {
246
+
.cnfg = 0x0c00,
247
+
.status = 0x0c70,
248
+
.tlow_sext = 0x0cd0,
249
+
.tx_fifo = 0x0d40,
250
+
.rx_fifo = 0x0d50,
251
+
.packet_transfer_status = 0x0d60,
252
+
.fifo_control = 0x0d70,
253
+
.fifo_status = 0x0d80,
254
+
.int_mask = 0x0d90,
255
+
.int_status = 0x0da0,
256
+
.clk_divisor = 0x0db0,
257
+
.bus_clear_cnfg = 0x0e10,
258
+
.bus_clear_status = 0x0e20,
259
+
.config_load = 0x0e30,
260
+
.clken_override = 0x0e40,
261
+
.interface_timing_0 = 0x0e50,
262
+
.interface_timing_1 = 0x0e60,
263
+
.hs_interface_timing_0 = 0x0e70,
264
+
.hs_interface_timing_1 = 0x0e80,
265
+
.master_reset_cntrl = 0x0ea0,
266
+
.mst_fifo_control = 0x0ed0,
267
+
.mst_fifo_status = 0x0ee0,
268
+
};
269
+
#endif
270
+
271
+
static const struct tegra_i2c_regs tegra264_i2c_regs = {
272
+
.cnfg = 0x000,
273
+
.status = 0x01c,
274
+
.sl_cnfg = 0x020,
275
+
.sl_addr1 = 0x02c,
276
+
.sl_addr2 = 0x030,
277
+
.tx_fifo = 0x050,
278
+
.rx_fifo = 0x054,
279
+
.packet_transfer_status = 0x058,
280
+
.fifo_control = 0x05c,
281
+
.fifo_status = 0x060,
282
+
.int_mask = 0x064,
283
+
.int_status = 0x068,
284
+
.clk_divisor = 0x06c,
285
+
.bus_clear_cnfg = 0x084,
286
+
.bus_clear_status = 0x088,
287
+
.config_load = 0x08c,
288
+
.clken_override = 0x090,
289
+
.interface_timing_0 = 0x094,
290
+
.interface_timing_1 = 0x098,
291
+
.hs_interface_timing_0 = 0x09c,
292
+
.hs_interface_timing_1 = 0x0a0,
293
+
.master_reset_cntrl = 0x0a8,
294
+
.mst_fifo_control = 0x0b4,
295
+
.mst_fifo_status = 0x0b8,
296
+
.sw_mutex = 0x0ec,
297
+
};
140
298
141
299
/*
142
300
* msg_end_type: The bus control which needs to be sent at end of transfer.
···
352
236
* @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
353
237
* @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
354
238
* @variant: This represents the I2C controller variant.
239
+
* @regs: Register offsets for the specific SoC variant.
355
240
*/
356
241
struct tegra_i2c_hw_feature {
357
242
bool has_continue_xfer_support;
···
385
268
bool enable_hs_mode_support;
386
269
bool has_mutex;
387
270
enum tegra_i2c_variant variant;
271
+
const struct tegra_i2c_regs *regs;
388
272
};
389
273
390
274
/**
···
469
351
return readl_relaxed(i2c_dev->base + reg);
470
352
}
471
353
472
-
/*
473
-
* If necessary, i2c_writel() and i2c_readl() will offset the register
474
-
* in order to talk to the I2C block inside the DVC block.
475
-
*/
476
-
static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
477
-
{
478
-
if (IS_DVC(i2c_dev))
479
-
reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
480
-
else if (IS_VI(i2c_dev))
481
-
reg = 0xc00 + (reg << 2);
482
-
483
-
return reg;
484
-
}
485
-
486
354
static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
487
355
{
488
-
writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
356
+
writel_relaxed(val, i2c_dev->base + reg);
489
357
490
358
/* read back register to make sure that register writes completed */
491
-
if (reg != I2C_TX_FIFO)
492
-
readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
359
+
if (reg != i2c_dev->hw->regs->tx_fifo)
360
+
readl_relaxed(i2c_dev->base + reg);
493
361
else if (IS_VI(i2c_dev))
494
-
readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
362
+
readl_relaxed(i2c_dev->base + i2c_dev->hw->regs->int_status);
495
363
}
496
364
497
365
static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
498
366
{
499
-
return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
367
+
return readl_relaxed(i2c_dev->base + reg);
500
368
}
501
369
502
370
static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
503
371
unsigned int reg, unsigned int len)
504
372
{
505
-
writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
373
+
writesl(i2c_dev->base + reg, data, len);
506
374
}
507
375
508
376
static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
···
509
405
static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
510
406
unsigned int reg, unsigned int len)
511
407
{
512
-
readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
408
+
readsl(i2c_dev->base + reg, data, len);
513
409
}
514
410
515
411
static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev)
516
412
{
517
-
unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
413
+
unsigned int reg = i2c_dev->hw->regs->sw_mutex;
518
414
u32 val, id;
519
415
520
416
val = readl(i2c_dev->base + reg);
···
525
421
526
422
static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
527
423
{
528
-
unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
424
+
unsigned int reg = i2c_dev->hw->regs->sw_mutex;
529
425
u32 val, id;
530
426
531
427
val = readl(i2c_dev->base + reg);
···
563
459
564
460
static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
565
461
{
566
-
unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
462
+
unsigned int reg = i2c_dev->hw->regs->sw_mutex;
567
463
u32 val, id;
568
464
569
465
if (!i2c_dev->hw->has_mutex)
···
586
482
{
587
483
u32 int_mask;
588
484
589
-
int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
590
-
i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
485
+
int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) & ~mask;
486
+
i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask);
591
487
}
592
488
593
489
static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
594
490
{
595
491
u32 int_mask;
596
492
597
-
int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
598
-
i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
493
+
int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) | mask;
494
+
i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask);
599
495
}
600
496
601
497
static void tegra_i2c_dma_complete(void *args)
···
739
635
740
636
value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
741
637
FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
742
-
i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
638
+
i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_0);
743
639
744
640
value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
745
641
FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
746
642
FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
747
643
FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
748
-
i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
644
+
i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_1);
749
645
750
646
value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
751
647
FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
752
-
i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
648
+
i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_0);
753
649
754
650
value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
755
651
FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
756
652
FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
757
-
i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
653
+
i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_1);
758
654
759
655
value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
760
-
i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
656
+
i2c_writel(i2c_dev, value, i2c_dev->hw->regs->bus_clear_cnfg);
761
657
762
-
i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
658
+
i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->tlow_sext);
763
659
}
764
660
765
661
static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
766
662
u32 reg, u32 mask, u32 delay_us,
767
663
u32 timeout_us)
768
664
{
769
-
void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
665
+
void __iomem *addr = i2c_dev->base + reg;
770
666
u32 val;
771
667
772
668
if (!i2c_dev->atomic_mode)
···
785
681
if (i2c_dev->hw->has_mst_fifo) {
786
682
mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
787
683
I2C_MST_FIFO_CONTROL_RX_FLUSH;
788
-
offset = I2C_MST_FIFO_CONTROL;
684
+
offset = i2c_dev->hw->regs->mst_fifo_control;
789
685
} else {
790
686
mask = I2C_FIFO_CONTROL_TX_FLUSH |
791
687
I2C_FIFO_CONTROL_RX_FLUSH;
792
-
offset = I2C_FIFO_CONTROL;
688
+
offset = i2c_dev->hw->regs->fifo_control;
793
689
}
794
690
795
691
val = i2c_readl(i2c_dev, offset);
···
812
708
if (!i2c_dev->hw->has_config_load_reg)
813
709
return 0;
814
710
815
-
i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
711
+
i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, i2c_dev->hw->regs->config_load);
816
712
817
-
err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
713
+
err = tegra_i2c_poll_register(i2c_dev, i2c_dev->hw->regs->config_load, 0xffffffff,
818
714
1000, I2C_CONFIG_LOAD_TIMEOUT);
819
715
if (err) {
820
716
dev_err(i2c_dev->dev, "failed to load config\n");
···
835
731
* SW needs to wait for 2us after assertion and de-assertion of this soft
836
732
* reset.
837
733
*/
838
-
i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL);
734
+
i2c_writel(i2c_dev, 0x1, i2c_dev->hw->regs->master_reset_cntrl);
839
735
fsleep(2);
840
736
841
-
i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL);
737
+
i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->master_reset_cntrl);
842
738
fsleep(2);
843
739
844
740
return 0;
···
880
776
if (i2c_dev->hw->has_multi_master_mode)
881
777
val |= I2C_CNFG_MULTI_MASTER_MODE;
882
778
883
-
i2c_writel(i2c_dev, val, I2C_CNFG);
884
-
i2c_writel(i2c_dev, 0, I2C_INT_MASK);
779
+
i2c_writel(i2c_dev, val, i2c_dev->hw->regs->cnfg);
780
+
i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->int_mask);
885
781
886
782
if (IS_VI(i2c_dev))
887
783
tegra_i2c_vi_init(i2c_dev);
···
926
822
clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
927
823
i2c_dev->hw->clk_divisor_hs_mode) |
928
824
FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
929
-
i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
825
+
i2c_writel(i2c_dev, clk_divisor, i2c_dev->hw->regs->clk_divisor);
930
826
931
827
if (i2c_dev->hw->has_interface_timing_reg) {
932
828
val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
933
829
FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
934
-
i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
830
+
i2c_writel(i2c_dev, val, i2c_dev->hw->regs->interface_timing_0);
935
831
}
936
832
937
833
/*
···
939
835
* Otherwise, preserve the chip default values.
940
836
*/
941
837
if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
942
-
i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
838
+
i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->interface_timing_1);
943
839
944
840
/* Write HS mode registers. These will get used only for HS mode*/
945
841
if (i2c_dev->hw->enable_hs_mode_support) {
···
949
845
950
846
val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
951
847
FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
952
-
i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0);
953
-
i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1);
848
+
i2c_writel(i2c_dev, val, i2c_dev->hw->regs->hs_interface_timing_0);
849
+
i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->hs_interface_timing_1);
954
850
}
955
851
956
852
clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
···
963
859
}
964
860
965
861
if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
966
-
u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
862
+
u32 sl_cfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->sl_cnfg);
967
863
968
864
sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
969
-
i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
970
-
i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
971
-
i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
865
+
i2c_writel(i2c_dev, sl_cfg, i2c_dev->hw->regs->sl_cnfg);
866
+
i2c_writel(i2c_dev, 0xfc, i2c_dev->hw->regs->sl_addr1);
867
+
i2c_writel(i2c_dev, 0x00, i2c_dev->hw->regs->sl_addr2);
972
868
}
973
869
974
870
err = tegra_i2c_flush_fifos(i2c_dev);
···
976
872
return err;
977
873
978
874
if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
979
-
i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
875
+
i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, i2c_dev->hw->regs->clken_override);
980
876
981
877
err = tegra_i2c_wait_for_config_load(i2c_dev);
982
878
if (err)
···
997
893
*/
998
894
udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
999
895
1000
-
cnfg = i2c_readl(i2c_dev, I2C_CNFG);
896
+
cnfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg);
1001
897
if (cnfg & I2C_CNFG_PACKET_MODE_EN)
1002
-
i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
898
+
i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, i2c_dev->hw->regs->cnfg);
1003
899
1004
900
return tegra_i2c_wait_for_config_load(i2c_dev);
1005
901
}
···
1019
915
return -EINVAL;
1020
916
1021
917
if (i2c_dev->hw->has_mst_fifo) {
1022
-
val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
918
+
val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status);
1023
919
rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
1024
920
} else {
1025
-
val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
921
+
val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status);
1026
922
rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
1027
923
}
1028
924
···
1031
927
if (words_to_transfer > rx_fifo_avail)
1032
928
words_to_transfer = rx_fifo_avail;
1033
929
1034
-
i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
930
+
i2c_readsl(i2c_dev, buf, i2c_dev->hw->regs->rx_fifo, words_to_transfer);
1035
931
1036
932
buf += words_to_transfer * BYTES_PER_FIFO_WORD;
1037
933
buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
···
1047
943
* when (words_to_transfer was > rx_fifo_avail) earlier
1048
944
* in this function.
1049
945
*/
1050
-
val = i2c_readl(i2c_dev, I2C_RX_FIFO);
946
+
val = i2c_readl(i2c_dev, i2c_dev->hw->regs->rx_fifo);
1051
947
val = cpu_to_le32(val);
1052
948
memcpy(buf, &val, buf_remaining);
1053
949
buf_remaining = 0;
···
1072
968
u32 val;
1073
969
1074
970
if (i2c_dev->hw->has_mst_fifo) {
1075
-
val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
971
+
val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status);
1076
972
tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
1077
973
} else {
1078
-
val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
974
+
val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status);
1079
975
tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
1080
976
}
1081
977
···
1106
1002
i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
1107
1003
1108
1004
if (IS_VI(i2c_dev))
1109
-
i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
1005
+
i2c_writesl_vi(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer);
1110
1006
else
1111
-
i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
1007
+
i2c_writesl(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer);
1112
1008
1113
1009
buf += words_to_transfer * BYTES_PER_FIFO_WORD;
1114
1010
}
···
1130
1026
i2c_dev->msg_buf_remaining = 0;
1131
1027
i2c_dev->msg_buf = NULL;
1132
1028
1133
-
i2c_writel(i2c_dev, val, I2C_TX_FIFO);
1029
+
i2c_writel(i2c_dev, val, i2c_dev->hw->regs->tx_fifo);
1134
1030
}
1135
1031
1136
1032
return 0;
···
1142
1038
struct tegra_i2c_dev *i2c_dev = dev_id;
1143
1039
u32 status;
1144
1040
1145
-
status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1041
+
status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status);
1146
1042
1147
1043
if (status == 0) {
1148
1044
dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
1149
-
i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
1150
-
i2c_readl(i2c_dev, I2C_STATUS),
1151
-
i2c_readl(i2c_dev, I2C_CNFG));
1045
+
i2c_readl(i2c_dev, i2c_dev->hw->regs->packet_transfer_status),
1046
+
i2c_readl(i2c_dev, i2c_dev->hw->regs->status),
1047
+
i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg));
1152
1048
i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1153
1049
goto err;
1154
1050
}
···
1191
1087
}
1192
1088
}
1193
1089
1194
-
i2c_writel(i2c_dev, status, I2C_INT_STATUS);
1090
+
i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status);
1195
1091
if (IS_DVC(i2c_dev))
1196
1092
dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1197
1093
···
1229
1125
if (i2c_dev->hw->supports_bus_clear)
1230
1126
tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1231
1127
1232
-
i2c_writel(i2c_dev, status, I2C_INT_STATUS);
1128
+
i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status);
1233
1129
1234
1130
if (IS_DVC(i2c_dev))
1235
1131
dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
···
1252
1148
int err;
1253
1149
1254
1150
if (i2c_dev->hw->has_mst_fifo)
1255
-
reg = I2C_MST_FIFO_CONTROL;
1151
+
reg = i2c_dev->hw->regs->mst_fifo_control;
1256
1152
else
1257
-
reg = I2C_FIFO_CONTROL;
1153
+
reg = i2c_dev->hw->regs->fifo_control;
1258
1154
1259
1155
if (i2c_dev->dma_mode) {
1260
1156
if (len & 0xF)
···
1265
1161
dma_burst = 8;
1266
1162
1267
1163
if (i2c_dev->msg_read) {
1268
-
reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1164
+
reg_offset = i2c_dev->hw->regs->rx_fifo;
1269
1165
1270
1166
slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1271
1167
slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
···
1276
1172
else
1277
1173
val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1278
1174
} else {
1279
-
reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1175
+
reg_offset = i2c_dev->hw->regs->tx_fifo;
1280
1176
1281
1177
slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1282
1178
slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
···
1319
1215
ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1320
1216
1321
1217
do {
1322
-
u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1218
+
u32 status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status);
1323
1219
1324
1220
if (status)
1325
1221
tegra_i2c_isr(i2c_dev->irq, i2c_dev);
···
1378
1274
1379
1275
val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1380
1276
I2C_BC_TERMINATE;
1381
-
i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1277
+
i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg);
1382
1278
1383
1279
err = tegra_i2c_wait_for_config_load(i2c_dev);
1384
1280
if (err)
1385
1281
return err;
1386
1282
1387
1283
val |= I2C_BC_ENABLE;
1388
-
i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1284
+
i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg);
1389
1285
tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1390
1286
1391
1287
time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
···
1396
1292
return -ETIMEDOUT;
1397
1293
}
1398
1294
1399
-
val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1295
+
val = i2c_readl(i2c_dev, i2c_dev->hw->regs->bus_clear_status);
1400
1296
if (!(val & I2C_BC_STATUS)) {
1401
1297
dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1402
1298
return -EIO;
···
1421
1317
if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1422
1318
*dma_buf++ = packet_header;
1423
1319
else
1424
-
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1320
+
i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1425
1321
1426
1322
packet_header = i2c_dev->msg_len - 1;
1427
1323
1428
1324
if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1429
1325
*dma_buf++ = packet_header;
1430
1326
else
1431
-
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1327
+
i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1432
1328
1433
1329
packet_header = I2C_HEADER_IE_ENABLE;
1434
1330
···
1456
1352
if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1457
1353
*dma_buf++ = packet_header;
1458
1354
else
1459
-
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1355
+
i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1460
1356
}
1461
1357
1462
1358
static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
···
1577
1473
1578
1474
tegra_i2c_unmask_irq(i2c_dev, int_mask);
1579
1475
dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1580
-
i2c_readl(i2c_dev, I2C_INT_MASK));
1476
+
i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask));
1581
1477
1582
1478
if (i2c_dev->dma_mode) {
1583
1479
time_left = tegra_i2c_wait_completion(i2c_dev,
···
1752
1648
.enable_hs_mode_support = false,
1753
1649
.has_mutex = false,
1754
1650
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1651
+
.regs = &tegra20_i2c_regs,
1755
1652
};
1756
1653
1757
1654
#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
···
1785
1680
.enable_hs_mode_support = false,
1786
1681
.has_mutex = false,
1787
1682
.variant = TEGRA_I2C_VARIANT_DVC,
1683
+
.regs = &tegra20_dvc_i2c_regs,
1788
1684
};
1789
1685
#endif
1790
1686
···
1818
1712
.enable_hs_mode_support = false,
1819
1713
.has_mutex = false,
1820
1714
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1715
+
.regs = &tegra20_i2c_regs,
1821
1716
};
1822
1717
1823
1718
static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
···
1850
1743
.enable_hs_mode_support = false,
1851
1744
.has_mutex = false,
1852
1745
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1746
+
.regs = &tegra20_i2c_regs,
1853
1747
};
1854
1748
1855
1749
static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
···
1882
1774
.enable_hs_mode_support = false,
1883
1775
.has_mutex = false,
1884
1776
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1777
+
.regs = &tegra20_i2c_regs,
1885
1778
};
1886
1779
1887
1780
static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
···
1914
1805
.enable_hs_mode_support = false,
1915
1806
.has_mutex = false,
1916
1807
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1808
+
.regs = &tegra20_i2c_regs,
1917
1809
};
1918
1810
1919
1811
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
···
1947
1837
.enable_hs_mode_support = false,
1948
1838
.has_mutex = false,
1949
1839
.variant = TEGRA_I2C_VARIANT_VI,
1840
+
.regs = &tegra210_vi_i2c_regs,
1950
1841
};
1951
1842
#endif
1952
1843
···
1980
1869
.enable_hs_mode_support = false,
1981
1870
.has_mutex = false,
1982
1871
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1872
+
.regs = &tegra20_i2c_regs,
1983
1873
};
1984
1874
1985
1875
static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
···
2014
1902
.enable_hs_mode_support = true,
2015
1903
.has_mutex = false,
2016
1904
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1905
+
.regs = &tegra20_i2c_regs,
2017
1906
};
2018
1907
2019
1908
static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
···
2048
1935
.enable_hs_mode_support = true,
2049
1936
.has_mutex = true,
2050
1937
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1938
+
.regs = &tegra264_i2c_regs,
2051
1939
};
2052
1940
2053
1941
static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
···
2082
1968
.enable_hs_mode_support = true,
2083
1969
.has_mutex = true,
2084
1970
.variant = TEGRA_I2C_VARIANT_DEFAULT,
1971
+
.regs = &tegra264_i2c_regs,
2085
1972
};
2086
1973
2087
1974
static const struct of_device_id tegra_i2c_of_match[] = {