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drm/msm/a6xx: Switch to preemption safe AO counter

CP_ALWAYS_ON_COUNTER is not save-restored during preemption, so it won't
provide accurate data about the 'submit' when preemption is enabled.
Switch to CP_ALWAYS_ON_CONTEXT which is preemption safe.

Fixes: e7ae83da4a28 ("drm/msm/a6xx: Implement preemption for a7xx targets")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714657/
Message-ID: <20260327-a8xx-gpu-batch2-v2-3-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark 0c59f258 cfc8b486

+7 -7
+7 -7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 347 347 * GPU registers so we need to add 0x1a800 to the register value on A630 348 348 * to get the right value from PM4. 349 349 */ 350 - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 350 + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT, 351 351 rbmemptr_stats(ring, index, alwayson_start)); 352 352 353 353 /* Invalidate CCU depth and color */ ··· 388 388 389 389 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 390 390 rbmemptr_stats(ring, index, cpcycles_end)); 391 - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 391 + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT, 392 392 rbmemptr_stats(ring, index, alwayson_end)); 393 393 394 394 /* Write the fence to the scratch register */ ··· 457 457 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 458 458 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 459 459 struct msm_ringbuffer *ring = submit->ring; 460 - u32 rbbm_perfctr_cp0, cp_always_on_counter; 460 + u32 rbbm_perfctr_cp0, cp_always_on_context; 461 461 unsigned int i, ibs = 0; 462 462 463 463 adreno_check_and_reenable_stall(adreno_gpu); ··· 480 480 481 481 if (adreno_is_a8xx(adreno_gpu)) { 482 482 rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0); 483 - cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_COUNTER; 483 + cp_always_on_context = REG_A8XX_CP_ALWAYS_ON_CONTEXT; 484 484 } else { 485 485 rbbm_perfctr_cp0 = REG_A7XX_RBBM_PERFCTR_CP(0); 486 - cp_always_on_counter = REG_A6XX_CP_ALWAYS_ON_COUNTER; 486 + cp_always_on_context = REG_A6XX_CP_ALWAYS_ON_CONTEXT; 487 487 } 488 488 489 489 get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_start)); 490 - get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index, alwayson_start)); 490 + get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring, index, alwayson_start)); 491 491 492 492 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 493 493 OUT_RING(ring, CP_SET_THREAD_BOTH); ··· 535 535 } 536 536 537 537 get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_end)); 538 - get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index, alwayson_end)); 538 + get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring, index, alwayson_end)); 539 539 540 540 /* Write the fence to the scratch register */ 541 541 if (adreno_is_a8xx(adreno_gpu)) {